};
/* infracfg */
-#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
-#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL)
static const struct mtk_parent infra_mux1_parents[] = {
XTAL_PARENT(CLK_XTAL),
[CLK_PERI_FCI] = 48,
};
-#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
-#define XTAL_PARENT(_id) PARENT(_id, CLK_PARENT_XTAL)
-
static const struct mtk_parent uart_ck_sel_parents[] = {
XTAL_PARENT(CLK_XTAL),
TOP_PARENT(CLK_TOP_UART_SEL),
};
/* INFRASYS MUX PARENTS */
-#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS)
-#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
-#define VOID_PARENT PARENT(-1, 0)
static const struct mtk_parent infra_uart0_parents[] = {
TOP_PARENT(CLK_TOP_F26M_SEL),
#define MT7986_CLK_PDN 0x250
#define MT7986_CLK_PDN_EN_WRITE BIT(31)
-#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
-#define INFRA_PARENT(_id) PARENT(_id, CLK_PARENT_INFRASYS)
-#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
-#define VOID_PARENT PARENT(-1, 0)
-
#define FIXED_CLK0(_id, _rate) \
FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
};
/* TOPCKGEN MUX PARENTS */
-#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
-#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
/* CLK_TOP_NETSYS_SEL (netsys_sel) in topckgen */
static const struct mtk_parent netsys_parents[] = {
};
/* TOPCKGEN MUX PARENTS */
-#define APMIXED_PARENT(_id) PARENT(_id, CLK_PARENT_APMIXED)
-#define TOP_PARENT(_id) PARENT(_id, CLK_PARENT_TOPCKGEN)
static const struct mtk_parent netsys_parents[] = {
TOP_PARENT(CLK_TOP_XTAL), TOP_PARENT(CLK_TOP_NET2PLL_D2),
FACTOR1(CLK_TOP_OSC_D20, CLK_PAD_ULPOSC, 1, 20),
};
-#define EXT_PARENT(id) PARENT(id, CLK_PARENT_EXT)
-#define APMIXED_PARENT(id) PARENT(id, CLK_PARENT_APMIXED)
-#define TOP_PARENT(id) PARENT(id, CLK_PARENT_TOPCKGEN)
-
static const struct mtk_parent axi_parents[] = {
EXT_PARENT(CLK_PAD_CLK26M),
TOP_PARENT(CLK_TOP_MAINPLL_D4_D4),
.flags = _flags, \
}
+#define APMIXED_PARENT(id) PARENT(id, CLK_PARENT_APMIXED)
+#define TOP_PARENT(id) PARENT(id, CLK_PARENT_TOPCKGEN)
+#define INFRA_PARENT(id) PARENT(id, CLK_PARENT_INFRASYS)
+#define XTAL_PARENT(id) PARENT(id, CLK_PARENT_XTAL)
+#define EXT_PARENT(id) PARENT(id, CLK_PARENT_EXT)
+#define VOID_PARENT PARENT(-1, 0)
+
/**
* struct mtk_composite - aggregate clock of mux, divider and gate clocks
*