Move rtpcs_930x_sds_set_power() and rtpcs_930x_sds_rx_reset() out of
rtpcs_930x_sds_apply_ip_mode() and into rtpcs_930x_sds_{de,}activate().
After this, apply_ip_mode is pure IP-mode/CMU/state-machine programming
and the SerDes-core analog power is owned by the outer phase pair, the
same place that already owns the 1G/10G PHY block and fiber RX power.
Behavioural change: USXGMII / QSGMII / XSGMII modes did not previously
go through apply_ip_mode and therefore never had the SerDes-core power
gated on mode transitions. After this commit, every mode transition
power-cycles the SerDes core via the outer deactivate/activate.
For the SGMII / 1000BASE-X / 2500BASE-X / 10GBASE-R path the set of
register writes is unchanged; only the relative ordering vs. the
fiber/PHY power writes shifts: set_power(false) now precedes those
writes (was after), set_power(true) now follows them (was before).
Verified on RTL930x hardware: SGMII, 2500BASE-X, 10GBASE-R, USXGMII-QX
and XSGMII all come up with link, ping and iperf3 throughput as
expected.
Link: https://github.com/openwrt/openwrt/pull/23513
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
* if this sequence should quit early in case of errors.
*/
- rtpcs_930x_sds_set_power(sds, false);
ret = rtpcs_93xx_sds_set_ip_mode(sds, RTPCS_SDS_MODE_OFF);
if (ret < 0)
return ret;
pr_err("%s: SDS %d could not reset state machine\n", __func__,
sds->id);
- rtpcs_930x_sds_set_power(sds, true);
- rtpcs_930x_sds_rx_reset(sds, hw_mode);
return 0;
}
{
int ret;
+ /* Power down the SerDes core analog block. */
+ rtpcs_930x_sds_set_power(sds, false);
+
ret = rtpcs_930x_sds_set_mode(sds, RTPCS_SDS_MODE_OFF);
if (ret)
return ret;
{
int ret;
+ /* Power up the SerDes core analog block and reset its RX path. */
+ rtpcs_930x_sds_set_power(sds, true);
+ rtpcs_930x_sds_rx_reset(sds, sds->hw_mode);
+
/* Enable fiber RX. */
ret = rtpcs_sds_write_bits(sds, 0x20, 2, 12, 12, 0);
if (ret)