clk: samsung: gs101: Fix missing USI7_USI DIV clock in peric0_clk_regs

In the peric0_clk_regs array, the divider register offset for USI6 was
accidentally listed twice, while the divider for USI7 was omitted.

Missing this DIV register causes the USI7 clock divider setting to be
lost and reset to its hardware default value during a suspend/resume
cycle.

Replace the duplicated USI6 DIV entry with the correct USI7 DIV
register.

Fixes: 893f133a040b ("clk: samsung: gs101: add support for cmu_peric0")
Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://patch.msgid.link/20260505171457.1960837-1-visitorckw@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index d2bcd3a9daf8939157640c4e7a00da3d39ac309e..b44bb31f38b30675b7391110d2ed763d5ec92a59 100644 (file)
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -3921,7 +3921,7 @@ static const unsigned long peric0_clk_regs[] __initconst = {
        CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI,
        CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI,
        CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI,
-       CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI,
+       CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI,
        CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI,
        CLK_CON_BUF_CLKBUF_PERIC0_IP,
        CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,