arm64: dts: imx95: Add Root Port node and PERST property

Since describing the PCIe PERST# property under Host Bridge node is now
deprecated, it is recommended to add it to the Root Port node, so
creating the Root Port node and add the reset-gpios property in Root
Port.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
index e4649d7f9122a1f875ee276d4f8c15e06416c8f3..7d820a0f80b22aed8bc699b03b9019178e91d14e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
@@ -553,6 +553,7 @@
 &pcie0 {
        pinctrl-0 = <&pinctrl_pcie0>;
        pinctrl-names = "default";
+       /* This property is deprecated, use reset-gpios from the Root Port node. */
        reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>;
        vpcie-supply = <&reg_m2_pwr>;
        vpcie3v3aux-supply = <&reg_m2_pwr>;
@@ -567,6 +568,10 @@
        status = "disabled";
 };
 
+&pcie0_port0 {
+       reset-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+};
+
 &sai1 {
        assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
                          <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,

diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
index 49400bc9ba919b7096fdd261cca0793782f20198..2e463bc7c60123f7a01ae1df8066f118481b6617 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
@@ -540,6 +540,7 @@
 &pcie0 {
        pinctrl-0 = <&pinctrl_pcie0>;
        pinctrl-names = "default";
+       /* This property is deprecated, use reset-gpios from the Root Port node. */
        reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
        vpcie-supply = <&reg_pcie0>;
        vpcie3v3aux-supply = <&reg_pcie0>;
@@ -554,9 +555,14 @@
        status = "disabled";
 };
 
+&pcie0_port0 {
+       reset-gpios = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>;
+};
+
 &pcie1 {
        pinctrl-0 = <&pinctrl_pcie1>;
        pinctrl-names = "default";
+       /* This property is deprecated, use reset-gpios from the Root Port node. */
        reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
        vpcie-supply = <&reg_slot_pwr>;
        vpcie3v3aux-supply = <&reg_slot_pwr>;
@@ -570,6 +576,10 @@
        status = "disabled";
 };
 
+&pcie1_port0 {
+       reset-gpios = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>;
+};
+
 &sai1 {
        #sound-dai-cells = <0>;
        pinctrl-names = "default";

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 3e35c956a4d7af88310b3dfaef7e3d064f530e07..d2aa6e543a09474c57785b78ca5eb9683a62f119 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1974,6 +1974,17 @@
                        iommu-map-mask = <0x1ff>;
                        fsl,max-link-speed = <3>;
                        status = "disabled";
+
+                       pcie0_port0: pcie@0 {
+                               compatible = "pciclass,0604";
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
                };
 
                pcie0_ep: pcie-ep@4c300000 {
@@ -2051,6 +2062,17 @@
                        iommu-map-mask = <0x1ff>;
                        fsl,max-link-speed = <3>;
                        status = "disabled";
+
+                       pcie1_port0: pcie@0 {
+                               compatible = "pciclass,0604";
+                               device_type = "pci";
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               bus-range = <0x01 0xff>;
+
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               ranges;
+                       };
                };
 
                pcie1_ep: pcie-ep@4c380000 {