5.3-stable patches

added patches:
	clk-at91-fix-update-bit-maps-on-cfg_mor-write.patch
	usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core_reset.patch

diff --git a/queue-5.3/clk-at91-fix-update-bit-maps-on-cfg_mor-write.patch b/queue-5.3/clk-at91-fix-update-bit-maps-on-cfg_mor-write.patch
new file mode 100644 (file)
index 0000000..dc4a2e4
--- /dev/null
+++ b/queue-5.3/clk-at91-fix-update-bit-maps-on-cfg_mor-write.patch
@@ -0,0 +1,38 @@
+From 263eaf8f172d9f44e15d6aca85fe40ec18d2c477 Mon Sep 17 00:00:00 2001
+From: Eugen Hristev <eugen.hristev@microchip.com>
+Date: Mon, 9 Sep 2019 15:30:31 +0000
+Subject: clk: at91: fix update bit maps on CFG_MOR write
+
+From: Eugen Hristev <eugen.hristev@microchip.com>
+
+commit 263eaf8f172d9f44e15d6aca85fe40ec18d2c477 upstream.
+
+The regmap update bits call was not selecting the proper mask, considering
+the bits which was updating.
+Update the mask from call to also include OSCBYPASS.
+Removed MOSCEN which was not updated.
+
+Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally")
+Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
+Link: https://lkml.kernel.org/r/1568042692-11784-1-git-send-email-eugen.hristev@microchip.com
+Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
+Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Lee Jones <lee.jones@linaro.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/clk/at91/clk-main.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/at91/clk-main.c
++++ b/drivers/clk/at91/clk-main.c
+@@ -156,7 +156,7 @@ at91_clk_register_main_osc(struct regmap
+       if (bypass)
+               regmap_update_bits(regmap,
+                                  AT91_CKGR_MOR, MOR_KEY_MASK |
+-                                 AT91_PMC_MOSCEN,
++                                 AT91_PMC_OSCBYPASS,
+                                  AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
+ 
+       hw = &osc->hw;

diff --git a/queue-5.3/series b/queue-5.3/series
index e141d43549f7f3b376da3fee5dba79f877bea6ae..cc0224423ba9bf6b9c72d9715c2a2708c787b333 100644 (file)
--- a/queue-5.3/series
+++ b/queue-5.3/series
@@ -94,3 +94,5 @@ pwm-bcm-iproc-prevent-unloading-the-driver-module-wh.patch
 ice-fix-potential-infinite-loop-because-loop-counter.patch
 iavf-initialize-itrn-registers-with-correct-values.patch
 i40e-fix-for-ethtool-m-issue-on-x722-nic.patch
+clk-at91-fix-update-bit-maps-on-cfg_mor-write.patch
+usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core_reset.patch

diff --git a/queue-5.3/usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core_reset.patch b/queue-5.3/usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core_reset.patch
new file mode 100644 (file)
index 0000000..354501a
--- /dev/null
+++ b/queue-5.3/usb-dwc2-use-a-longer-core-rest-timeout-in-dwc2_core_reset.patch
@@ -0,0 +1,40 @@
+From 6689f0f4bb14e50917ba42eb9b41c25e0184970c Mon Sep 17 00:00:00 2001
+From: Mathias Kresin <dev@kresin.me>
+Date: Sun, 7 Jul 2019 16:22:01 +0200
+Subject: usb: dwc2: use a longer core rest timeout in dwc2_core_reset()
+
+From: Mathias Kresin <dev@kresin.me>
+
+commit 6689f0f4bb14e50917ba42eb9b41c25e0184970c upstream.
+
+Testing on different generations of Lantiq MIPS SoC based boards, showed
+that it takes up to 1500 us until the core reset bit is cleared.
+
+The driver from the vendor SDK (ifxhcd) uses a 1 second timeout. Use the
+same timeout to fix wrong hang detections and make the driver work for
+Lantiq MIPS SoCs.
+
+At least till kernel 4.14 the hanging reset only caused a warning but
+the driver was probed successful. With kernel 4.19 errors out with
+EBUSY.
+
+Cc: linux-stable <stable@vger.kernel.org> # 4.19+
+Signed-off-by: Mathias Kresin <dev@kresin.me>
+Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/usb/dwc2/core.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/usb/dwc2/core.c
++++ b/drivers/usb/dwc2/core.c
+@@ -524,7 +524,7 @@ int dwc2_core_reset(struct dwc2_hsotg *h
+       greset |= GRSTCTL_CSFTRST;
+       dwc2_writel(hsotg, greset, GRSTCTL);
+ 
+-      if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) {
++      if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 10000)) {
+               dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n",
+                        __func__);
+               return -EBUSY;