Add TARGET_MMX_WITH_SSE to the condition of all 64-bit _Float16 vector related patterns.

gcc/ChangeLog:

	PR target/123484
	* config/i386/mmx.md (divv4hf3): Add TARGET_MMX_WITH_SSE to
	the condition.
	(cmlav4hf4): Ditto.
	(cmla_conjv4hf4): Ditto.
	(cmulv4hf3): Ditto.
	(cmul_conjv4hf3): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr123484.c: New test.

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 0525bfdd5615dfb0c9f8963ec57e083d9a642137..a23474716a64e12dd69507a7a7534bb591efa9d2 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -2061,7 +2061,8 @@
        (div:V4HF
          (match_operand:V4HF 1 "nonimmediate_operand")
          (match_operand:V4HF 2 "register_operand")))]
-  "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math"
+  "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math
+  && TARGET_MMX_WITH_SSE"
 {
   rtx op2 = gen_reg_rtx (V8HFmode);
   rtx op1 = gen_reg_rtx (V8HFmode);
@@ -2896,7 +2897,8 @@
    (match_operand:V4HF 1 "vector_operand")
    (match_operand:V4HF 2 "vector_operand")
    (match_operand:V4HF 3 "vector_operand")]
-  "TARGET_AVX512FP16 && TARGET_AVX512VL"
+  "TARGET_AVX512FP16 && TARGET_AVX512VL
+  && TARGET_MMX_WITH_SSE"
 {
   rtx op3 = gen_reg_rtx (V8HFmode);
   rtx op2 = gen_reg_rtx (V8HFmode);
@@ -2918,7 +2920,8 @@
    (match_operand:V4HF 1 "vector_operand")
    (match_operand:V4HF 2 "vector_operand")
    (match_operand:V4HF 3 "vector_operand")]
-  "TARGET_AVX512FP16 && TARGET_AVX512VL"
+  "TARGET_AVX512FP16 && TARGET_AVX512VL
+  && TARGET_MMX_WITH_SSE"
 {
   rtx op3 = gen_reg_rtx (V8HFmode);
   rtx op2 = gen_reg_rtx (V8HFmode);
@@ -2939,7 +2942,8 @@
   [(match_operand:V4HF 0 "register_operand")
    (match_operand:V4HF 1 "vector_operand")
    (match_operand:V4HF 2 "vector_operand")]
-  "TARGET_AVX512FP16 && TARGET_AVX512VL"
+  "TARGET_AVX512FP16 && TARGET_AVX512VL
+  && TARGET_MMX_WITH_SSE"
 {
   rtx op2 = gen_reg_rtx (V8HFmode);
   rtx op1 = gen_reg_rtx (V8HFmode);
@@ -2957,7 +2961,8 @@
   [(match_operand:V4HF 0 "register_operand")
    (match_operand:V4HF 1 "vector_operand")
    (match_operand:V4HF 2 "vector_operand")]
-  "TARGET_AVX512FP16 && TARGET_AVX512VL"
+  "TARGET_AVX512FP16 && TARGET_AVX512VL
+  && TARGET_MMX_WITH_SSE"
 {
   rtx op2 = gen_reg_rtx (V8HFmode);
   rtx op1 = gen_reg_rtx (V8HFmode);

diff --git a/gcc/testsuite/gcc.target/i386/pr123484.c b/gcc/testsuite/gcc.target/i386/pr123484.c
new file mode 100644 (file)
index 0000000..258da40
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr123484.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512vl -mavx512fp16 " }*/
+typedef __attribute__((__vector_size__ (8))) _Float16 F;
+int a, b;
+F f, *p;
+
+void
+foo ()
+{
+  do
+    {
+      f /= b ? *p : (F) {40};
+l:
+    }
+  while (a);
+  goto l;
+}