drm/amd/display: Fix compiler warnings

[Why] Implicit conversions from wider integer types to byte-sized fields
were generating compiler warnings. These warnings hide intentional protocol
/storage boundaries and reduce signal quality during builds. Making
conversion intent explicit improves readability and warning hygiene
without changing behavior.

[How] Added explicit, type-safe  casts at intentional narrow-storage
boundaries. Kept data models & runtime logic unchanged, only clarifying
conversion intent.

Functionality and behavior is unchanged; only type intent is explicit.
Aligned warning cleanup with existing coding standards for explicit
boundary conversions.

Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 5267f1a9473bfd06b53944c8569a0ba8cb9fafcc..c94e532ac4a4bf5b40724bb8351944075d10e739 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1061,9 +1061,11 @@ struct dc_debug_options {
        bool hdmi20_disable;
        bool skip_detection_link_training;
        uint32_t edid_read_retry_times;
-       unsigned int force_odm_combine; //bit vector based on otg inst
-       unsigned int seamless_boot_odm_combine;
-       unsigned int force_odm_combine_4to1; //bit vector based on otg inst
+
+       uint8_t force_odm_combine; //bit vector based on otg inst
+       uint8_t seamless_boot_odm_combine;
+       uint8_t force_odm_combine_4to1; //bit vector based on otg inst
+
        int minimum_z8_residency_time;
        int minimum_z10_residency_time;
        bool disable_z9_mpc;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 86394203cee797a2b86b59276e7828bbe3750405..7c38fa6f8cb1964b33bbf8d5d6c80b0fd4661e65 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -162,13 +162,13 @@ struct test_pattern {
 #define SUBVP_DRR_MARGIN_US 100 // 100us for DRR margin (SubVP + DRR)
 
 struct dc_stream_debug_options {
-       char force_odm_combine_segments;
+       uint8_t force_odm_combine_segments;
        /*
         * When force_odm_combine_segments is non zero, allow dc to
         * temporarily transition to ODM bypass when minimal transition state
         * is required to prevent visual glitches showing on the screen
         */
-       char allow_transition_for_forced_odm;
+       uint8_t allow_transition_for_forced_odm;
 };
 
 #define LUMINANCE_DATA_TABLE_SIZE 10

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 7672ee88be82c5cdae167297461c8b9a1cc7c518..c08d5c005df6e3ad4a28b99e74eb3779e9efafe8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -205,7 +205,7 @@ struct dc_edid_caps {
        uint32_t audio_latency;
        uint32_t video_latency;
 
-       unsigned int freesync_vcp_code;
+       unsigned char freesync_vcp_code;
 
        uint8_t qs_bit;
        uint8_t qy_bit;