--- /dev/null
+CONFIG_64BIT=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=10
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PKEY_BITS=3
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_ARCH_SELECTS_KEXEC_FILE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_EXECMEM_LATE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARC_EMAC_CORE=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_ERRATUM_1024718=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_1319367=y
+CONFIG_ARM64_ERRATUM_1463225=y
+CONFIG_ARM64_ERRATUM_1530923=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2441007=y
+CONFIG_ARM64_ERRATUM_2441009=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_3117295=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_858921=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PLATFORM_DEVICES=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_RAS_EXTN=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=48
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_MHU=y
+CONFIG_ARM_MHU_V2=y
+# CONFIG_ARM_MHU_V3 is not set
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
+CONFIG_ARM_SCMI_CPUFREQ=y
+# CONFIG_ARM_SCMI_DEBUG_COUNTERS is not set
+CONFIG_ARM_SCMI_HAVE_SHMEM=y
+CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
+CONFIG_ARM_SCMI_PERF_DOMAIN=y
+CONFIG_ARM_SCMI_POWER_CONTROL=y
+CONFIG_ARM_SCMI_POWER_DOMAIN=y
+CONFIG_ARM_SCMI_PROTOCOL=y
+# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set
+CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC=y
+CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE=y
+CONFIG_ARM_SCPI_CPUFREQ=y
+CONFIG_ARM_SCPI_POWER_DOMAIN=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CHARGER_GPIO=y
+# CONFIG_CHARGER_RK817 is not set
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_PX30=y
+CONFIG_CLK_RK3308=y
+CONFIG_CLK_RK3328=y
+CONFIG_CLK_RK3368=y
+CONFIG_CLK_RK3399=y
+CONFIG_CLK_RK3528=y
+CONFIG_CLK_RK3568=y
+CONFIG_CLK_RK3576=y
+CONFIG_CLK_RK3588=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_ROCKCHIP=y
+CONFIG_COMMON_CLK_SCMI=y
+CONFIG_COMMON_CLK_SCPI=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRASH_RESERVE=y
+CONFIG_CRC16=y
+CONFIG_CRC64=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_POLYVAL=y
+CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SM3=y
+CONFIG_CRYPTO_SM3_NEON=y
+CONFIG_CRYPTO_SM4=y
+CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
+CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DEVMEM=y
+# CONFIG_DEVPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_NEED_SYNC=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS_HELPERS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_GENPD=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DWMAC_DWC_QOS_ETH=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_ROCKCHIP=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EMAC_ROCKCHIP=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=4
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_DEVICES=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_ROCKCHIP=y
+CONFIG_GPIO_SYSCON=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+# CONFIG_HOTPLUG_PCI_PCIE is not set
+# CONFIG_HOTPLUG_PCI_SHPC is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HUGETLB_PMD_PAGE_TABLE_SHARING=y
+CONFIG_HWMON=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_ROCKCHIP=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_RK3X=y
+CONFIG_IIO=y
+# CONFIG_IIO_SCMI is not set
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_INDIRECT_PIO=y
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_RK805_PWRKEY=y
+# CONFIG_IOMMUFD is not set
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_IO_PGTABLE=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_DART is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IO_STRICT_DEVMEM is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_MSI_LIB=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEXEC_FILE=y
+CONFIG_KSM=y
+# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_PANIC=y
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_LRU_GEN_WALKS_MMU=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_SERIAL=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_GPIO=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIATEK_GE_PHY=y
+# CONFIG_MEDIATEK_GE_SOC_PHY is not set
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_KHADAS_MCU is not set
+CONFIG_MFD_RK8XX=y
+CONFIG_MFD_RK8XX_I2C=y
+CONFIG_MFD_RK8XX_SPI=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_DW=y
+# CONFIG_MMC_DW_BLUEFIELD is not set
+# CONFIG_MMC_DW_EXYNOS is not set
+# CONFIG_MMC_DW_HI3798CV200 is not set
+# CONFIG_MMC_DW_HI3798MV200 is not set
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_DWCMSHC=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_MQ_IOSCHED_DEADLINE=y
+# CONFIG_MTD_CFI is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTK_NET_PHYLIB=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SG_DMA_FLAGS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DEVMEM=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_MT7530_MDIO=y
+CONFIG_NET_DSA_MT7530_MMIO=y
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=256
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_ROCKCHIP_EFUSE=y
+CONFIG_NVMEM_ROCKCHIP_OTP=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVME_CORE=y
+# CONFIG_NVME_HWMON is not set
+# CONFIG_NVME_MULTIPATH is not set
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_OVERLAY=y
+CONFIG_OF_RESOLVE=y
+# CONFIG_OVERLAY_FS_XINO_AUTO is not set
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_PME=y
+CONFIG_PCIE_ROCKCHIP=y
+CONFIG_PCIE_ROCKCHIP_DW=y
+CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+CONFIG_PCIE_ROCKCHIP_HOST=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_STUB=y
+CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PCS_XPCS=y
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_HAS_HUGE_LEAVES=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_ROCKCHIP_DP=y
+# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
+CONFIG_PHY_ROCKCHIP_EMMC=y
+# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
+# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+CONFIG_PHY_ROCKCHIP_PCIE=y
+# CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX is not set
+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RK805=y
+CONFIG_PINCTRL_ROCKCHIP=y
+# CONFIG_PINCTRL_SCMI is not set
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PL330_DMA=y
+CONFIG_PLATFORM_MHU=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_SUPPLY_HWMON=y
+CONFIG_PPS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_ROCKCHIP=y
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_RAID_ATTRS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+# CONFIG_RAVE_SP_CORE is not set
+CONFIG_RCU_TRACE=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REALTEK_PHY_HWMON=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ARM_SCMI=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK808=y
+CONFIG_RELOCATABLE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SCMI=y
+CONFIG_RFS_ACCEL=y
+CONFIG_ROCKCHIP_ERRATUM_3568002=y
+CONFIG_ROCKCHIP_ERRATUM_3588001=y
+CONFIG_ROCKCHIP_GRF=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_ROCKCHIP_MBOX=y
+CONFIG_ROCKCHIP_PHY=y
+CONFIG_ROCKCHIP_PM_DOMAINS=y
+# CONFIG_ROCKCHIP_SARADC is not set
+CONFIG_ROCKCHIP_THERMAL=y
+CONFIG_ROCKCHIP_TIMER=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RSEQ=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_HYM8563=y
+CONFIG_RTC_DRV_RK808=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SCSI_UFSHCD=y
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+CONFIG_SCSI_UFS_HWMON=y
+CONFIG_SCSI_UFS_ROCKCHIP=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SENSORS_ARM_SCMI=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=12
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=12
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_DYNAMIC=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_ROCKCHIP=y
+CONFIG_SPI_ROCKCHIP_SFC=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPLIT_PMD_PTLOCKS=y
+CONFIG_SPLIT_PTE_PTLOCKS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SRAM=y
+CONFIG_STACKPROTECTOR=y
+CONFIG_STACKPROTECTOR_PER_TASK=y
+CONFIG_STACKPROTECTOR_STRONG=y
+CONFIG_STACKTRACE=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_SWAP is not set
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFS_SYSCALL=y
+# CONFIG_TEXTSEARCH is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TOOLS_SUPPORT_RELR=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set
+CONFIG_TRANS_TABLE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TYPEC=y
+# CONFIG_TYPEC_ANX7411 is not set
+CONFIG_TYPEC_FUSB302=y
+# CONFIG_TYPEC_HD3SS3220 is not set
+# CONFIG_TYPEC_MUX_FSA4480 is not set
+# CONFIG_TYPEC_MUX_GPIO_SBU is not set
+# CONFIG_TYPEC_MUX_IT5205 is not set
+# CONFIG_TYPEC_MUX_NB7VPQ904M is not set
+# CONFIG_TYPEC_MUX_PI3USB30532 is not set
+# CONFIG_TYPEC_MUX_PTN36502 is not set
+# CONFIG_TYPEC_MUX_WCD939X_USBSS is not set
+# CONFIG_TYPEC_RT1719 is not set
+# CONFIG_TYPEC_STUSB160X is not set
+# CONFIG_TYPEC_TCPCI is not set
+CONFIG_TYPEC_TCPM=y
+# CONFIG_TYPEC_TPS6598X is not set
+# CONFIG_TYPEC_WUSB3801 is not set
+# CONFIG_UCLAMP_TASK is not set
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_HOST=y
+CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USER_STACKTRACE_SUPPORT=y
+CONFIG_VDSO_GETRANDOM=y
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_VMAP_STACK=y
+CONFIG_VMCORE_INFO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XARRAY_MULTI=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
--- /dev/null
+From 4294e32111781b3de4d73b944cbd1bc1662a9a7a Mon Sep 17 00:00:00 2001
+From: Sam Edwards <cfsworks@gmail.com>
+Date: Wed, 11 Sep 2024 19:50:30 -0700
+Subject: arm64: dts: rockchip: Split up RK3588's PCIe pinctrls
+
+These pinctrls manage the low-speed PCIe signals:
+- CLKREQ#: An output on the RK3588 (both RC or EP modes), used to
+ request that external clock-generation circuitry provide a clock.
+- PERST#: An input on the RK3588 in EP mode, used to detect a reset
+ signal from the RC. In RC mode, the hardware does not use this signal:
+ Linux itself generates it by putting the pin in GPIO mode.
+- WAKE#: In EP mode, this is an output; in RC mode, this is an input.
+
+Each of these signals serves a distinct purpose, and more importantly,
+PERST# should not be muxed when the RK3588 is in the RC role. Bundling
+them together in pinctrl groups prevents proper use: indeed, almost none
+of the current board-specific .dts files make any use of them.
+(Exception: Rock 5A recently had a patch land that misuses _pins; this
+ patch corrects that.)
+
+However, on some RK3588 boards, the PCIe 3 controller will indefinitely
+stall the boot if CLKREQ# is not muxed (details in the next patch).
+This patch unbundles the signals to allow them to be used.
+
+Signed-off-by: Sam Edwards <CFSworks@gmail.com>
+Link: https://lore.kernel.org/r/20240912025034.180233-2-CFSworks@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base-pinctrl.dtsi
+@@ -1612,23 +1612,43 @@
+
+ pcie20x1 {
+ /omit-if-no-ref/
+- pcie20x1m0_pins: pcie20x1m0-pins {
++ pcie20x1m0_clkreqn: pcie20x1m0-clkreqn {
+ rockchip,pins =
+ /* pcie20x1_2_clkreqn_m0 */
+- <3 RK_PC7 4 &pcfg_pull_none>,
++ <3 RK_PC7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie20x1m0_perstn: pcie20x1m0-perstn {
++ rockchip,pins =
+ /* pcie20x1_2_perstn_m0 */
+- <3 RK_PD1 4 &pcfg_pull_none>,
++ <3 RK_PD1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie20x1m0_waken: pcie20x1m0-waken {
++ rockchip,pins =
+ /* pcie20x1_2_waken_m0 */
+ <3 RK_PD0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- pcie20x1m1_pins: pcie20x1m1-pins {
++ pcie20x1m1_clkreqn: pcie20x1m1-clkreqn {
+ rockchip,pins =
+ /* pcie20x1_2_clkreqn_m1 */
+- <4 RK_PB7 4 &pcfg_pull_none>,
++ <4 RK_PB7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie20x1m1_perstn: pcie20x1m1-perstn {
++ rockchip,pins =
+ /* pcie20x1_2_perstn_m1 */
+- <4 RK_PC1 4 &pcfg_pull_none>,
++ <4 RK_PC1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie20x1m1_waken: pcie20x1m1-waken {
++ rockchip,pins =
+ /* pcie20x1_2_waken_m1 */
+ <4 RK_PC0 4 &pcfg_pull_none>;
+ };
+@@ -1654,52 +1674,127 @@
+
+ pcie30x1 {
+ /omit-if-no-ref/
+- pcie30x1m0_pins: pcie30x1m0-pins {
++ pcie30x1m0_0_clkreqn: pcie30x1m0-0-clkreqn {
+ rockchip,pins =
+ /* pcie30x1_0_clkreqn_m0 */
+- <0 RK_PC0 12 &pcfg_pull_none>,
++ <0 RK_PC0 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m0_0_perstn: pcie30x1m0-0-perstn {
++ rockchip,pins =
+ /* pcie30x1_0_perstn_m0 */
+- <0 RK_PC5 12 &pcfg_pull_none>,
++ <0 RK_PC5 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m0_0_waken: pcie30x1m0-0-waken {
++ rockchip,pins =
+ /* pcie30x1_0_waken_m0 */
+- <0 RK_PC4 12 &pcfg_pull_none>,
++ <0 RK_PC4 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m0_1_clkreqn: pcie30x1m0-1-clkreqn {
++ rockchip,pins =
+ /* pcie30x1_1_clkreqn_m0 */
+- <0 RK_PB5 12 &pcfg_pull_none>,
++ <0 RK_PB5 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m0_1_perstn: pcie30x1m0-1-perstn {
++ rockchip,pins =
+ /* pcie30x1_1_perstn_m0 */
+- <0 RK_PB7 12 &pcfg_pull_none>,
++ <0 RK_PB7 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m0_1_waken: pcie30x1m0-1-waken {
++ rockchip,pins =
+ /* pcie30x1_1_waken_m0 */
+ <0 RK_PB6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- pcie30x1m1_pins: pcie30x1m1-pins {
++ pcie30x1m1_0_clkreqn: pcie30x1m1-0-clkreqn {
+ rockchip,pins =
+ /* pcie30x1_0_clkreqn_m1 */
+- <4 RK_PA3 4 &pcfg_pull_none>,
++ <4 RK_PA3 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m1_0_perstn: pcie30x1m1-0-perstn {
++ rockchip,pins =
+ /* pcie30x1_0_perstn_m1 */
+- <4 RK_PA5 4 &pcfg_pull_none>,
++ <4 RK_PA5 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m1_0_waken: pcie30x1m1-0-waken {
++ rockchip,pins =
+ /* pcie30x1_0_waken_m1 */
+- <4 RK_PA4 4 &pcfg_pull_none>,
++ <4 RK_PA4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m1_1_clkreqn: pcie30x1m1-1-clkreqn {
++ rockchip,pins =
+ /* pcie30x1_1_clkreqn_m1 */
+- <4 RK_PA0 4 &pcfg_pull_none>,
++ <4 RK_PA0 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m1_1_perstn: pcie30x1m1-1-perstn {
++ rockchip,pins =
+ /* pcie30x1_1_perstn_m1 */
+- <4 RK_PA2 4 &pcfg_pull_none>,
++ <4 RK_PA2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m1_1_waken: pcie30x1m1-1-waken {
++ rockchip,pins =
+ /* pcie30x1_1_waken_m1 */
+ <4 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- pcie30x1m2_pins: pcie30x1m2-pins {
++ pcie30x1m2_0_clkreqn: pcie30x1m2-0-clkreqn {
+ rockchip,pins =
+ /* pcie30x1_0_clkreqn_m2 */
+- <1 RK_PB5 4 &pcfg_pull_none>,
++ <1 RK_PB5 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m2_0_perstn: pcie30x1m2-0-perstn {
++ rockchip,pins =
+ /* pcie30x1_0_perstn_m2 */
+- <1 RK_PB4 4 &pcfg_pull_none>,
++ <1 RK_PB4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m2_0_waken: pcie30x1m2-0-waken {
++ rockchip,pins =
+ /* pcie30x1_0_waken_m2 */
+- <1 RK_PB3 4 &pcfg_pull_none>,
++ <1 RK_PB3 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m2_1_clkreqn: pcie30x1m2-1-clkreqn {
++ rockchip,pins =
+ /* pcie30x1_1_clkreqn_m2 */
+- <1 RK_PA0 4 &pcfg_pull_none>,
++ <1 RK_PA0 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m2_1_perstn: pcie30x1m2-1-perstn {
++ rockchip,pins =
+ /* pcie30x1_1_perstn_m2 */
+- <1 RK_PA7 4 &pcfg_pull_none>,
++ <1 RK_PA7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x1m2_1_waken: pcie30x1m2-1-waken {
++ rockchip,pins =
+ /* pcie30x1_1_waken_m2 */
+ <1 RK_PA1 4 &pcfg_pull_none>;
+ };
+@@ -1721,45 +1816,85 @@
+
+ pcie30x2 {
+ /omit-if-no-ref/
+- pcie30x2m0_pins: pcie30x2m0-pins {
++ pcie30x2m0_clkreqn: pcie30x2m0-clkreqn {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m0 */
+- <0 RK_PD1 12 &pcfg_pull_none>,
++ <0 RK_PD1 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x2m0_perstn: pcie30x2m0-perstn {
++ rockchip,pins =
+ /* pcie30x2_perstn_m0 */
+- <0 RK_PD4 12 &pcfg_pull_none>,
++ <0 RK_PD4 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x2m0_waken: pcie30x2m0-waken {
++ rockchip,pins =
+ /* pcie30x2_waken_m0 */
+ <0 RK_PD2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- pcie30x2m1_pins: pcie30x2m1-pins {
++ pcie30x2m1_clkreqn: pcie30x2m1-clkreqn {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m1 */
+- <4 RK_PA6 4 &pcfg_pull_none>,
++ <4 RK_PA6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x2m1_perstn: pcie30x2m1-perstn {
++ rockchip,pins =
+ /* pcie30x2_perstn_m1 */
+- <4 RK_PB0 4 &pcfg_pull_none>,
++ <4 RK_PB0 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x2m1_waken: pcie30x2m1-waken {
++ rockchip,pins =
+ /* pcie30x2_waken_m1 */
+ <4 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- pcie30x2m2_pins: pcie30x2m2-pins {
++ pcie30x2m2_clkreqn: pcie30x2m2-clkreqn {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m2 */
+- <3 RK_PD2 4 &pcfg_pull_none>,
++ <3 RK_PD2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x2m2_perstn: pcie30x2m2-perstn {
++ rockchip,pins =
+ /* pcie30x2_perstn_m2 */
+- <3 RK_PD4 4 &pcfg_pull_none>,
++ <3 RK_PD4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x2m2_waken: pcie30x2m2-waken {
++ rockchip,pins =
+ /* pcie30x2_waken_m2 */
+ <3 RK_PD3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- pcie30x2m3_pins: pcie30x2m3-pins {
++ pcie30x2m3_clkreqn: pcie30x2m3-clkreqn {
+ rockchip,pins =
+ /* pcie30x2_clkreqn_m3 */
+- <1 RK_PD7 4 &pcfg_pull_none>,
++ <1 RK_PD7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x2m3_perstn: pcie30x2m3-perstn {
++ rockchip,pins =
+ /* pcie30x2_perstn_m3 */
+- <1 RK_PB7 4 &pcfg_pull_none>,
++ <1 RK_PB7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x2m3_waken: pcie30x2m3-waken {
++ rockchip,pins =
+ /* pcie30x2_waken_m3 */
+ <1 RK_PB6 4 &pcfg_pull_none>;
+ };
+@@ -1774,45 +1909,85 @@
+
+ pcie30x4 {
+ /omit-if-no-ref/
+- pcie30x4m0_pins: pcie30x4m0-pins {
++ pcie30x4m0_clkreqn: pcie30x4m0-clkreqn {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m0 */
+- <0 RK_PC6 12 &pcfg_pull_none>,
++ <0 RK_PC6 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x4m0_perstn: pcie30x4m0-perstn {
++ rockchip,pins =
+ /* pcie30x4_perstn_m0 */
+- <0 RK_PD0 12 &pcfg_pull_none>,
++ <0 RK_PD0 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x4m0_waken: pcie30x4m0-waken {
++ rockchip,pins =
+ /* pcie30x4_waken_m0 */
+ <0 RK_PC7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- pcie30x4m1_pins: pcie30x4m1-pins {
++ pcie30x4m1_clkreqn: pcie30x4m1-clkreqn {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m1 */
+- <4 RK_PB4 4 &pcfg_pull_none>,
++ <4 RK_PB4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x4m1_perstn: pcie30x4m1-perstn {
++ rockchip,pins =
+ /* pcie30x4_perstn_m1 */
+- <4 RK_PB6 4 &pcfg_pull_none>,
++ <4 RK_PB6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x4m1_waken: pcie30x4m1-waken {
++ rockchip,pins =
+ /* pcie30x4_waken_m1 */
+ <4 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- pcie30x4m2_pins: pcie30x4m2-pins {
++ pcie30x4m2_clkreqn: pcie30x4m2-clkreqn {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m2 */
+- <3 RK_PC4 4 &pcfg_pull_none>,
++ <3 RK_PC4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x4m2_perstn: pcie30x4m2-perstn {
++ rockchip,pins =
+ /* pcie30x4_perstn_m2 */
+- <3 RK_PC6 4 &pcfg_pull_none>,
++ <3 RK_PC6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x4m2_waken: pcie30x4m2-waken {
++ rockchip,pins =
+ /* pcie30x4_waken_m2 */
+ <3 RK_PC5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- pcie30x4m3_pins: pcie30x4m3-pins {
++ pcie30x4m3_clkreqn: pcie30x4m3-clkreqn {
+ rockchip,pins =
+ /* pcie30x4_clkreqn_m3 */
+- <1 RK_PB0 4 &pcfg_pull_none>,
++ <1 RK_PB0 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x4m3_perstn: pcie30x4m3-perstn {
++ rockchip,pins =
+ /* pcie30x4_perstn_m3 */
+- <1 RK_PB2 4 &pcfg_pull_none>,
++ <1 RK_PB2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pcie30x4m3_waken: pcie30x4m3-waken {
++ rockchip,pins =
+ /* pcie30x4_waken_m3 */
+ <1 RK_PB1 4 &pcfg_pull_none>;
+ };
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -311,7 +311,7 @@
+ };
+
+ &pcie2x1l2 {
+- pinctrl-0 = <&pcie20x1m0_pins>;
++ pinctrl-0 = <&pcie2_reset>, <&pcie20x1m0_clkreqn>, <&pcie20x1m0_waken>;
+ pinctrl-names = "default";
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_wf>;
+@@ -329,6 +329,10 @@
+ pow_en: pow-en {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
++
++ pcie2_reset: pcie2-reset {
++ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
+ };
+
+ power {
--- /dev/null
+From d7bb71e69f58c1b3665a9f926bf8d3855111bf8e Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Sat, 19 Oct 2024 13:12:10 +0300
+Subject: arm64: dts: rockchip: Add HDMI0 node to rk3588
+
+Add support for the HDMI0 output port found on RK3588 SoC.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1369,6 +1369,47 @@
+ status = "disabled";
+ };
+
++ hdmi0: hdmi@fde80000 {
++ compatible = "rockchip,rk3588-dw-hdmi-qp";
++ reg = <0x0 0xfde80000 0x0 0x20000>;
++ clocks = <&cru PCLK_HDMITX0>,
++ <&cru CLK_HDMITX0_EARC>,
++ <&cru CLK_HDMITX0_REF>,
++ <&cru MCLK_I2S5_8CH_TX>,
++ <&cru CLK_HDMIHDP0>,
++ <&cru HCLK_VO1>;
++ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
++ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
++ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
++ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
++ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
++ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
++ interrupt-names = "avp", "cec", "earc", "main", "hpd";
++ phys = <&hdptxphy_hdmi0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
++ &hdmim0_tx0_scl &hdmim0_tx0_sda>;
++ power-domains = <&power RK3588_PD_VO1>;
++ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
++ reset-names = "ref", "hdp";
++ rockchip,grf = <&sys_grf>;
++ rockchip,vo-grf = <&vo1_grf>;
++ status = "disabled";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ hdmi0_in: port@0 {
++ reg = <0>;
++ };
++
++ hdmi0_out: port@1 {
++ reg = <1>;
++ };
++ };
++ };
++
+ qos_gpu_m0: qos@fdf35000 {
+ compatible = "rockchip,rk3588-qos", "syscon";
+ reg = <0x0 0xfdf35000 0x0 0x20>;
--- /dev/null
+From 33b561eb66f1e271f2899e103c857d20425076f4 Mon Sep 17 00:00:00 2001
+From: Dragan Simic <dsimic@manjaro.org>
+Date: Wed, 8 Jan 2025 05:26:45 +0100
+Subject: arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi
+
+The preferred way to denote hardware with non-coherent DMA is to use the
+"dma-noncoherent" DT property, at both the GIC redistributor and the GIC ITS
+levels, [1] instead of relying on the compatibles to handle hardware errata,
+in this case the Rockchip 3588001 errata. [2]
+
+Let's have the preferred way employed in the base Rockchip RK3588 SoC dtsi,
+which also goes along with adding initial support for the Rockchip RK3582 SoC
+variant, with its separate compatible. [2][3]
+
+[1] Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
+[2] https://lore.kernel.org/linux-rockchip/86msgoozqa.wl-maz@kernel.org/
+[3] https://lore.kernel.org/linux-rockchip/20241222030355.2246-4-naoki@radxa.com/
+
+Cc: Marc Zyngier <maz@kernel.org>
+Cc: FUKAUMI Naoki <naoki@radxa.com>
+Acked-by: Marc Zyngier <maz@kernel.org>
+Signed-off-by: Dragan Simic <dsimic@manjaro.org>
+Link: https://lore.kernel.org/r/fa1a672dae3644bb3caa58f03216d0ca349db88b.1736279094.git.dsimic@manjaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -2020,6 +2020,7 @@
+ <0x0 0xfe680000 0 0x100000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-controller;
++ dma-noncoherent;
+ mbi-alias = <0x0 0xfe610000>;
+ mbi-ranges = <424 56>;
+ msi-controller;
+@@ -2031,6 +2032,7 @@
+ its0: msi-controller@fe640000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0xfe640000 0x0 0x20000>;
++ dma-noncoherent;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+@@ -2038,6 +2040,7 @@
+ its1: msi-controller@fe660000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0xfe660000 0x0 0x20000>;
++ dma-noncoherent;
+ msi-controller;
+ #msi-cells = <1>;
+ };
--- /dev/null
+From d0f17738778c12be629ba77ff00c43c3e9eb8428 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Tue, 4 Feb 2025 14:40:07 +0200
+Subject: arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588
+
+Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
+provider support"), the HDMI PHY PLL can be used as an alternative and
+more accurate pixel clock source for VOP2 to improve display modes
+handling on RK3588 SoC.
+
+Add the missing #clock-cells property to allow using the clock provider
+functionality of HDMI0 PHY.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Tested-by: FUKAUMI Naoki <naoki@radxa.com>
+Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-4-d71c6a196e58@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -2813,6 +2813,7 @@
+ reg = <0x0 0xfed60000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
+ clock-names = "ref", "apb";
++ #clock-cells = <0>;
+ #phy-cells = <0>;
+ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
+ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
--- /dev/null
+From eb4262203d7d85eb7b6f2696816db272e41f5464 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Tue, 4 Feb 2025 14:40:08 +0200
+Subject: arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on
+ RK3588
+
+VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
+more accurate pixel clock source to improve handling of display modes up
+to 4K@60Hz on video ports 0, 1 and 2.
+
+For now only HDMI0 output is supported, hence add the related PLL clock.
+
+Tested-by: FUKAUMI Naoki <naoki@radxa.com>
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1261,14 +1261,16 @@
+ <&cru DCLK_VOP1>,
+ <&cru DCLK_VOP2>,
+ <&cru DCLK_VOP3>,
+- <&cru PCLK_VOP_ROOT>;
++ <&cru PCLK_VOP_ROOT>,
++ <&hdptxphy_hdmi0>;
+ clock-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+ "dclk_vp1",
+ "dclk_vp2",
+ "dclk_vp3",
+- "pclk_vop";
++ "pclk_vop",
++ "pll_hdmiphy0";
+ iommus = <&vop_mmu>;
+ power-domains = <&power RK3588_PD_VOP>;
+ rockchip,grf = <&sys_grf>;
--- /dev/null
+From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001
+From: Damon Ding <damon.ding@rock-chips.com>
+Date: Thu, 6 Feb 2025 11:03:30 +0800
+Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
+
+The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
+and eDP Link. Therefore, it is better to name it hdptxphy0 other than
+hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
+
+Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
+Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
+[added armsom-sige7, where hdmi-support was added recently and also
+ the hdptxphy0-as-dclk source I just added]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1262,7 +1262,7 @@
+ <&cru DCLK_VOP2>,
+ <&cru DCLK_VOP3>,
+ <&cru PCLK_VOP_ROOT>,
+- <&hdptxphy_hdmi0>;
++ <&hdptxphy0>;
+ clock-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+@@ -1387,7 +1387,7 @@
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "avp", "cec", "earc", "main", "hpd";
+- phys = <&hdptxphy_hdmi0>;
++ phys = <&hdptxphy0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
+ &hdmim0_tx0_scl &hdmim0_tx0_sda>;
+@@ -2810,7 +2810,7 @@
+ #dma-cells = <1>;
+ };
+
+- hdptxphy_hdmi0: phy@fed60000 {
++ hdptxphy0: phy@fed60000 {
+ compatible = "rockchip,rk3588-hdptx-phy";
+ reg = <0x0 0xfed60000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
--- /dev/null
+From ea97212a0f66b7bd71c23c12f781f1770dd6fcff Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Wed, 11 Dec 2024 01:06:15 +0200
+Subject: arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588
+
+In preparation to enable the second HDMI output port found on RK3588
+SoC, add the related PHY node. This requires a GRF, hence add the
+dependent node as well.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
+Tested-by: Alexandre ARNOUD <aarnoud@me.com>
+Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-2-02cdca22ff68@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+@@ -67,6 +67,11 @@
+ };
+ };
+
++ hdptxphy1_grf: syscon@fd5e4000 {
++ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
++ reg = <0x0 0xfd5e4000 0x0 0x100>;
++ };
++
+ i2s8_8ch: i2s@fddc8000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfddc8000 0x0 0x1000>;
+@@ -395,6 +400,22 @@
+ };
+ };
+
++ hdptxphy1: phy@fed70000 {
++ compatible = "rockchip,rk3588-hdptx-phy";
++ reg = <0x0 0xfed70000 0x0 0x2000>;
++ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
++ clock-names = "ref", "apb";
++ #phy-cells = <0>;
++ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
++ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
++ <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>,
++ <&cru SRST_HDPTX1_LCPLL>;
++ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
++ "lcpll";
++ rockchip,grf = <&hdptxphy1_grf>;
++ status = "disabled";
++ };
++
+ usbdp_phy1: phy@fed90000 {
+ compatible = "rockchip,rk3588-usbdp-phy";
+ reg = <0x0 0xfed90000 0x0 0x10000>;
--- /dev/null
+From bed6964e779b5853de042da14320edf9f79506fe Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Wed, 11 Dec 2024 01:06:16 +0200
+Subject: arm64: dts: rockchip: Add HDMI1 node on RK3588
+
+Add support for the second HDMI TX port found on RK3588 SoC.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-6tops-modules
+Tested-by: Alexandre ARNOUD <aarnoud@me.com>
+Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-3-02cdca22ff68@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+@@ -140,6 +140,47 @@
+ status = "disabled";
+ };
+
++ hdmi1: hdmi@fdea0000 {
++ compatible = "rockchip,rk3588-dw-hdmi-qp";
++ reg = <0x0 0xfdea0000 0x0 0x20000>;
++ clocks = <&cru PCLK_HDMITX1>,
++ <&cru CLK_HDMITX1_EARC>,
++ <&cru CLK_HDMITX1_REF>,
++ <&cru MCLK_I2S6_8CH_TX>,
++ <&cru CLK_HDMIHDP1>,
++ <&cru HCLK_VO1>;
++ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
++ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>,
++ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>,
++ <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>,
++ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>,
++ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>;
++ interrupt-names = "avp", "cec", "earc", "main", "hpd";
++ phys = <&hdptxphy1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd
++ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
++ power-domains = <&power RK3588_PD_VO1>;
++ resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>;
++ reset-names = "ref", "hdp";
++ rockchip,grf = <&sys_grf>;
++ rockchip,vo-grf = <&vo1_grf>;
++ status = "disabled";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ hdmi1_in: port@0 {
++ reg = <0>;
++ };
++
++ hdmi1_out: port@1 {
++ reg = <1>;
++ };
++ };
++ };
++
+ pcie3x4: pcie@fe150000 {
+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ #address-cells = <3>;
--- /dev/null
+From aadaa27956e3430217d9e6b8af5880e39b05b961 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Sun, 23 Feb 2025 11:31:39 +0200
+Subject: arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588
+
+Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock
+provider support"), the HDMI PHY PLL can be used as an alternative and
+more accurate pixel clock source for VOP2 to improve display modes
+handling on RK3588 SoC.
+
+Add the missing #clock-cells property to allow using the clock provider
+functionality of HDMI1 PHY.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-3-f4cec5e06fbe@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+@@ -446,6 +446,7 @@
+ reg = <0x0 0xfed70000 0x0 0x2000>;
+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>;
+ clock-names = "ref", "apb";
++ #clock-cells = <0>;
+ #phy-cells = <0>;
+ resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>,
+ <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>,
--- /dev/null
+From b2e668a60ed866ba960acb5310d1fb6bf81d154f Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Sun, 23 Feb 2025 11:31:40 +0200
+Subject: arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on
+ RK3588
+
+VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
+more accurate pixel clock source to improve handling of display modes up
+to 4K@60Hz on video ports 0, 1 and 2.
+
+The HDMI1 PHY PLL clock source cannot be added directly to vop node in
+rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an
+optional feature and its PHY node belongs to a separate (extra) DT file.
+
+Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its
+clocks & clock-names properties in the extra DT file.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20250223-vop2-hdmi1-disp-modes-v2-4-f4cec5e06fbe@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+@@ -509,3 +509,24 @@
+ status = "disabled";
+ };
+ };
++
++&vop {
++ clocks = <&cru ACLK_VOP>,
++ <&cru HCLK_VOP>,
++ <&cru DCLK_VOP0>,
++ <&cru DCLK_VOP1>,
++ <&cru DCLK_VOP2>,
++ <&cru DCLK_VOP3>,
++ <&cru PCLK_VOP_ROOT>,
++ <&hdptxphy0>,
++ <&hdptxphy1>;
++ clock-names = "aclk",
++ "hclk",
++ "dclk_vp0",
++ "dclk_vp1",
++ "dclk_vp2",
++ "dclk_vp3",
++ "pclk_vop",
++ "pll_hdmiphy0",
++ "pll_hdmiphy1";
++};
--- /dev/null
+From 6ee0b9ad3995ee5fa229035c69013b7dd0d3634b Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 4 Feb 2025 16:35:51 +0100
+Subject: [PATCH] arm64: dts: rockchip: Add rng node to RK3588
+
+Add the RK3588's standalone hardware random number generator node to its
+device tree, and enable it.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250204-rk3588-trng-submission-v2-6-608172b6fd91@collabora.com
+[changed reset-id to its numeric value while the constant makes its
+ way through the crypto tree]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1921,6 +1921,14 @@
+ status = "disabled";
+ };
+
++ rng@fe378000 {
++ compatible = "rockchip,rk3588-rng";
++ reg = <0x0 0xfe378000 0x0 0x200>;
++ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
++ resets = <&scmi_reset 48>;
++ };
++
+ i2s0_8ch: i2s@fe470000 {
+ compatible = "rockchip,rk3588-i2s-tdm";
+ reg = <0x0 0xfe470000 0x0 0x1000>;
--- /dev/null
+From b8c6c136971c0e9750eec89f367529b2854d3a3c Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Mon, 17 Feb 2025 16:47:41 -0500
+Subject: arm64: dts: rockchip: Add HDMI audio outputs for rk3588
+
+For hdmi0_sound, use the simple-audio-card driver with the hdmi0 QP node
+as CODEC and the i2s5 device as CPU.
+
+Similarly for hdmi1_sound, the CODEC is the hdmi1 node and the CPU is
+i2s6, but only added in the rk3588-extra.dtsi device tree as the second
+TX HDMI port is not available on base versions of the SoC.
+
+The simple-audio-card,mclk-fs value is set to 128 as it is done in
+the downstream driver.
+
+The #sound-dai-cells value is set to 0 in the hdmi0 and hdmi1 nodes so
+that they can be used as audio codec nodes.
+
+Tested-by: Quentin Schulz <quentin.schulz@cherry.de> # RK3588 Tiger Haikou
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node")
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Link: https://lore.kernel.org/r/20250217215641.372723-3-detlev.casanova@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -382,6 +382,22 @@
+ };
+ };
+
++ hdmi0_sound: hdmi0-sound {
++ compatible = "simple-audio-card";
++ simple-audio-card,format = "i2s";
++ simple-audio-card,mclk-fs = <128>;
++ simple-audio-card,name = "hdmi0";
++ status = "disabled";
++
++ simple-audio-card,codec {
++ sound-dai = <&hdmi0>;
++ };
++
++ simple-audio-card,cpu {
++ sound-dai = <&i2s5_8ch>;
++ };
++ };
++
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
+@@ -1396,6 +1412,7 @@
+ reset-names = "ref", "hdp";
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo-grf = <&vo1_grf>;
++ #sound-dai-cells = <0>;
+ status = "disabled";
+
+ ports {
+--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+@@ -7,6 +7,22 @@
+ #include "rk3588-extra-pinctrl.dtsi"
+
+ / {
++ hdmi1_sound: hdmi1-sound {
++ compatible = "simple-audio-card";
++ simple-audio-card,format = "i2s";
++ simple-audio-card,mclk-fs = <128>;
++ simple-audio-card,name = "hdmi1";
++ status = "disabled";
++
++ simple-audio-card,codec {
++ sound-dai = <&hdmi1>;
++ };
++
++ simple-audio-card,cpu {
++ sound-dai = <&i2s6_8ch>;
++ };
++ };
++
+ usb_host1_xhci: usb@fc400000 {
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ reg = <0x0 0xfc400000 0x0 0x400000>;
+@@ -165,6 +181,7 @@
+ reset-names = "ref", "hdp";
+ rockchip,grf = <&sys_grf>;
+ rockchip,vo-grf = <&vo1_grf>;
++ #sound-dai-cells = <0>;
+ status = "disabled";
+
+ ports {
--- /dev/null
+From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 20 Feb 2025 19:58:11 +0100
+Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
+ RK3588
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Enabling the GPU power domain requires that the GPU regulator is
+enabled. The regulator is enabled at boot time, but gets disabled
+automatically when there are no users.
+
+This means the system might run into a failure state hanging the
+whole system for the following use cases:
+
+ * if the GPU driver is being probed late (e.g. build as a
+ module and firmware is not in initramfs), the regulator
+ might already have been disabled. In that case the power
+ domain is enabled before the regulator.
+ * unbinding the GPU driver will disable the PM domain and
+ the regulator. When the driver is bound again, the PM
+ domain will be enabled before the regulator and error
+ appears.
+
+Avoid this by adding an explicit regulator dependency to the
+power domain.
+
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Reported-by: Adrián MartÃnez Larumbe <adrian.larumbe@collabora.com>
+Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -880,7 +880,7 @@
+ };
+ };
+ /* These power domains are grouped by VD_GPU */
+- power-domain@RK3588_PD_GPU {
++ pd_gpu: power-domain@RK3588_PD_GPU {
+ reg = <RK3588_PD_GPU>;
+ clocks = <&cru CLK_GPU>,
+ <&cru CLK_GPU_COREGROUP>,
--- /dev/null
+From 55a43c346d24434e46ef7fcc09a9df8179c346e4 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Sun, 16 Feb 2025 16:27:42 +0100
+Subject: [PATCH] arm64: dts: rockchip: change rng reset id back to its
+ constant value
+
+With the binding header now providing the SCMI_SRST_H_TRNG_NS constant,
+switch back to it from the temporary numeric value.
+
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1943,7 +1943,7 @@
+ reg = <0x0 0xfe378000 0x0 0x200>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
+- resets = <&scmi_reset 48>;
++ resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>;
+ };
+
+ i2s0_8ch: i2s@fe470000 {
--- /dev/null
+From 0327238991ba2d1de25e1116b1c064f433e45b8d Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Fri, 7 Mar 2025 12:18:56 +0300
+Subject: arm64: dts: rockchip: Add device tree support for HDMI RX Controller
+
+Add device tree support for Synopsys DesignWare HDMI RX
+Controller.
+
+Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Tested-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Co-developed-by: Dingxian Wen <shawn.wen@rock-chips.com>
+Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Link: https://lore.kernel.org/r/20250307091857.646581-2-dmitry.osipenko@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi
+@@ -23,6 +23,30 @@
+ };
+ };
+
++ reserved-memory {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ /*
++ * The 4k HDMI capture controller works only with 32bit
++ * phys addresses and doesn't support IOMMU. HDMI RX CMA
++ * must be reserved below 4GB.
++ * The size of 160MB was determined as follows:
++ * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB
++ * To ensure sufficient support for practical use-cases,
++ * we doubled the 66MB value.
++ */
++ hdmi_receiver_cma: hdmi-receiver-cma {
++ compatible = "shared-dma-pool";
++ alloc-ranges = <0x0 0x0 0x0 0xffffffff>;
++ size = <0x0 (160 * 0x100000)>; /* 160MiB */
++ alignment = <0x0 0x40000>; /* 64K */
++ no-map;
++ status = "disabled";
++ };
++ };
++
+ usb_host1_xhci: usb@fc400000 {
+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+ reg = <0x0 0xfc400000 0x0 0x400000>;
+@@ -198,6 +222,37 @@
+ };
+ };
+
++ hdmi_receiver: hdmi_receiver@fdee0000 {
++ compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx";
++ reg = <0x0 0xfdee0000 0x0 0x6000>;
++ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>,
++ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>,
++ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>;
++ interrupt-names = "cec", "hdmi", "dma";
++ clocks = <&cru ACLK_HDMIRX>,
++ <&cru CLK_HDMIRX_AUD>,
++ <&cru CLK_CR_PARA>,
++ <&cru PCLK_HDMIRX>,
++ <&cru CLK_HDMIRX_REF>,
++ <&cru PCLK_S_HDMIRX>,
++ <&cru HCLK_VO1>;
++ clock-names = "aclk",
++ "audio",
++ "cr_para",
++ "pclk",
++ "ref",
++ "hclk_s_hdmirx",
++ "hclk_vo1";
++ memory-region = <&hdmi_receiver_cma>;
++ power-domains = <&power RK3588_PD_VO1>;
++ resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>,
++ <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>;
++ reset-names = "axi", "apb", "ref", "biu";
++ rockchip,grf = <&sys_grf>;
++ rockchip,vo1-grf = <&vo1_grf>;
++ status = "disabled";
++ };
++
+ pcie3x4: pcie@fe150000 {
+ compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ #address-cells = <3>;
--- /dev/null
+From 9d856aa1c81930a5d8df0e29d6cb0faa3fa87206 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Fri, 31 Oct 2025 16:58:24 +0100
+Subject: [PATCH] arm64: dts: rockchip: add eMMC CQE support for rk3588
+
+The RK3588 eMMC controller supports CQE, so add the missing
+DT flag.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://patch.msgid.link/20251031-rockchip-emmc-cqe-support-v2-2-958171f5edad@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+@@ -1935,6 +1935,7 @@
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
++ supports-cqe;
+ status = "disabled";
+ };
+
--- /dev/null
+From a98053d098c4ad91a45a3a55604d9574dfc6ffdb Mon Sep 17 00:00:00 2001
+From: FUKAUMI Naoki <naoki@radxa.com>
+Date: Sat, 19 Oct 2024 02:50:08 +0000
+Subject: arm64: dts: rockchip: add and enable gpu node for Radxa ROCK 5A
+
+add gpu node to make it usable on Radxa ROCK 5A.
+
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+Link: https://lore.kernel.org/r/20241019025008.852-1-naoki@radxa.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -166,6 +166,11 @@
+ cpu-supply = <&vdd_cpu_lit_s0>;
+ };
+
++&gpu {
++ mali-supply = <&vdd_gpu_s0>;
++ status = "okay";
++};
++
+ &i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
--- /dev/null
+From f57a8daf6bbd8e71f16693ad6d8421cb881c7fe0 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Tue, 22 Oct 2024 19:04:42 +0300
+Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5a
+
+Add the necessary DT changes to enable HDMI0 on Radxa ROCK 5A.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20241022-rk3588-hdmi0-dt-v3-1-3cc981e89afb@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -5,6 +5,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3588s.dtsi"
+
+ / {
+@@ -35,6 +36,17 @@
+ stdout-path = "serial2:1500000n8";
+ };
+
++ hdmi0-con {
++ compatible = "hdmi-connector";
++ type = "d";
++
++ port {
++ hdmi0_con_in: endpoint {
++ remote-endpoint = <&hdmi0_out_con>;
++ };
++ };
++ };
++
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+@@ -302,6 +314,31 @@
+ status = "okay";
+ };
+
++&hdmi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&hdmim0_tx0_cec
++ &hdmim1_tx0_hpd
++ &hdmim0_tx0_scl
++ &hdmim0_tx0_sda>;
++ status = "okay";
++};
++
++&hdmi0_in {
++ hdmi0_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi0>;
++ };
++};
++
++&hdmi0_out {
++ hdmi0_out_con: endpoint {
++ remote-endpoint = <&hdmi0_con_in>;
++ };
++};
++
++&hdptxphy_hdmi0 {
++ status = "okay";
++};
++
+ &mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ /* RTL8211F */
+@@ -794,3 +831,18 @@
+ &usb_host2_xhci {
+ status = "okay";
+ };
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vop {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi0_in_vp0>;
++ };
++};
--- /dev/null
+From 9f3360b42bb5b0c99073827a3dd81d2568b2a4ed Mon Sep 17 00:00:00 2001
+From: FUKAUMI Naoki <naoki@radxa.com>
+Date: Mon, 28 Oct 2024 07:23:44 +0000
+Subject: arm64: dts: rockchip: sort rk3588s-rock5a properly in Makefile
+
+sort target dtb files properly in Makefile for rockchip.
+
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+Link: https://lore.kernel.org/r/20241028072344.1514-1-naoki@radxa.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -151,6 +151,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-i
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb
+-dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
--- /dev/null
+From 5c96e63301978f4657c9082c55a066763c8db7b1 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Sat, 5 Oct 2024 22:40:12 +0200
+Subject: arm64: dts: rockchip: adapt regulator nodenames to preferred form
+
+The preferred nodename for fixed-regulators has changed to
+pattern: '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$'
+
+Fix all Rockchip DT regulator nodenames.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Link: https://lore.kernel.org/r/0ae40493-93e9-40cd-9ca9-990ae064f21a@gmail.com
+[adapted rebased on top of a number of other changes and included
+ neu6a-wifi + wolfvision-pf5-io-expander overlays]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -68,7 +68,7 @@
+ #cooling-cells = <2>;
+ };
+
+- vcc12v_dcin: vcc12v-dcin-regulator {
++ vcc12v_dcin: regulator-vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+@@ -77,7 +77,7 @@
+ regulator-max-microvolt = <12000000>;
+ };
+
+- vcc3v3_wf: vcc3v3-wf-regulator {
++ vcc3v3_wf: regulator-vcc3v3-wf {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_wf";
+ regulator-min-microvolt = <3300000>;
+@@ -89,7 +89,7 @@
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+- vcc5v0_host: vcc5v0-host-regulator {
++ vcc5v0_host: regulator-vcc5v0-host {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+@@ -103,7 +103,7 @@
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+- vcc5v0_sys: vcc5v0-sys-regulator {
++ vcc5v0_sys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+@@ -113,7 +113,7 @@
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+- vcc_5v0: vcc-5v0-regulator {
++ vcc_5v0: regulator-vcc-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v0";
+ regulator-min-microvolt = <5000000>;
+@@ -127,7 +127,7 @@
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
--- /dev/null
+From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001
+From: Damon Ding <damon.ding@rock-chips.com>
+Date: Thu, 6 Feb 2025 11:03:30 +0800
+Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
+
+The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
+and eDP Link. Therefore, it is better to name it hdptxphy0 other than
+hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
+
+Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
+Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
+[added armsom-sige7, where hdmi-support was added recently and also
+ the hdptxphy0-as-dclk source I just added]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -335,7 +335,7 @@
+ };
+ };
+
+-&hdptxphy_hdmi0 {
++&hdptxphy0 {
+ status = "okay";
+ };
+
--- /dev/null
+From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 20 Feb 2025 19:58:11 +0100
+Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
+ RK3588
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Enabling the GPU power domain requires that the GPU regulator is
+enabled. The regulator is enabled at boot time, but gets disabled
+automatically when there are no users.
+
+This means the system might run into a failure state hanging the
+whole system for the following use cases:
+
+ * if the GPU driver is being probed late (e.g. build as a
+ module and firmware is not in initramfs), the regulator
+ might already have been disabled. In that case the power
+ domain is enabled before the regulator.
+ * unbinding the GPU driver will disable the PM domain and
+ the regulator. When the driver is bound again, the PM
+ domain will be enabled before the regulator and error
+ appears.
+
+Avoid this by adding an explicit regulator dependency to the
+power domain.
+
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Reported-by: Adrián MartÃnez Larumbe <adrian.larumbe@collabora.com>
+Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -360,6 +360,10 @@
+ status = "okay";
+ };
+
++&pd_gpu {
++ domain-supply = <&vdd_gpu_s0>;
++};
++
+ &pinctrl {
+ leds {
+ io_led: io-led {
--- /dev/null
+From 3ca743f8a5b568dc5e5d5f1bab0298a4a43c2360 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 27 Sep 2024 14:42:22 +0200
+Subject: arm64: dts: rockchip: Switch to hp-det-gpios
+
+Replace the deprecated "hp-det-gpio" property by "hp-det-gpios" in Audio
+Graph Card and Realtek RT5651 Audio Codec device nodes.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
+Link: https://lore.kernel.org/r/717e7c9527139c3a3e5246dd367a3ad98c5c81b6.1727438777.git.geert+renesas@glider.be
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -32,7 +32,7 @@
+ "Headphones", "HPOR";
+
+ dais = <&i2s0_8ch_p0>;
+- hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
++ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ };
--- /dev/null
+From c8152f79c2dd8039e14073be76fdbce8760175da Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Sat, 19 Oct 2024 13:12:11 +0300
+Subject: arm64: dts: rockchip: Enable HDMI0 on rock-5b
+
+Add the necessary DT changes to enable HDMI0 on Radxa ROCK 5B.
+
+Tested-by: FUKAUMI Naoki <naoki@radxa.com>
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-2-466cd80e8ff9@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -4,6 +4,7 @@
+
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3588.dtsi"
+
+ / {
+@@ -37,6 +38,17 @@
+ pinctrl-0 = <&hp_detect>;
+ };
+
++ hdmi0-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi0_con_in: endpoint {
++ remote-endpoint = <&hdmi0_out_con>;
++ };
++ };
++ };
++
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+@@ -192,6 +204,26 @@
+ status = "okay";
+ };
+
++&hdmi0 {
++ status = "okay";
++};
++
++&hdmi0_in {
++ hdmi0_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi0>;
++ };
++};
++
++&hdmi0_out {
++ hdmi0_out_con: endpoint {
++ remote-endpoint = <&hdmi0_con_in>;
++ };
++};
++
++&hdptxphy_hdmi0 {
++ status = "okay";
++};
++
+ &i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+@@ -858,3 +890,18 @@
+ &usb_host2_xhci {
+ status = "okay";
+ };
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vop {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi0_in_vp0>;
++ };
++};
--- /dev/null
+From 5c96e63301978f4657c9082c55a066763c8db7b1 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Sat, 5 Oct 2024 22:40:12 +0200
+Subject: arm64: dts: rockchip: adapt regulator nodenames to preferred form
+
+The preferred nodename for fixed-regulators has changed to
+pattern: '^regulator(-[0-9]+v[0-9]+|-[0-9a-z-]+)?$'
+
+Fix all Rockchip DT regulator nodenames.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Link: https://lore.kernel.org/r/0ae40493-93e9-40cd-9ca9-990ae064f21a@gmail.com
+[adapted rebased on top of a number of other changes and included
+ neu6a-wifi + wolfvision-pf5-io-expander overlays]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -84,7 +84,7 @@
+ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+ };
+
+- vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
++ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+@@ -99,7 +99,7 @@
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+- vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator {
++ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie2x1l2";
+ regulator-min-microvolt = <3300000>;
+@@ -108,7 +108,7 @@
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+- vcc3v3_pcie30: vcc3v3-pcie30-regulator {
++ vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+@@ -121,7 +121,7 @@
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+- vcc5v0_host: vcc5v0-host-regulator {
++ vcc5v0_host: regulator-vcc5v0-host {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_host";
+ regulator-boot-on;
+@@ -135,7 +135,7 @@
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+- vcc5v0_sys: vcc5v0-sys-regulator {
++ vcc5v0_sys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+@@ -144,7 +144,7 @@
+ regulator-max-microvolt = <5000000>;
+ };
+
+- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
--- /dev/null
+From 2ddd93481bce86c6a46223f45accdb3b149a43e4 Mon Sep 17 00:00:00 2001
+From: FUKAUMI Naoki <naoki@radxa.com>
+Date: Thu, 28 Nov 2024 12:06:30 +0000
+Subject: arm64: dts: rockchip: rename rfkill label for Radxa ROCK 5B
+
+on ROCK 5B, there is no PCIe slot, instead there is a M.2 slot.
+rfkill pin is not exclusive to PCIe devices, there is SDIO Wi-Fi
+devices.
+
+rename rfkill label from "rfkill-pcie-wlan" to "rfkill-m2-wlan", it
+matches with rfkill-bt.
+
+Fixes: 82d40b141a4c ("arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b")
+Reviewed-by: Dragan Simic <dsimic@manjaro.org>
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+Fixes: 82d40b141a4c ("arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b")
+Link: https://lore.kernel.org/r/20241128120631.37458-1-naoki@radxa.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -72,7 +72,7 @@
+
+ rfkill {
+ compatible = "rfkill-gpio";
+- label = "rfkill-pcie-wlan";
++ label = "rfkill-m2-wlan";
+ radio-type = "wlan";
+ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
--- /dev/null
+From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001
+From: Damon Ding <damon.ding@rock-chips.com>
+Date: Thu, 6 Feb 2025 11:03:30 +0800
+Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
+
+The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
+and eDP Link. Therefore, it is better to name it hdptxphy0 other than
+hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
+
+Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
+Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
+[added armsom-sige7, where hdmi-support was added recently and also
+ the hdptxphy0-as-dclk source I just added]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -220,7 +220,7 @@
+ };
+ };
+
+-&hdptxphy_hdmi0 {
++&hdptxphy0 {
+ status = "okay";
+ };
+
--- /dev/null
+From 77cea7ca13680e14119a3b9635c7ef16cd7ee44e Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Wed, 11 Dec 2024 01:06:17 +0200
+Subject: arm64: dts: rockchip: Enable HDMI1 on rock-5b
+
+Add the necessary DT changes to enable the second HDMI output port on
+Radxa ROCK 5B.
+
+While at it, switch the position of &vop_mmu and @vop to maintain the
+alphabetical order.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Tested-by: Alexandre ARNOUD <aarnoud@me.com>
+Link: https://lore.kernel.org/r/20241211-rk3588-hdmi1-v2-4-02cdca22ff68@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -49,6 +49,17 @@
+ };
+ };
+
++ hdmi1-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi1_con_in: endpoint {
++ remote-endpoint = <&hdmi1_out_con>;
++ };
++ };
++ };
++
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+@@ -220,10 +231,32 @@
+ };
+ };
+
++&hdmi1 {
++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
++ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
++ status = "okay";
++};
++
++&hdmi1_in {
++ hdmi1_in_vp1: endpoint {
++ remote-endpoint = <&vp1_out_hdmi1>;
++ };
++};
++
++&hdmi1_out {
++ hdmi1_out_con: endpoint {
++ remote-endpoint = <&hdmi1_con_in>;
++ };
++};
++
+ &hdptxphy0 {
+ status = "okay";
+ };
+
++&hdptxphy1 {
++ status = "okay";
++};
++
+ &i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+@@ -891,11 +924,11 @@
+ status = "okay";
+ };
+
+-&vop_mmu {
++&vop {
+ status = "okay";
+ };
+
+-&vop {
++&vop_mmu {
+ status = "okay";
+ };
+
+@@ -905,3 +938,10 @@
+ remote-endpoint = <&hdmi0_in_vp0>;
+ };
+ };
++
++&vp1 {
++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI1>;
++ remote-endpoint = <&hdmi1_in_vp1>;
++ };
++};
--- /dev/null
+From 97aa62ed1e970bf8aa9f57e87c946a95fa3d5bef Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Mon, 17 Feb 2025 16:47:42 -0500
+Subject: arm64: dts: rockchip: Enable HDMI audio outputs for Rock 5B
+
+HDMI audio is available on the Rock 5B HDMI TX ports.
+Enable it for both ports.
+
+Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+Fixes: 419d1918105e ("ASoC: simple-card-utils: use __free(device_node) for device node")
+Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+Link: https://lore.kernel.org/r/20250217215641.372723-4-detlev.casanova@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -231,6 +231,10 @@
+ };
+ };
+
++&hdmi0_sound {
++ status = "okay";
++};
++
+ &hdmi1 {
+ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
+ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
+@@ -249,6 +253,10 @@
+ };
+ };
+
++&hdmi1_sound {
++ status = "okay";
++};
++
+ &hdptxphy0 {
+ status = "okay";
+ };
+@@ -351,6 +359,14 @@
+ };
+ };
+
++&i2s5_8ch {
++ status = "okay";
++};
++
++&i2s6_8ch {
++ status = "okay";
++};
++
+ &package_thermal {
+ polling-delay = <1000>;
+
--- /dev/null
+From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 20 Feb 2025 19:58:11 +0100
+Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
+ RK3588
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Enabling the GPU power domain requires that the GPU regulator is
+enabled. The regulator is enabled at boot time, but gets disabled
+automatically when there are no users.
+
+This means the system might run into a failure state hanging the
+whole system for the following use cases:
+
+ * if the GPU driver is being probed late (e.g. build as a
+ module and firmware is not in initramfs), the regulator
+ might already have been disabled. In that case the power
+ domain is enabled before the regulator.
+ * unbinding the GPU driver will disable the PM domain and
+ the regulator. When the driver is bound again, the PM
+ domain will be enabled before the regulator and error
+ appears.
+
+Avoid this by adding an explicit regulator dependency to the
+power domain.
+
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Reported-by: Adrián MartÃnez Larumbe <adrian.larumbe@collabora.com>
+Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -425,6 +425,10 @@
+ status = "okay";
+ };
+
++&pd_gpu {
++ domain-supply = <&vdd_gpu_s0>;
++};
++
+ &pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
--- /dev/null
+From c62d8fdb27391ee72bfdf53328463813997844f1 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Fri, 7 Mar 2025 12:18:57 +0300
+Subject: arm64: dts: rockchip: Enable HDMI receiver on rock-5b
+
+The Rock 5B has a Micro HDMI port, which can be used for receiving
+HDMI data. This enables support for it.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Link: https://lore.kernel.org/r/20250307091857.646581-3-dmitry.osipenko@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -257,6 +257,17 @@
+ status = "okay";
+ };
+
++&hdmi_receiver_cma {
++ status = "okay";
++};
++
++&hdmi_receiver {
++ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
++ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
++ pinctrl-names = "default";
++ status = "okay";
++};
++
+ &hdptxphy0 {
+ status = "okay";
+ };
+@@ -430,6 +441,12 @@
+ };
+
+ &pinctrl {
++ hdmirx {
++ hdmirx_hpd: hdmirx-5v-detection {
++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
--- /dev/null
+From 425af91c58023a8924cc2330384e040d388adc4e Mon Sep 17 00:00:00 2001
+From: Diederik de Haas <didi.debian@cknow.org>
+Date: Fri, 25 Apr 2025 10:44:44 +0200
+Subject: arm64: dts: rockchip: Add vcc-supply to SPI flash on rk3588-rock-5b
+
+The Radxa Rock 5B component placement document identifies the SPI Nor
+Flash chip as 'U4300' which is described on page 25 of the Schematic
+v1.45. There we can see that the VCC connector is connected to the
+VCC_3V3_S3 power source.
+
+This fixes the following warning:
+
+ spi-nor spi5.0: supply vcc not found, using dummy regulator
+
+Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
+Link: https://lore.kernel.org/r/20250425092601.56549-5-didi.debian@cknow.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -562,6 +562,7 @@
+ spi-max-frequency = <104000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
++ vcc-supply = <&vcc_3v3_s3>;
+ };
+ };
+
--- /dev/null
+From aadfbdcf7e1e7f3892e0e4bdcc3c9c7c9adfb723 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 8 May 2025 19:48:50 +0200
+Subject: arm64: dts: rockchip: move rock 5b to include file
+
+Radxa released some more boards, which are based on the original
+Rock 5B. Move its board description into an include file to avoid
+unnecessary duplication.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-1-677033cc1ac2@kernel.org
+Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-2-677033cc1ac2@kernel.org
+
+[The original submission was split into two elements, renaming the file
+ and then moving some nodes around. This was done to make review easier
+ due to the diff being smaller. This commit is a squash of both of them
+ to facilitate bisectability and was also intended by the original author]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -2,532 +2,11 @@
+
+ /dts-v1/;
+
+-#include <dt-bindings/gpio/gpio.h>
+-#include <dt-bindings/leds/common.h>
+-#include <dt-bindings/soc/rockchip,vop2.h>
+-#include "rk3588.dtsi"
++#include "rk3588-rock-5b.dtsi"
+
+ / {
+ model = "Radxa ROCK 5B";
+ compatible = "radxa,rock-5b", "rockchip,rk3588";
+-
+- aliases {
+- mmc0 = &sdhci;
+- mmc1 = &sdmmc;
+- mmc2 = &sdio;
+- };
+-
+- chosen {
+- stdout-path = "serial2:1500000n8";
+- };
+-
+- analog-sound {
+- compatible = "audio-graph-card";
+- label = "rk3588-es8316";
+-
+- widgets = "Microphone", "Mic Jack",
+- "Headphone", "Headphones";
+-
+- routing = "MIC2", "Mic Jack",
+- "Headphones", "HPOL",
+- "Headphones", "HPOR";
+-
+- dais = <&i2s0_8ch_p0>;
+- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&hp_detect>;
+- };
+-
+- hdmi0-con {
+- compatible = "hdmi-connector";
+- type = "a";
+-
+- port {
+- hdmi0_con_in: endpoint {
+- remote-endpoint = <&hdmi0_out_con>;
+- };
+- };
+- };
+-
+- hdmi1-con {
+- compatible = "hdmi-connector";
+- type = "a";
+-
+- port {
+- hdmi1_con_in: endpoint {
+- remote-endpoint = <&hdmi1_out_con>;
+- };
+- };
+- };
+-
+- leds {
+- compatible = "gpio-leds";
+- pinctrl-names = "default";
+- pinctrl-0 = <&led_rgb_b>;
+-
+- led_rgb_b {
+- function = LED_FUNCTION_STATUS;
+- color = <LED_COLOR_ID_BLUE>;
+- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+- };
+- };
+-
+- fan: pwm-fan {
+- compatible = "pwm-fan";
+- cooling-levels = <0 120 150 180 210 240 255>;
+- fan-supply = <&vcc5v0_sys>;
+- pwms = <&pwm1 0 50000 0>;
+- #cooling-cells = <2>;
+- };
+-
+- rfkill {
+- compatible = "rfkill-gpio";
+- label = "rfkill-m2-wlan";
+- radio-type = "wlan";
+- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+- };
+-
+- rfkill-bt {
+- compatible = "rfkill-gpio";
+- label = "rfkill-m2-bt";
+- radio-type = "bluetooth";
+- shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+- };
+-
+- vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
+- compatible = "regulator-fixed";
+- enable-active-high;
+- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&pcie2_0_vcc3v3_en>;
+- regulator-name = "vcc3v3_pcie2x1l0";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- startup-delay-us = <50000>;
+- vin-supply = <&vcc5v0_sys>;
+- };
+-
+- vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc3v3_pcie2x1l2";
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- startup-delay-us = <5000>;
+- vin-supply = <&vcc_3v3_s3>;
+- };
+-
+- vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
+- compatible = "regulator-fixed";
+- enable-active-high;
+- gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&pcie3_vcc3v3_en>;
+- regulator-name = "vcc3v3_pcie30";
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- startup-delay-us = <5000>;
+- vin-supply = <&vcc5v0_sys>;
+- };
+-
+- vcc5v0_host: regulator-vcc5v0-host {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc5v0_host";
+- regulator-boot-on;
+- regulator-always-on;
+- regulator-min-microvolt = <5000000>;
+- regulator-max-microvolt = <5000000>;
+- enable-active-high;
+- gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&vcc5v0_host_en>;
+- vin-supply = <&vcc5v0_sys>;
+- };
+-
+- vcc5v0_sys: regulator-vcc5v0-sys {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc5v0_sys";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <5000000>;
+- regulator-max-microvolt = <5000000>;
+- };
+-
+- vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc_1v1_nldo_s3";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1100000>;
+- regulator-max-microvolt = <1100000>;
+- vin-supply = <&vcc5v0_sys>;
+- };
+-};
+-
+-&combphy0_ps {
+- status = "okay";
+-};
+-
+-&combphy1_ps {
+- status = "okay";
+-};
+-
+-&combphy2_psu {
+- status = "okay";
+-};
+-
+-&cpu_b0 {
+- cpu-supply = <&vdd_cpu_big0_s0>;
+-};
+-
+-&cpu_b1 {
+- cpu-supply = <&vdd_cpu_big0_s0>;
+-};
+-
+-&cpu_b2 {
+- cpu-supply = <&vdd_cpu_big1_s0>;
+-};
+-
+-&cpu_b3 {
+- cpu-supply = <&vdd_cpu_big1_s0>;
+-};
+-
+-&cpu_l0 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&cpu_l1 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&cpu_l2 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&cpu_l3 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&gpu {
+- mali-supply = <&vdd_gpu_s0>;
+- status = "okay";
+-};
+-
+-&hdmi0 {
+- status = "okay";
+-};
+-
+-&hdmi0_in {
+- hdmi0_in_vp0: endpoint {
+- remote-endpoint = <&vp0_out_hdmi0>;
+- };
+-};
+-
+-&hdmi0_out {
+- hdmi0_out_con: endpoint {
+- remote-endpoint = <&hdmi0_con_in>;
+- };
+-};
+-
+-&hdmi0_sound {
+- status = "okay";
+-};
+-
+-&hdmi1 {
+- pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
+- &hdmim1_tx1_scl &hdmim1_tx1_sda>;
+- status = "okay";
+-};
+-
+-&hdmi1_in {
+- hdmi1_in_vp1: endpoint {
+- remote-endpoint = <&vp1_out_hdmi1>;
+- };
+-};
+-
+-&hdmi1_out {
+- hdmi1_out_con: endpoint {
+- remote-endpoint = <&hdmi1_con_in>;
+- };
+-};
+-
+-&hdmi1_sound {
+- status = "okay";
+-};
+-
+-&hdmi_receiver_cma {
+- status = "okay";
+-};
+-
+-&hdmi_receiver {
+- hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+- pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
+- pinctrl-names = "default";
+- status = "okay";
+-};
+-
+-&hdptxphy0 {
+- status = "okay";
+-};
+-
+-&hdptxphy1 {
+- status = "okay";
+-};
+-
+-&i2c0 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&i2c0m2_xfer>;
+- status = "okay";
+-
+- vdd_cpu_big0_s0: regulator@42 {
+- compatible = "rockchip,rk8602";
+- reg = <0x42>;
+- fcs,suspend-voltage-selector = <1>;
+- regulator-name = "vdd_cpu_big0_s0";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <1050000>;
+- regulator-ramp-delay = <2300>;
+- vin-supply = <&vcc5v0_sys>;
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_cpu_big1_s0: regulator@43 {
+- compatible = "rockchip,rk8603", "rockchip,rk8602";
+- reg = <0x43>;
+- fcs,suspend-voltage-selector = <1>;
+- regulator-name = "vdd_cpu_big1_s0";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <1050000>;
+- regulator-ramp-delay = <2300>;
+- vin-supply = <&vcc5v0_sys>;
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-};
+-
+-&i2c6 {
+- status = "okay";
+-
+- hym8563: rtc@51 {
+- compatible = "haoyu,hym8563";
+- reg = <0x51>;
+- #clock-cells = <0>;
+- clock-output-names = "hym8563";
+- pinctrl-names = "default";
+- pinctrl-0 = <&hym8563_int>;
+- interrupt-parent = <&gpio0>;
+- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+- wakeup-source;
+- };
+-};
+-
+-&i2c7 {
+- status = "okay";
+-
+- es8316: audio-codec@11 {
+- compatible = "everest,es8316";
+- reg = <0x11>;
+- clocks = <&cru I2S0_8CH_MCLKOUT>;
+- clock-names = "mclk";
+- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+- assigned-clock-rates = <12288000>;
+- #sound-dai-cells = <0>;
+-
+- port {
+- es8316_p0_0: endpoint {
+- remote-endpoint = <&i2s0_8ch_p0_0>;
+- };
+- };
+- };
+-};
+-
+-&i2s0_8ch {
+- pinctrl-names = "default";
+- pinctrl-0 = <&i2s0_lrck
+- &i2s0_mclk
+- &i2s0_sclk
+- &i2s0_sdi0
+- &i2s0_sdo0>;
+- status = "okay";
+-
+- i2s0_8ch_p0: port {
+- i2s0_8ch_p0_0: endpoint {
+- dai-format = "i2s";
+- mclk-fs = <256>;
+- remote-endpoint = <&es8316_p0_0>;
+- };
+- };
+-};
+-
+-&i2s5_8ch {
+- status = "okay";
+-};
+-
+-&i2s6_8ch {
+- status = "okay";
+-};
+-
+-&package_thermal {
+- polling-delay = <1000>;
+-
+- trips {
+- package_fan0: package-fan0 {
+- temperature = <55000>;
+- hysteresis = <2000>;
+- type = "active";
+- };
+-
+- package_fan1: package-fan1 {
+- temperature = <65000>;
+- hysteresis = <2000>;
+- type = "active";
+- };
+- };
+-
+- cooling-maps {
+- map0 {
+- trip = <&package_fan0>;
+- cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+- };
+-
+- map1 {
+- trip = <&package_fan1>;
+- cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+- };
+- };
+-};
+-
+-&pcie2x1l0 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pcie2_0_rst>;
+- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
+- status = "okay";
+-};
+-
+-&pcie2x1l2 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pcie2_2_rst>;
+- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+- vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
+- status = "okay";
+-};
+-
+-&pcie30phy {
+- status = "okay";
+-};
+-
+-&pcie3x4 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pcie3_rst>;
+- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+- vpcie3v3-supply = <&vcc3v3_pcie30>;
+- status = "okay";
+-};
+-
+-&pd_gpu {
+- domain-supply = <&vdd_gpu_s0>;
+-};
+-
+-&pinctrl {
+- hdmirx {
+- hdmirx_hpd: hdmirx-5v-detection {
+- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- hym8563 {
+- hym8563_int: hym8563-int {
+- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- leds {
+- led_rgb_b: led-rgb-b {
+- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- sound {
+- hp_detect: hp-detect {
+- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- pcie2 {
+- pcie2_0_rst: pcie2-0-rst {
+- rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+- pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
+- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+- pcie2_2_rst: pcie2-2-rst {
+- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- pcie3 {
+- pcie3_rst: pcie3-rst {
+- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+- pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- usb {
+- vcc5v0_host_en: vcc5v0-host-en {
+- rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-};
+-
+-&pwm1 {
+- status = "okay";
+-};
+-
+-&saradc {
+- vref-supply = <&avcc_1v8_s0>;
+- status = "okay";
+-};
+-
+-&sdhci {
+- bus-width = <8>;
+- no-sdio;
+- no-sd;
+- non-removable;
+- mmc-hs400-1_8v;
+- mmc-hs400-enhanced-strobe;
+- status = "okay";
+-};
+-
+-&sdmmc {
+- max-frequency = <200000000>;
+- no-sdio;
+- no-mmc;
+- bus-width = <4>;
+- cap-mmc-highspeed;
+- cap-sd-highspeed;
+- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+- disable-wp;
+- sd-uhs-sdr104;
+- vmmc-supply = <&vcc_3v3_s3>;
+- vqmmc-supply = <&vccio_sd_s0>;
+- status = "okay";
+ };
+
+ &sdio {
+@@ -551,435 +30,23 @@
+ status = "okay";
+ };
+
+-&sfc {
+- pinctrl-names = "default";
+- pinctrl-0 = <&fspim2_pins>;
+- status = "okay";
+-
+- flash@0 {
+- compatible = "jedec,spi-nor";
+- reg = <0>;
+- spi-max-frequency = <104000000>;
+- spi-rx-bus-width = <4>;
+- spi-tx-bus-width = <1>;
+- vcc-supply = <&vcc_3v3_s3>;
+- };
+-};
+-
+ &uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6m1_xfer &uart6m1_ctsn &uart6m1_rtsn>;
+ status = "okay";
+ };
+
+-&spi2 {
+- status = "okay";
+- assigned-clocks = <&cru CLK_SPI2>;
+- assigned-clock-rates = <200000000>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+- num-cs = <1>;
+-
+- pmic@0 {
+- compatible = "rockchip,rk806";
+- spi-max-frequency = <1000000>;
+- reg = <0x0>;
+-
+- interrupt-parent = <&gpio0>;
+- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+-
+- pinctrl-names = "default";
+- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+-
+- system-power-controller;
+-
+- vcc1-supply = <&vcc5v0_sys>;
+- vcc2-supply = <&vcc5v0_sys>;
+- vcc3-supply = <&vcc5v0_sys>;
+- vcc4-supply = <&vcc5v0_sys>;
+- vcc5-supply = <&vcc5v0_sys>;
+- vcc6-supply = <&vcc5v0_sys>;
+- vcc7-supply = <&vcc5v0_sys>;
+- vcc8-supply = <&vcc5v0_sys>;
+- vcc9-supply = <&vcc5v0_sys>;
+- vcc10-supply = <&vcc5v0_sys>;
+- vcc11-supply = <&vcc_2v0_pldo_s3>;
+- vcc12-supply = <&vcc5v0_sys>;
+- vcc13-supply = <&vcc_1v1_nldo_s3>;
+- vcc14-supply = <&vcc_1v1_nldo_s3>;
+- vcca-supply = <&vcc5v0_sys>;
+-
+- gpio-controller;
+- #gpio-cells = <2>;
+-
+- rk806_dvs1_null: dvs1-null-pins {
+- pins = "gpio_pwrctrl1";
+- function = "pin_fun0";
+- };
+-
+- rk806_dvs2_null: dvs2-null-pins {
+- pins = "gpio_pwrctrl2";
+- function = "pin_fun0";
+- };
+-
+- rk806_dvs3_null: dvs3-null-pins {
+- pins = "gpio_pwrctrl3";
+- function = "pin_fun0";
+- };
+-
+- regulators {
+- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <950000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_gpu_s0";
+- regulator-enable-ramp-delay = <400>;
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <950000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_cpu_lit_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_log_s0: dcdc-reg3 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <675000>;
+- regulator-max-microvolt = <750000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_log_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <750000>;
+- };
+- };
+-
+- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <950000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_vdenc_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_ddr_s0: dcdc-reg5 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <675000>;
+- regulator-max-microvolt = <900000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_ddr_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <850000>;
+- };
+- };
+-
+- vdd2_ddr_s3: dcdc-reg6 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-name = "vdd2_ddr_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- };
+- };
+-
+- vcc_2v0_pldo_s3: dcdc-reg7 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <2000000>;
+- regulator-max-microvolt = <2000000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_2v0_pldo_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <2000000>;
+- };
+- };
+-
+- vcc_3v3_s3: dcdc-reg8 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-name = "vcc_3v3_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <3300000>;
+- };
+- };
+-
+- vddq_ddr_s0: dcdc-reg9 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-name = "vddq_ddr_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vcc_1v8_s3: dcdc-reg10 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "vcc_1v8_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <1800000>;
+- };
+- };
+-
+- avcc_1v8_s0: pldo-reg1 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "avcc_1v8_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vcc_1v8_s0: pldo-reg2 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "vcc_1v8_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <1800000>;
+- };
+- };
+-
+- avdd_1v2_s0: pldo-reg3 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1200000>;
+- regulator-max-microvolt = <1200000>;
+- regulator-name = "avdd_1v2_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vcc_3v3_s0: pldo-reg4 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vcc_3v3_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vccio_sd_s0: pldo-reg5 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vccio_sd_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- pldo6_s3: pldo-reg6 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "pldo6_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <1800000>;
+- };
+- };
+-
+- vdd_0v75_s3: nldo-reg1 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <750000>;
+- regulator-max-microvolt = <750000>;
+- regulator-name = "vdd_0v75_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <750000>;
+- };
+- };
+-
+- vdd_ddr_pll_s0: nldo-reg2 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <850000>;
+- regulator-max-microvolt = <850000>;
+- regulator-name = "vdd_ddr_pll_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <850000>;
+- };
+- };
+-
+- avdd_0v75_s0: nldo-reg3 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <750000>;
+- regulator-max-microvolt = <750000>;
+- regulator-name = "avdd_0v75_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_0v85_s0: nldo-reg4 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <850000>;
+- regulator-max-microvolt = <850000>;
+- regulator-name = "vdd_0v85_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_0v75_s0: nldo-reg5 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <750000>;
+- regulator-max-microvolt = <750000>;
+- regulator-name = "vdd_0v75_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
++&pinctrl {
++ usb {
++ vcc5v0_host_en: vcc5v0-host-en {
++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+ };
+
+-&tsadc {
+- status = "okay";
+-};
+-
+-&uart2 {
+- pinctrl-0 = <&uart2m0_xfer>;
+- status = "okay";
+-};
+-
+-&u2phy1 {
+- status = "okay";
+-};
+-
+-&u2phy1_otg {
+- status = "okay";
+-};
+-
+-&u2phy2 {
+- status = "okay";
+-};
+-
+-&u2phy2_host {
+- /* connected to USB hub, which is powered by vcc5v0_sys */
+- phy-supply = <&vcc5v0_sys>;
+- status = "okay";
+-};
+-
+-&u2phy3 {
+- status = "okay";
+-};
+-
+-&u2phy3_host {
+- phy-supply = <&vcc5v0_host>;
+- status = "okay";
+-};
+-
+-&usbdp_phy1 {
+- status = "okay";
+-};
+-
+-&usb_host0_ehci {
+- status = "okay";
+-};
+-
+-&usb_host0_ohci {
+- status = "okay";
+-};
+-
+-&usb_host1_ehci {
+- status = "okay";
+-};
+-
+-&usb_host1_ohci {
+- status = "okay";
+-};
+-
+-&usb_host1_xhci {
+- dr_mode = "host";
+- status = "okay";
+-};
+-
+-&usb_host2_xhci {
+- status = "okay";
+-};
+-
+-&vop {
+- status = "okay";
+-};
+-
+-&vop_mmu {
+- status = "okay";
+-};
+-
+-&vp0 {
+- vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+- remote-endpoint = <&hdmi0_in_vp0>;
+- };
+-};
+-
+-&vp1 {
+- vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
+- reg = <ROCKCHIP_VOP2_EP_HDMI1>;
+- remote-endpoint = <&hdmi1_in_vp1>;
+- };
++&vcc5v0_host {
++ enable-active-high;
++ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vcc5v0_host_en>;
+ };
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi
+@@ -0,0 +1,945 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3588.dtsi"
++
++/ {
++ aliases {
++ mmc0 = &sdhci;
++ mmc1 = &sdmmc;
++ mmc2 = &sdio;
++ };
++
++ chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ analog-sound {
++ compatible = "audio-graph-card";
++ label = "rk3588-es8316";
++
++ widgets = "Microphone", "Mic Jack",
++ "Headphone", "Headphones";
++
++ routing = "MIC2", "Mic Jack",
++ "Headphones", "HPOL",
++ "Headphones", "HPOR";
++
++ dais = <&i2s0_8ch_p0>;
++ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hp_detect>;
++ };
++
++ hdmi0-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi0_con_in: endpoint {
++ remote-endpoint = <&hdmi0_out_con>;
++ };
++ };
++ };
++
++ hdmi1-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi1_con_in: endpoint {
++ remote-endpoint = <&hdmi1_out_con>;
++ };
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&led_rgb_b>;
++
++ led_rgb_b {
++ function = LED_FUNCTION_STATUS;
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ fan: pwm-fan {
++ compatible = "pwm-fan";
++ cooling-levels = <0 120 150 180 210 240 255>;
++ fan-supply = <&vcc5v0_sys>;
++ pwms = <&pwm1 0 50000 0>;
++ #cooling-cells = <2>;
++ };
++
++ rfkill {
++ compatible = "rfkill-gpio";
++ label = "rfkill-m2-wlan";
++ radio-type = "wlan";
++ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
++ };
++
++ rfkill-bt {
++ compatible = "rfkill-gpio";
++ label = "rfkill-m2-bt";
++ radio-type = "bluetooth";
++ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
++ };
++
++ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
++ regulator-name = "vcc3v3_pcie2x1l0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <50000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_pcie2x1l2";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <5000>;
++ vin-supply = <&vcc_3v3_s3>;
++ };
++
++ vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie3_vcc3v3_en>;
++ regulator-name = "vcc3v3_pcie30";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <5000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc5v0_host: regulator-vcc5v0-host {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_host";
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc5v0_sys: regulator-vcc5v0-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_1v1_nldo_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++};
++
++&combphy0_ps {
++ status = "okay";
++};
++
++&combphy1_ps {
++ status = "okay";
++};
++
++&combphy2_psu {
++ status = "okay";
++};
++
++&cpu_b0 {
++ cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b1 {
++ cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b2 {
++ cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_b3 {
++ cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_l0 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l1 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l2 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l3 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&gpu {
++ mali-supply = <&vdd_gpu_s0>;
++ status = "okay";
++};
++
++&hdmi0 {
++ status = "okay";
++};
++
++&hdmi0_in {
++ hdmi0_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi0>;
++ };
++};
++
++&hdmi0_out {
++ hdmi0_out_con: endpoint {
++ remote-endpoint = <&hdmi0_con_in>;
++ };
++};
++
++&hdmi0_sound {
++ status = "okay";
++};
++
++&hdmi1 {
++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
++ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
++ status = "okay";
++};
++
++&hdmi1_in {
++ hdmi1_in_vp1: endpoint {
++ remote-endpoint = <&vp1_out_hdmi1>;
++ };
++};
++
++&hdmi1_out {
++ hdmi1_out_con: endpoint {
++ remote-endpoint = <&hdmi1_con_in>;
++ };
++};
++
++&hdmi1_sound {
++ status = "okay";
++};
++
++&hdmi_receiver_cma {
++ status = "okay";
++};
++
++&hdmi_receiver {
++ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
++ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
++ pinctrl-names = "default";
++ status = "okay";
++};
++
++&hdptxphy0 {
++ status = "okay";
++};
++
++&hdptxphy1 {
++ status = "okay";
++};
++
++&i2c0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0m2_xfer>;
++ status = "okay";
++
++ vdd_cpu_big0_s0: regulator@42 {
++ compatible = "rockchip,rk8602";
++ reg = <0x42>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu_big0_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1050000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_big1_s0: regulator@43 {
++ compatible = "rockchip,rk8603", "rockchip,rk8602";
++ reg = <0x43>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu_big1_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1050000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++};
++
++&i2c6 {
++ status = "okay";
++
++ hym8563: rtc@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ #clock-cells = <0>;
++ clock-output-names = "hym8563";
++ pinctrl-names = "default";
++ pinctrl-0 = <&hym8563_int>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
++ wakeup-source;
++ };
++};
++
++&i2c7 {
++ status = "okay";
++
++ es8316: audio-codec@11 {
++ compatible = "everest,es8316";
++ reg = <0x11>;
++ clocks = <&cru I2S0_8CH_MCLKOUT>;
++ clock-names = "mclk";
++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
++ assigned-clock-rates = <12288000>;
++ #sound-dai-cells = <0>;
++
++ port {
++ es8316_p0_0: endpoint {
++ remote-endpoint = <&i2s0_8ch_p0_0>;
++ };
++ };
++ };
++};
++
++&i2s0_8ch {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2s0_lrck
++ &i2s0_mclk
++ &i2s0_sclk
++ &i2s0_sdi0
++ &i2s0_sdo0>;
++ status = "okay";
++
++ i2s0_8ch_p0: port {
++ i2s0_8ch_p0_0: endpoint {
++ dai-format = "i2s";
++ mclk-fs = <256>;
++ remote-endpoint = <&es8316_p0_0>;
++ };
++ };
++};
++
++&i2s5_8ch {
++ status = "okay";
++};
++
++&i2s6_8ch {
++ status = "okay";
++};
++
++&package_thermal {
++ polling-delay = <1000>;
++
++ trips {
++ package_fan0: package-fan0 {
++ temperature = <55000>;
++ hysteresis = <2000>;
++ type = "active";
++ };
++
++ package_fan1: package-fan1 {
++ temperature = <65000>;
++ hysteresis = <2000>;
++ type = "active";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&package_fan0>;
++ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
++ };
++
++ map1 {
++ trip = <&package_fan1>;
++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
++ };
++ };
++};
++
++&pcie2x1l0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie2_0_rst>;
++ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
++ status = "okay";
++};
++
++&pcie2x1l2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie2_2_rst>;
++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
++ status = "okay";
++};
++
++&pcie30phy {
++ status = "okay";
++};
++
++&pcie3x4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie3_rst>;
++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pcie30>;
++ status = "okay";
++};
++
++&pd_gpu {
++ domain-supply = <&vdd_gpu_s0>;
++};
++
++&pinctrl {
++ hdmirx {
++ hdmirx_hpd: hdmirx-5v-detection {
++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ hym8563 {
++ hym8563_int: hym8563-int {
++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ leds {
++ led_rgb_b: led-rgb-b {
++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ sound {
++ hp_detect: hp-detect {
++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie2 {
++ pcie2_0_rst: pcie2-0-rst {
++ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ pcie2_2_rst: pcie2-2-rst {
++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie3 {
++ pcie3_rst: pcie3-rst {
++ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ pcie3_vcc3v3_en: pcie3-vcc3v3-en {
++ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&pwm1 {
++ status = "okay";
++};
++
++&saradc {
++ vref-supply = <&avcc_1v8_s0>;
++ status = "okay";
++};
++
++&sdhci {
++ bus-width = <8>;
++ no-sdio;
++ no-sd;
++ non-removable;
++ mmc-hs400-1_8v;
++ mmc-hs400-enhanced-strobe;
++ status = "okay";
++};
++
++&sdmmc {
++ max-frequency = <200000000>;
++ no-sdio;
++ no-mmc;
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
++ disable-wp;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3_s3>;
++ vqmmc-supply = <&vccio_sd_s0>;
++ status = "okay";
++};
++
++&sfc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&fspim2_pins>;
++ status = "okay";
++
++ flash@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <104000000>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <1>;
++ vcc-supply = <&vcc_3v3_s3>;
++ };
++};
++
++&spi2 {
++ status = "okay";
++ assigned-clocks = <&cru CLK_SPI2>;
++ assigned-clock-rates = <200000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
++ num-cs = <1>;
++
++ pmic@0 {
++ compatible = "rockchip,rk806";
++ spi-max-frequency = <1000000>;
++ reg = <0x0>;
++
++ interrupt-parent = <&gpio0>;
++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
++ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
++
++ system-power-controller;
++
++ vcc1-supply = <&vcc5v0_sys>;
++ vcc2-supply = <&vcc5v0_sys>;
++ vcc3-supply = <&vcc5v0_sys>;
++ vcc4-supply = <&vcc5v0_sys>;
++ vcc5-supply = <&vcc5v0_sys>;
++ vcc6-supply = <&vcc5v0_sys>;
++ vcc7-supply = <&vcc5v0_sys>;
++ vcc8-supply = <&vcc5v0_sys>;
++ vcc9-supply = <&vcc5v0_sys>;
++ vcc10-supply = <&vcc5v0_sys>;
++ vcc11-supply = <&vcc_2v0_pldo_s3>;
++ vcc12-supply = <&vcc5v0_sys>;
++ vcc13-supply = <&vcc_1v1_nldo_s3>;
++ vcc14-supply = <&vcc_1v1_nldo_s3>;
++ vcca-supply = <&vcc5v0_sys>;
++
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ rk806_dvs1_null: dvs1-null-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs2_null: dvs2-null-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs3_null: dvs3-null-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun0";
++ };
++
++ regulators {
++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_gpu_s0";
++ regulator-enable-ramp-delay = <400>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_cpu_lit_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_log_s0: dcdc-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <675000>;
++ regulator-max-microvolt = <750000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_log_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_vdenc_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_ddr_s0: dcdc-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <675000>;
++ regulator-max-microvolt = <900000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_ddr_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ vdd2_ddr_s3: dcdc-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vdd2_ddr_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_2v0_pldo_s3: dcdc-reg7 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <2000000>;
++ regulator-max-microvolt = <2000000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_2v0_pldo_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <2000000>;
++ };
++ };
++
++ vcc_3v3_s3: dcdc-reg8 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vddq_ddr_s0: dcdc-reg9 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vddq_ddr_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8_s3: dcdc-reg10 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ avcc_1v8_s0: pldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "avcc_1v8_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8_s0: pldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ avdd_1v2_s0: pldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-name = "avdd_1v2_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_3v3_s0: pldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vcc_3v3_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vccio_sd_s0: pldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vccio_sd_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ pldo6_s3: pldo-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "pldo6_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_0v75_s3: nldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdd_0v75_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdd_ddr_pll_s0: nldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "vdd_ddr_pll_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ avdd_0v75_s0: nldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "avdd_0v75_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_0v85_s0: nldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "vdd_0v85_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_0v75_s0: nldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdd_0v75_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++&tsadc {
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-0 = <&uart2m0_xfer>;
++ status = "okay";
++};
++
++&u2phy1 {
++ status = "okay";
++};
++
++&u2phy1_otg {
++ status = "okay";
++};
++
++&u2phy2 {
++ status = "okay";
++};
++
++&u2phy2_host {
++ /* connected to USB hub, which is powered by vcc5v0_sys */
++ phy-supply = <&vcc5v0_sys>;
++ status = "okay";
++};
++
++&u2phy3 {
++ status = "okay";
++};
++
++&u2phy3_host {
++ phy-supply = <&vcc5v0_host>;
++ status = "okay";
++};
++
++&usbdp_phy1 {
++ status = "okay";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
++
++&usb_host1_ehci {
++ status = "okay";
++};
++
++&usb_host1_ohci {
++ status = "okay";
++};
++
++&usb_host1_xhci {
++ dr_mode = "host";
++ status = "okay";
++};
++
++&usb_host2_xhci {
++ status = "okay";
++};
++
++&vop {
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi0_in_vp0>;
++ };
++};
++
++&vp1 {
++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI1>;
++ remote-endpoint = <&hdmi1_in_vp1>;
++ };
++};
--- /dev/null
+From 376cb9696298df2028afb620a9dc6c4b10a18605 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 8 May 2025 19:48:53 +0200
+Subject: arm64: dts: rockchip: add Rock 5B+
+
+Add ROCK 5B+, which is an improved version of the ROCK 5B with the
+following changes:
+
+ * Memory LPDDR4X -> LPDDR5
+ * HDMI input connector size
+ * eMMC socket -> onboard
+ * M.2 E-Key is replaced by onboard RTL8852BE WLAN/BT
+ * M.2 M-Key 1x4 lanes is replaced by 2x2 lanes
+ * Added M.2 B-Key for USB connected WWAN modules (untested)
+ * Add second camera port (not yet supported in upstream Linux)
+ * Add dedicated USB-C port for device power (no impact in DT;
+ the existing port has not been changed and the new port is
+ handled by CH224D standalone chip)
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20250508-rock5bp-for-upstream-v2-4-677033cc1ac2@kernel.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -142,6 +142,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
+@@ -0,0 +1,113 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk3588-rock-5b.dtsi"
++
++/ {
++ model = "Radxa ROCK 5B+";
++ compatible = "radxa,rock-5b-plus", "rockchip,rk3588";
++
++ rfkill-wwan {
++ compatible = "rfkill-gpio";
++ label = "rfkill-m2-wwan";
++ radio-type = "wwan";
++ shutdown-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
++ };
++
++ vcc3v3_4g: regulator-vcc3v3-4g {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
++ /* pinctrl for the GPIO is requested by vcc3v3_pcie2x1l0 */
++ regulator-name = "vcc3v3_4g";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <50000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc3v3_wwan_pwr: regulator-vcc3v3-wwan {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&wwan_power_en>;
++ regulator-name = "vcc3v3_wwan_pwr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc3v3_4g>;
++ };
++};
++
++&gpio0 {
++ wwan-disable2-n-hog {
++ gpios = <RK_PB2 GPIO_ACTIVE_LOW>;
++ output-low;
++ line-name = "M.2 B-key W_DISABLE2#";
++ gpio-hog;
++ };
++};
++
++&gpio2 {
++ wwan-reset-n-hog {
++ gpios = <RK_PB3 GPIO_ACTIVE_LOW>;
++ output-low;
++ line-name = "M.2 B-key RESET#";
++ gpio-hog;
++ };
++
++ wwan-wake-n-hog {
++ gpios = <RK_PB2 GPIO_ACTIVE_LOW>;
++ input;
++ line-name = "M.2 B-key WoWWAN#";
++ gpio-hog;
++ };
++};
++
++&pcie30phy {
++ data-lanes = <1 1 2 2>;
++};
++
++&pcie3x2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie3x2_rst>;
++ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pcie30>;
++ status = "okay";
++};
++
++&pcie3x4 {
++ num-lanes = <2>;
++};
++
++&pinctrl {
++ wwan {
++ wwan_power_en: wwan-pwr-en {
++ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie3 {
++ pcie3x2_rst: pcie3x2-rst {
++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ usb {
++ vcc5v0_host_en: vcc5v0-host-en {
++ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&vcc5v0_host {
++ enable-active-high;
++ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vcc5v0_host_en>;
++};
--- /dev/null
+From 8b76abf78321ea3361c01e849c8dc3a6793c05d6 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 20 May 2025 20:50:09 +0200
+Subject: arm64: dts: rockchip: rename rk3588-rock-5b.dtsi
+
+As subsequent patches will add ROCK 5T support, rename the .dtsi file to
+reflect that it's shared between ROCK 5B, ROCK 5B+ and ROCK 5T.
+
+This is done separately from moving the 5B and 5B+ only nodes to a
+common tree so that the history stays bisectable and the diff easily
+reviewable.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-2-1f1971850a20@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
+@@ -2,7 +2,7 @@
+
+ /dts-v1/;
+
+-#include "rk3588-rock-5b.dtsi"
++#include "rk3588-rock-5b-5bp-5t.dtsi"
+
+ / {
+ model = "Radxa ROCK 5B+";
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -2,7 +2,7 @@
+
+ /dts-v1/;
+
+-#include "rk3588-rock-5b.dtsi"
++#include "rk3588-rock-5b-5bp-5t.dtsi"
+
+ / {
+ model = "Radxa ROCK 5B";
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
+@@ -0,0 +1,945 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3588.dtsi"
++
++/ {
++ aliases {
++ mmc0 = &sdhci;
++ mmc1 = &sdmmc;
++ mmc2 = &sdio;
++ };
++
++ chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ analog-sound {
++ compatible = "audio-graph-card";
++ label = "rk3588-es8316";
++
++ widgets = "Microphone", "Mic Jack",
++ "Headphone", "Headphones";
++
++ routing = "MIC2", "Mic Jack",
++ "Headphones", "HPOL",
++ "Headphones", "HPOR";
++
++ dais = <&i2s0_8ch_p0>;
++ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hp_detect>;
++ };
++
++ hdmi0-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi0_con_in: endpoint {
++ remote-endpoint = <&hdmi0_out_con>;
++ };
++ };
++ };
++
++ hdmi1-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi1_con_in: endpoint {
++ remote-endpoint = <&hdmi1_out_con>;
++ };
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&led_rgb_b>;
++
++ led_rgb_b {
++ function = LED_FUNCTION_STATUS;
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ fan: pwm-fan {
++ compatible = "pwm-fan";
++ cooling-levels = <0 120 150 180 210 240 255>;
++ fan-supply = <&vcc5v0_sys>;
++ pwms = <&pwm1 0 50000 0>;
++ #cooling-cells = <2>;
++ };
++
++ rfkill {
++ compatible = "rfkill-gpio";
++ label = "rfkill-m2-wlan";
++ radio-type = "wlan";
++ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
++ };
++
++ rfkill-bt {
++ compatible = "rfkill-gpio";
++ label = "rfkill-m2-bt";
++ radio-type = "bluetooth";
++ shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
++ };
++
++ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
++ regulator-name = "vcc3v3_pcie2x1l0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <50000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_pcie2x1l2";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <5000>;
++ vin-supply = <&vcc_3v3_s3>;
++ };
++
++ vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie3_vcc3v3_en>;
++ regulator-name = "vcc3v3_pcie30";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <5000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc5v0_host: regulator-vcc5v0-host {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_host";
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc5v0_sys: regulator-vcc5v0-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_1v1_nldo_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++};
++
++&combphy0_ps {
++ status = "okay";
++};
++
++&combphy1_ps {
++ status = "okay";
++};
++
++&combphy2_psu {
++ status = "okay";
++};
++
++&cpu_b0 {
++ cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b1 {
++ cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b2 {
++ cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_b3 {
++ cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_l0 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l1 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l2 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l3 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&gpu {
++ mali-supply = <&vdd_gpu_s0>;
++ status = "okay";
++};
++
++&hdmi0 {
++ status = "okay";
++};
++
++&hdmi0_in {
++ hdmi0_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi0>;
++ };
++};
++
++&hdmi0_out {
++ hdmi0_out_con: endpoint {
++ remote-endpoint = <&hdmi0_con_in>;
++ };
++};
++
++&hdmi0_sound {
++ status = "okay";
++};
++
++&hdmi1 {
++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
++ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
++ status = "okay";
++};
++
++&hdmi1_in {
++ hdmi1_in_vp1: endpoint {
++ remote-endpoint = <&vp1_out_hdmi1>;
++ };
++};
++
++&hdmi1_out {
++ hdmi1_out_con: endpoint {
++ remote-endpoint = <&hdmi1_con_in>;
++ };
++};
++
++&hdmi1_sound {
++ status = "okay";
++};
++
++&hdmi_receiver_cma {
++ status = "okay";
++};
++
++&hdmi_receiver {
++ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
++ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
++ pinctrl-names = "default";
++ status = "okay";
++};
++
++&hdptxphy0 {
++ status = "okay";
++};
++
++&hdptxphy1 {
++ status = "okay";
++};
++
++&i2c0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0m2_xfer>;
++ status = "okay";
++
++ vdd_cpu_big0_s0: regulator@42 {
++ compatible = "rockchip,rk8602";
++ reg = <0x42>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu_big0_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1050000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_big1_s0: regulator@43 {
++ compatible = "rockchip,rk8603", "rockchip,rk8602";
++ reg = <0x43>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu_big1_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1050000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++};
++
++&i2c6 {
++ status = "okay";
++
++ hym8563: rtc@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ #clock-cells = <0>;
++ clock-output-names = "hym8563";
++ pinctrl-names = "default";
++ pinctrl-0 = <&hym8563_int>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
++ wakeup-source;
++ };
++};
++
++&i2c7 {
++ status = "okay";
++
++ es8316: audio-codec@11 {
++ compatible = "everest,es8316";
++ reg = <0x11>;
++ clocks = <&cru I2S0_8CH_MCLKOUT>;
++ clock-names = "mclk";
++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
++ assigned-clock-rates = <12288000>;
++ #sound-dai-cells = <0>;
++
++ port {
++ es8316_p0_0: endpoint {
++ remote-endpoint = <&i2s0_8ch_p0_0>;
++ };
++ };
++ };
++};
++
++&i2s0_8ch {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2s0_lrck
++ &i2s0_mclk
++ &i2s0_sclk
++ &i2s0_sdi0
++ &i2s0_sdo0>;
++ status = "okay";
++
++ i2s0_8ch_p0: port {
++ i2s0_8ch_p0_0: endpoint {
++ dai-format = "i2s";
++ mclk-fs = <256>;
++ remote-endpoint = <&es8316_p0_0>;
++ };
++ };
++};
++
++&i2s5_8ch {
++ status = "okay";
++};
++
++&i2s6_8ch {
++ status = "okay";
++};
++
++&package_thermal {
++ polling-delay = <1000>;
++
++ trips {
++ package_fan0: package-fan0 {
++ temperature = <55000>;
++ hysteresis = <2000>;
++ type = "active";
++ };
++
++ package_fan1: package-fan1 {
++ temperature = <65000>;
++ hysteresis = <2000>;
++ type = "active";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&package_fan0>;
++ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
++ };
++
++ map1 {
++ trip = <&package_fan1>;
++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
++ };
++ };
++};
++
++&pcie2x1l0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie2_0_rst>;
++ reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
++ status = "okay";
++};
++
++&pcie2x1l2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie2_2_rst>;
++ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
++ status = "okay";
++};
++
++&pcie30phy {
++ status = "okay";
++};
++
++&pcie3x4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie3_rst>;
++ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pcie30>;
++ status = "okay";
++};
++
++&pd_gpu {
++ domain-supply = <&vdd_gpu_s0>;
++};
++
++&pinctrl {
++ hdmirx {
++ hdmirx_hpd: hdmirx-5v-detection {
++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ hym8563 {
++ hym8563_int: hym8563-int {
++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ leds {
++ led_rgb_b: led-rgb-b {
++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ sound {
++ hp_detect: hp-detect {
++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie2 {
++ pcie2_0_rst: pcie2-0-rst {
++ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ pcie2_2_rst: pcie2-2-rst {
++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie3 {
++ pcie3_rst: pcie3-rst {
++ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ pcie3_vcc3v3_en: pcie3-vcc3v3-en {
++ rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&pwm1 {
++ status = "okay";
++};
++
++&saradc {
++ vref-supply = <&avcc_1v8_s0>;
++ status = "okay";
++};
++
++&sdhci {
++ bus-width = <8>;
++ no-sdio;
++ no-sd;
++ non-removable;
++ mmc-hs400-1_8v;
++ mmc-hs400-enhanced-strobe;
++ status = "okay";
++};
++
++&sdmmc {
++ max-frequency = <200000000>;
++ no-sdio;
++ no-mmc;
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
++ disable-wp;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3_s3>;
++ vqmmc-supply = <&vccio_sd_s0>;
++ status = "okay";
++};
++
++&sfc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&fspim2_pins>;
++ status = "okay";
++
++ flash@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <104000000>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <1>;
++ vcc-supply = <&vcc_3v3_s3>;
++ };
++};
++
++&spi2 {
++ status = "okay";
++ assigned-clocks = <&cru CLK_SPI2>;
++ assigned-clock-rates = <200000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
++ num-cs = <1>;
++
++ pmic@0 {
++ compatible = "rockchip,rk806";
++ spi-max-frequency = <1000000>;
++ reg = <0x0>;
++
++ interrupt-parent = <&gpio0>;
++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
++ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
++
++ system-power-controller;
++
++ vcc1-supply = <&vcc5v0_sys>;
++ vcc2-supply = <&vcc5v0_sys>;
++ vcc3-supply = <&vcc5v0_sys>;
++ vcc4-supply = <&vcc5v0_sys>;
++ vcc5-supply = <&vcc5v0_sys>;
++ vcc6-supply = <&vcc5v0_sys>;
++ vcc7-supply = <&vcc5v0_sys>;
++ vcc8-supply = <&vcc5v0_sys>;
++ vcc9-supply = <&vcc5v0_sys>;
++ vcc10-supply = <&vcc5v0_sys>;
++ vcc11-supply = <&vcc_2v0_pldo_s3>;
++ vcc12-supply = <&vcc5v0_sys>;
++ vcc13-supply = <&vcc_1v1_nldo_s3>;
++ vcc14-supply = <&vcc_1v1_nldo_s3>;
++ vcca-supply = <&vcc5v0_sys>;
++
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ rk806_dvs1_null: dvs1-null-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs2_null: dvs2-null-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs3_null: dvs3-null-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun0";
++ };
++
++ regulators {
++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_gpu_s0";
++ regulator-enable-ramp-delay = <400>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_cpu_lit_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_log_s0: dcdc-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <675000>;
++ regulator-max-microvolt = <750000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_log_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_vdenc_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_ddr_s0: dcdc-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <675000>;
++ regulator-max-microvolt = <900000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_ddr_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ vdd2_ddr_s3: dcdc-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vdd2_ddr_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_2v0_pldo_s3: dcdc-reg7 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <2000000>;
++ regulator-max-microvolt = <2000000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_2v0_pldo_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <2000000>;
++ };
++ };
++
++ vcc_3v3_s3: dcdc-reg8 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vddq_ddr_s0: dcdc-reg9 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vddq_ddr_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8_s3: dcdc-reg10 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ avcc_1v8_s0: pldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "avcc_1v8_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8_s0: pldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ avdd_1v2_s0: pldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-name = "avdd_1v2_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_3v3_s0: pldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vcc_3v3_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vccio_sd_s0: pldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vccio_sd_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ pldo6_s3: pldo-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "pldo6_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_0v75_s3: nldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdd_0v75_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdd_ddr_pll_s0: nldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "vdd_ddr_pll_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ avdd_0v75_s0: nldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "avdd_0v75_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_0v85_s0: nldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "vdd_0v85_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_0v75_s0: nldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdd_0v75_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++&tsadc {
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-0 = <&uart2m0_xfer>;
++ status = "okay";
++};
++
++&u2phy1 {
++ status = "okay";
++};
++
++&u2phy1_otg {
++ status = "okay";
++};
++
++&u2phy2 {
++ status = "okay";
++};
++
++&u2phy2_host {
++ /* connected to USB hub, which is powered by vcc5v0_sys */
++ phy-supply = <&vcc5v0_sys>;
++ status = "okay";
++};
++
++&u2phy3 {
++ status = "okay";
++};
++
++&u2phy3_host {
++ phy-supply = <&vcc5v0_host>;
++ status = "okay";
++};
++
++&usbdp_phy1 {
++ status = "okay";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
++
++&usb_host1_ehci {
++ status = "okay";
++};
++
++&usb_host1_ohci {
++ status = "okay";
++};
++
++&usb_host1_xhci {
++ dr_mode = "host";
++ status = "okay";
++};
++
++&usb_host2_xhci {
++ status = "okay";
++};
++
++&vop {
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi0_in_vp0>;
++ };
++};
++
++&vp1 {
++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI1>;
++ remote-endpoint = <&hdmi1_in_vp1>;
++ };
++};
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi
++++ /dev/null
+@@ -1,945 +0,0 @@
+-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+-
+-/dts-v1/;
+-
+-#include <dt-bindings/gpio/gpio.h>
+-#include <dt-bindings/leds/common.h>
+-#include <dt-bindings/soc/rockchip,vop2.h>
+-#include "rk3588.dtsi"
+-
+-/ {
+- aliases {
+- mmc0 = &sdhci;
+- mmc1 = &sdmmc;
+- mmc2 = &sdio;
+- };
+-
+- chosen {
+- stdout-path = "serial2:1500000n8";
+- };
+-
+- analog-sound {
+- compatible = "audio-graph-card";
+- label = "rk3588-es8316";
+-
+- widgets = "Microphone", "Mic Jack",
+- "Headphone", "Headphones";
+-
+- routing = "MIC2", "Mic Jack",
+- "Headphones", "HPOL",
+- "Headphones", "HPOR";
+-
+- dais = <&i2s0_8ch_p0>;
+- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&hp_detect>;
+- };
+-
+- hdmi0-con {
+- compatible = "hdmi-connector";
+- type = "a";
+-
+- port {
+- hdmi0_con_in: endpoint {
+- remote-endpoint = <&hdmi0_out_con>;
+- };
+- };
+- };
+-
+- hdmi1-con {
+- compatible = "hdmi-connector";
+- type = "a";
+-
+- port {
+- hdmi1_con_in: endpoint {
+- remote-endpoint = <&hdmi1_out_con>;
+- };
+- };
+- };
+-
+- leds {
+- compatible = "gpio-leds";
+- pinctrl-names = "default";
+- pinctrl-0 = <&led_rgb_b>;
+-
+- led_rgb_b {
+- function = LED_FUNCTION_STATUS;
+- color = <LED_COLOR_ID_BLUE>;
+- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+- };
+- };
+-
+- fan: pwm-fan {
+- compatible = "pwm-fan";
+- cooling-levels = <0 120 150 180 210 240 255>;
+- fan-supply = <&vcc5v0_sys>;
+- pwms = <&pwm1 0 50000 0>;
+- #cooling-cells = <2>;
+- };
+-
+- rfkill {
+- compatible = "rfkill-gpio";
+- label = "rfkill-m2-wlan";
+- radio-type = "wlan";
+- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+- };
+-
+- rfkill-bt {
+- compatible = "rfkill-gpio";
+- label = "rfkill-m2-bt";
+- radio-type = "bluetooth";
+- shutdown-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+- };
+-
+- vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
+- compatible = "regulator-fixed";
+- enable-active-high;
+- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&pcie2_0_vcc3v3_en>;
+- regulator-name = "vcc3v3_pcie2x1l0";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- startup-delay-us = <50000>;
+- vin-supply = <&vcc5v0_sys>;
+- };
+-
+- vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc3v3_pcie2x1l2";
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- startup-delay-us = <5000>;
+- vin-supply = <&vcc_3v3_s3>;
+- };
+-
+- vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
+- compatible = "regulator-fixed";
+- enable-active-high;
+- gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&pcie3_vcc3v3_en>;
+- regulator-name = "vcc3v3_pcie30";
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- startup-delay-us = <5000>;
+- vin-supply = <&vcc5v0_sys>;
+- };
+-
+- vcc5v0_host: regulator-vcc5v0-host {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc5v0_host";
+- regulator-boot-on;
+- regulator-always-on;
+- regulator-min-microvolt = <5000000>;
+- regulator-max-microvolt = <5000000>;
+- vin-supply = <&vcc5v0_sys>;
+- };
+-
+- vcc5v0_sys: regulator-vcc5v0-sys {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc5v0_sys";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <5000000>;
+- regulator-max-microvolt = <5000000>;
+- };
+-
+- vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc_1v1_nldo_s3";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1100000>;
+- regulator-max-microvolt = <1100000>;
+- vin-supply = <&vcc5v0_sys>;
+- };
+-};
+-
+-&combphy0_ps {
+- status = "okay";
+-};
+-
+-&combphy1_ps {
+- status = "okay";
+-};
+-
+-&combphy2_psu {
+- status = "okay";
+-};
+-
+-&cpu_b0 {
+- cpu-supply = <&vdd_cpu_big0_s0>;
+-};
+-
+-&cpu_b1 {
+- cpu-supply = <&vdd_cpu_big0_s0>;
+-};
+-
+-&cpu_b2 {
+- cpu-supply = <&vdd_cpu_big1_s0>;
+-};
+-
+-&cpu_b3 {
+- cpu-supply = <&vdd_cpu_big1_s0>;
+-};
+-
+-&cpu_l0 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&cpu_l1 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&cpu_l2 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&cpu_l3 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&gpu {
+- mali-supply = <&vdd_gpu_s0>;
+- status = "okay";
+-};
+-
+-&hdmi0 {
+- status = "okay";
+-};
+-
+-&hdmi0_in {
+- hdmi0_in_vp0: endpoint {
+- remote-endpoint = <&vp0_out_hdmi0>;
+- };
+-};
+-
+-&hdmi0_out {
+- hdmi0_out_con: endpoint {
+- remote-endpoint = <&hdmi0_con_in>;
+- };
+-};
+-
+-&hdmi0_sound {
+- status = "okay";
+-};
+-
+-&hdmi1 {
+- pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
+- &hdmim1_tx1_scl &hdmim1_tx1_sda>;
+- status = "okay";
+-};
+-
+-&hdmi1_in {
+- hdmi1_in_vp1: endpoint {
+- remote-endpoint = <&vp1_out_hdmi1>;
+- };
+-};
+-
+-&hdmi1_out {
+- hdmi1_out_con: endpoint {
+- remote-endpoint = <&hdmi1_con_in>;
+- };
+-};
+-
+-&hdmi1_sound {
+- status = "okay";
+-};
+-
+-&hdmi_receiver_cma {
+- status = "okay";
+-};
+-
+-&hdmi_receiver {
+- hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+- pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
+- pinctrl-names = "default";
+- status = "okay";
+-};
+-
+-&hdptxphy0 {
+- status = "okay";
+-};
+-
+-&hdptxphy1 {
+- status = "okay";
+-};
+-
+-&i2c0 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&i2c0m2_xfer>;
+- status = "okay";
+-
+- vdd_cpu_big0_s0: regulator@42 {
+- compatible = "rockchip,rk8602";
+- reg = <0x42>;
+- fcs,suspend-voltage-selector = <1>;
+- regulator-name = "vdd_cpu_big0_s0";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <1050000>;
+- regulator-ramp-delay = <2300>;
+- vin-supply = <&vcc5v0_sys>;
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_cpu_big1_s0: regulator@43 {
+- compatible = "rockchip,rk8603", "rockchip,rk8602";
+- reg = <0x43>;
+- fcs,suspend-voltage-selector = <1>;
+- regulator-name = "vdd_cpu_big1_s0";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <1050000>;
+- regulator-ramp-delay = <2300>;
+- vin-supply = <&vcc5v0_sys>;
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-};
+-
+-&i2c6 {
+- status = "okay";
+-
+- hym8563: rtc@51 {
+- compatible = "haoyu,hym8563";
+- reg = <0x51>;
+- #clock-cells = <0>;
+- clock-output-names = "hym8563";
+- pinctrl-names = "default";
+- pinctrl-0 = <&hym8563_int>;
+- interrupt-parent = <&gpio0>;
+- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+- wakeup-source;
+- };
+-};
+-
+-&i2c7 {
+- status = "okay";
+-
+- es8316: audio-codec@11 {
+- compatible = "everest,es8316";
+- reg = <0x11>;
+- clocks = <&cru I2S0_8CH_MCLKOUT>;
+- clock-names = "mclk";
+- assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
+- assigned-clock-rates = <12288000>;
+- #sound-dai-cells = <0>;
+-
+- port {
+- es8316_p0_0: endpoint {
+- remote-endpoint = <&i2s0_8ch_p0_0>;
+- };
+- };
+- };
+-};
+-
+-&i2s0_8ch {
+- pinctrl-names = "default";
+- pinctrl-0 = <&i2s0_lrck
+- &i2s0_mclk
+- &i2s0_sclk
+- &i2s0_sdi0
+- &i2s0_sdo0>;
+- status = "okay";
+-
+- i2s0_8ch_p0: port {
+- i2s0_8ch_p0_0: endpoint {
+- dai-format = "i2s";
+- mclk-fs = <256>;
+- remote-endpoint = <&es8316_p0_0>;
+- };
+- };
+-};
+-
+-&i2s5_8ch {
+- status = "okay";
+-};
+-
+-&i2s6_8ch {
+- status = "okay";
+-};
+-
+-&package_thermal {
+- polling-delay = <1000>;
+-
+- trips {
+- package_fan0: package-fan0 {
+- temperature = <55000>;
+- hysteresis = <2000>;
+- type = "active";
+- };
+-
+- package_fan1: package-fan1 {
+- temperature = <65000>;
+- hysteresis = <2000>;
+- type = "active";
+- };
+- };
+-
+- cooling-maps {
+- map0 {
+- trip = <&package_fan0>;
+- cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+- };
+-
+- map1 {
+- trip = <&package_fan1>;
+- cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+- };
+- };
+-};
+-
+-&pcie2x1l0 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pcie2_0_rst>;
+- reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+- vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
+- status = "okay";
+-};
+-
+-&pcie2x1l2 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pcie2_2_rst>;
+- reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+- vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
+- status = "okay";
+-};
+-
+-&pcie30phy {
+- status = "okay";
+-};
+-
+-&pcie3x4 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pcie3_rst>;
+- reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+- vpcie3v3-supply = <&vcc3v3_pcie30>;
+- status = "okay";
+-};
+-
+-&pd_gpu {
+- domain-supply = <&vdd_gpu_s0>;
+-};
+-
+-&pinctrl {
+- hdmirx {
+- hdmirx_hpd: hdmirx-5v-detection {
+- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- hym8563 {
+- hym8563_int: hym8563-int {
+- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- leds {
+- led_rgb_b: led-rgb-b {
+- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- sound {
+- hp_detect: hp-detect {
+- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- pcie2 {
+- pcie2_0_rst: pcie2-0-rst {
+- rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+- pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
+- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+- pcie2_2_rst: pcie2-2-rst {
+- rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- pcie3 {
+- pcie3_rst: pcie3-rst {
+- rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+- pcie3_vcc3v3_en: pcie3-vcc3v3-en {
+- rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-};
+-
+-&pwm1 {
+- status = "okay";
+-};
+-
+-&saradc {
+- vref-supply = <&avcc_1v8_s0>;
+- status = "okay";
+-};
+-
+-&sdhci {
+- bus-width = <8>;
+- no-sdio;
+- no-sd;
+- non-removable;
+- mmc-hs400-1_8v;
+- mmc-hs400-enhanced-strobe;
+- status = "okay";
+-};
+-
+-&sdmmc {
+- max-frequency = <200000000>;
+- no-sdio;
+- no-mmc;
+- bus-width = <4>;
+- cap-mmc-highspeed;
+- cap-sd-highspeed;
+- cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+- disable-wp;
+- sd-uhs-sdr104;
+- vmmc-supply = <&vcc_3v3_s3>;
+- vqmmc-supply = <&vccio_sd_s0>;
+- status = "okay";
+-};
+-
+-&sfc {
+- pinctrl-names = "default";
+- pinctrl-0 = <&fspim2_pins>;
+- status = "okay";
+-
+- flash@0 {
+- compatible = "jedec,spi-nor";
+- reg = <0>;
+- spi-max-frequency = <104000000>;
+- spi-rx-bus-width = <4>;
+- spi-tx-bus-width = <1>;
+- vcc-supply = <&vcc_3v3_s3>;
+- };
+-};
+-
+-&spi2 {
+- status = "okay";
+- assigned-clocks = <&cru CLK_SPI2>;
+- assigned-clock-rates = <200000000>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+- num-cs = <1>;
+-
+- pmic@0 {
+- compatible = "rockchip,rk806";
+- spi-max-frequency = <1000000>;
+- reg = <0x0>;
+-
+- interrupt-parent = <&gpio0>;
+- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+-
+- pinctrl-names = "default";
+- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+-
+- system-power-controller;
+-
+- vcc1-supply = <&vcc5v0_sys>;
+- vcc2-supply = <&vcc5v0_sys>;
+- vcc3-supply = <&vcc5v0_sys>;
+- vcc4-supply = <&vcc5v0_sys>;
+- vcc5-supply = <&vcc5v0_sys>;
+- vcc6-supply = <&vcc5v0_sys>;
+- vcc7-supply = <&vcc5v0_sys>;
+- vcc8-supply = <&vcc5v0_sys>;
+- vcc9-supply = <&vcc5v0_sys>;
+- vcc10-supply = <&vcc5v0_sys>;
+- vcc11-supply = <&vcc_2v0_pldo_s3>;
+- vcc12-supply = <&vcc5v0_sys>;
+- vcc13-supply = <&vcc_1v1_nldo_s3>;
+- vcc14-supply = <&vcc_1v1_nldo_s3>;
+- vcca-supply = <&vcc5v0_sys>;
+-
+- gpio-controller;
+- #gpio-cells = <2>;
+-
+- rk806_dvs1_null: dvs1-null-pins {
+- pins = "gpio_pwrctrl1";
+- function = "pin_fun0";
+- };
+-
+- rk806_dvs2_null: dvs2-null-pins {
+- pins = "gpio_pwrctrl2";
+- function = "pin_fun0";
+- };
+-
+- rk806_dvs3_null: dvs3-null-pins {
+- pins = "gpio_pwrctrl3";
+- function = "pin_fun0";
+- };
+-
+- regulators {
+- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <950000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_gpu_s0";
+- regulator-enable-ramp-delay = <400>;
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <950000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_cpu_lit_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_log_s0: dcdc-reg3 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <675000>;
+- regulator-max-microvolt = <750000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_log_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <750000>;
+- };
+- };
+-
+- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <950000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_vdenc_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_ddr_s0: dcdc-reg5 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <675000>;
+- regulator-max-microvolt = <900000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_ddr_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <850000>;
+- };
+- };
+-
+- vdd2_ddr_s3: dcdc-reg6 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-name = "vdd2_ddr_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- };
+- };
+-
+- vcc_2v0_pldo_s3: dcdc-reg7 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <2000000>;
+- regulator-max-microvolt = <2000000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_2v0_pldo_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <2000000>;
+- };
+- };
+-
+- vcc_3v3_s3: dcdc-reg8 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-name = "vcc_3v3_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <3300000>;
+- };
+- };
+-
+- vddq_ddr_s0: dcdc-reg9 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-name = "vddq_ddr_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vcc_1v8_s3: dcdc-reg10 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "vcc_1v8_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <1800000>;
+- };
+- };
+-
+- avcc_1v8_s0: pldo-reg1 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "avcc_1v8_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vcc_1v8_s0: pldo-reg2 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "vcc_1v8_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <1800000>;
+- };
+- };
+-
+- avdd_1v2_s0: pldo-reg3 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1200000>;
+- regulator-max-microvolt = <1200000>;
+- regulator-name = "avdd_1v2_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vcc_3v3_s0: pldo-reg4 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vcc_3v3_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vccio_sd_s0: pldo-reg5 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vccio_sd_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- pldo6_s3: pldo-reg6 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "pldo6_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <1800000>;
+- };
+- };
+-
+- vdd_0v75_s3: nldo-reg1 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <750000>;
+- regulator-max-microvolt = <750000>;
+- regulator-name = "vdd_0v75_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <750000>;
+- };
+- };
+-
+- vdd_ddr_pll_s0: nldo-reg2 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <850000>;
+- regulator-max-microvolt = <850000>;
+- regulator-name = "vdd_ddr_pll_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <850000>;
+- };
+- };
+-
+- avdd_0v75_s0: nldo-reg3 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <750000>;
+- regulator-max-microvolt = <750000>;
+- regulator-name = "avdd_0v75_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_0v85_s0: nldo-reg4 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <850000>;
+- regulator-max-microvolt = <850000>;
+- regulator-name = "vdd_0v85_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_0v75_s0: nldo-reg5 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <750000>;
+- regulator-max-microvolt = <750000>;
+- regulator-name = "vdd_0v75_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+- };
+- };
+-};
+-
+-&tsadc {
+- status = "okay";
+-};
+-
+-&uart2 {
+- pinctrl-0 = <&uart2m0_xfer>;
+- status = "okay";
+-};
+-
+-&u2phy1 {
+- status = "okay";
+-};
+-
+-&u2phy1_otg {
+- status = "okay";
+-};
+-
+-&u2phy2 {
+- status = "okay";
+-};
+-
+-&u2phy2_host {
+- /* connected to USB hub, which is powered by vcc5v0_sys */
+- phy-supply = <&vcc5v0_sys>;
+- status = "okay";
+-};
+-
+-&u2phy3 {
+- status = "okay";
+-};
+-
+-&u2phy3_host {
+- phy-supply = <&vcc5v0_host>;
+- status = "okay";
+-};
+-
+-&usbdp_phy1 {
+- status = "okay";
+-};
+-
+-&usb_host0_ehci {
+- status = "okay";
+-};
+-
+-&usb_host0_ohci {
+- status = "okay";
+-};
+-
+-&usb_host1_ehci {
+- status = "okay";
+-};
+-
+-&usb_host1_ohci {
+- status = "okay";
+-};
+-
+-&usb_host1_xhci {
+- dr_mode = "host";
+- status = "okay";
+-};
+-
+-&usb_host2_xhci {
+- status = "okay";
+-};
+-
+-&vop {
+- status = "okay";
+-};
+-
+-&vop_mmu {
+- status = "okay";
+-};
+-
+-&vp0 {
+- vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+- remote-endpoint = <&hdmi0_in_vp0>;
+- };
+-};
+-
+-&vp1 {
+- vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
+- reg = <ROCKCHIP_VOP2_EP_HDMI1>;
+- remote-endpoint = <&hdmi1_in_vp1>;
+- };
+-};
--- /dev/null
+From 988035f152709549a095b12fcdcb3cf26cbad63f Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 20 May 2025 20:50:10 +0200
+Subject: arm64: dts: rockchip: move common ROCK 5B/+ nodes into own tree
+
+A few device tree nodes are shared between ROCK 5B and ROCK 5B+ that are
+not shared with ROCK 5T.
+
+Move them into their own device tree include.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-3-1f1971850a20@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
+@@ -18,23 +18,6 @@
+ stdout-path = "serial2:1500000n8";
+ };
+
+- analog-sound {
+- compatible = "audio-graph-card";
+- label = "rk3588-es8316";
+-
+- widgets = "Microphone", "Mic Jack",
+- "Headphone", "Headphones";
+-
+- routing = "MIC2", "Mic Jack",
+- "Headphones", "HPOL",
+- "Headphones", "HPOR";
+-
+- dais = <&i2s0_8ch_p0>;
+- hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&hp_detect>;
+- };
+-
+ hdmi0-con {
+ compatible = "hdmi-connector";
+ type = "a";
+@@ -57,19 +40,6 @@
+ };
+ };
+
+- leds {
+- compatible = "gpio-leds";
+- pinctrl-names = "default";
+- pinctrl-0 = <&led_rgb_b>;
+-
+- led_rgb_b {
+- function = LED_FUNCTION_STATUS;
+- color = <LED_COLOR_ID_BLUE>;
+- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+- };
+- };
+-
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 120 150 180 210 240 255>;
+@@ -78,13 +48,6 @@
+ #cooling-cells = <2>;
+ };
+
+- rfkill {
+- compatible = "rfkill-gpio";
+- label = "rfkill-m2-wlan";
+- radio-type = "wlan";
+- shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+- };
+-
+ rfkill-bt {
+ compatible = "rfkill-gpio";
+ label = "rfkill-m2-bt";
+@@ -95,9 +58,6 @@
+ vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&pcie2_0_vcc3v3_en>;
+ regulator-name = "vcc3v3_pcie2x1l0";
+ regulator-always-on;
+ regulator-boot-on;
+@@ -105,6 +65,7 @@
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <50000>;
+ vin-supply = <&vcc5v0_sys>;
++ status = "disabled";
+ };
+
+ vcc3v3_pcie2x1l2: regulator-vcc3v3-pcie2x1l2 {
+@@ -255,10 +216,8 @@
+ };
+
+ &hdmi_receiver {
+- hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>;
+ pinctrl-names = "default";
+- status = "okay";
+ };
+
+ &hdptxphy0 {
+@@ -434,39 +393,17 @@
+ };
+
+ &pinctrl {
+- hdmirx {
+- hdmirx_hpd: hdmirx-5v-detection {
+- rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+ hym8563 {
+ hym8563_int: hym8563-int {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+- leds {
+- led_rgb_b: led-rgb-b {
+- rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- sound {
+- hp_detect: hp-detect {
+- rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+ pcie2 {
+ pcie2_0_rst: pcie2-0-rst {
+ rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+- pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
+- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+ pcie2_2_rst: pcie2-2-rst {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+@@ -918,10 +855,6 @@
+ status = "okay";
+ };
+
+-&usb_host2_xhci {
+- status = "okay";
+-};
+-
+ &vop {
+ status = "okay";
+ };
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-plus.dts
+@@ -2,7 +2,7 @@
+
+ /dts-v1/;
+
+-#include "rk3588-rock-5b-5bp-5t.dtsi"
++#include "rk3588-rock-5b.dtsi"
+
+ / {
+ model = "Radxa ROCK 5B+";
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -2,7 +2,7 @@
+
+ /dts-v1/;
+
+-#include "rk3588-rock-5b-5bp-5t.dtsi"
++#include "rk3588-rock-5b.dtsi"
+
+ / {
+ model = "Radxa ROCK 5B";
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi
+@@ -0,0 +1,86 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk3588-rock-5b-5bp-5t.dtsi"
++
++/ {
++ analog-sound {
++ compatible = "audio-graph-card";
++ label = "rk3588-es8316";
++
++ widgets = "Microphone", "Mic Jack",
++ "Headphone", "Headphones";
++
++ routing = "MIC2", "Mic Jack",
++ "Headphones", "HPOL",
++ "Headphones", "HPOR";
++
++ dais = <&i2s0_8ch_p0>;
++ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hp_detect>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&led_rgb_b>;
++
++ led_rgb_b {
++ function = LED_FUNCTION_STATUS;
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ rfkill {
++ compatible = "rfkill-gpio";
++ label = "rfkill-m2-wlan";
++ radio-type = "wlan";
++ shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
++ };
++};
++
++&hdmi_receiver {
++ hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&pinctrl {
++ hdmirx {
++ hdmirx_hpd: hdmirx-5v-detection {
++ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ leds {
++ led_rgb_b: led-rgb-b {
++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie2 {
++ pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ sound {
++ hp_detect: hp-detect {
++ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&usb_host2_xhci {
++ status = "okay";
++};
++
++&vcc3v3_pcie2x1l0 {
++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
++ status = "okay";
++};
--- /dev/null
+From 0ea651de9b79a17cbe410a69399877805c136b76 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 20 May 2025 20:50:11 +0200
+Subject: arm64: dts: rockchip: add ROCK 5T device tree
+
+The RADXA ROCK 5T is a single board computer quite similar to the ROCK
+5B+, except it has one more PCIe-to-Ethernet controller (at the expense
+of a USB3 port) and a barrel jack for power input instead. Some pins are
+shuffled around as well.
+
+Add a device tree for it.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250520-add-rock5t-v2-4-1f1971850a20@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -143,6 +143,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-plus.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5t.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
+@@ -0,0 +1,105 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk3588-rock-5b-5bp-5t.dtsi"
++
++/ {
++ model = "Radxa ROCK 5T";
++ compatible = "radxa,rock-5t", "rockchip,rk3588";
++
++ analog-sound {
++ compatible = "audio-graph-card";
++ label = "rk3588-es8316";
++
++ widgets = "Microphone", "Mic Jack",
++ "Headphone", "Headphones";
++
++ routing = "MIC2", "Mic Jack",
++ "Headphones", "HPOL",
++ "Headphones", "HPOR";
++
++ dais = <&i2s0_8ch_p0>;
++ hp-det-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hp_detect>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&led_rgb_b>;
++
++ led_rgb_b {
++ function = LED_FUNCTION_STATUS;
++ color = <LED_COLOR_ID_BLUE>;
++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ rfkill {
++ compatible = "rfkill-gpio";
++ label = "rfkill-m2-wlan";
++ radio-type = "wlan";
++ shutdown-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
++ };
++
++ vcc3v3_pcie2x1l1: regulator-vcc3v3-pcie2x1l2 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_pcie2x1l1";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <5000>;
++ vin-supply = <&vcc_3v3_s3>;
++ };
++};
++
++&hdmi_receiver {
++ hpd-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&pcie2x1l1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie2_1_rst>;
++ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pcie2x1l1>;
++ status = "okay";
++};
++
++&pinctrl {
++ hdmirx {
++ hdmirx_hpd: hdmirx-5v-detection {
++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ leds {
++ led_rgb_b: led-rgb-b {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie2 {
++ pcie2_1_rst: pcie2-1-rst {
++ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ pcie2_0_vcc3v3_en: pcie2-0-vcc-en {
++ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ sound {
++ hp_detect: hp-detect {
++ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&vcc3v3_pcie2x1l0 {
++ gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
++ status = "okay";
++};
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Mon, 25 Aug 2025 09:27:08 +0200
+Subject: arm64: dts: rockchip: fix USB on RADXA ROCK 5T
+
+The RADXA ROCK 5T board uses the same GPIO pin for controlling the USB
+host port regulator. This control pin was mistakenly left out of the
+ROCK 5T device tree.
+
+Reported-by: FUKAUMI Naoki <naoki@radxa.com>
+Closes: https://libera.catirclogs.org/linux-rockchip/2025-08-25#38609886;
+Fixes: 0ea651de9b79 ("arm64: dts: rockchip: add ROCK 5T device tree")
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
+@@ -95,6 +95,12 @@
+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
++
++ usb {
++ vcc5v0_host_en: vcc5v0-host-en {
++ rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
+ };
+
+ &vcc3v3_pcie2x1l0 {
+@@ -103,3 +109,10 @@
+ pinctrl-0 = <&pcie2_0_vcc3v3_en>;
+ status = "okay";
+ };
++
++&vcc5v0_host {
++ enable-active-high;
++ gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vcc5v0_host_en>;
++};
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 26 Aug 2025 10:08:36 +0200
+Subject: arm64: dts: rockchip: fix second M.2 slot on ROCK 5T
+
+The Radxa ROCK 5T has two M.2 slots, much like the Radxa Rock 5B+. As it
+stands, the board won't be able to use PCIe3 if the second M.2 slot is
+in use.
+
+Fix this by adding the necessary node enablement and data-lanes property
+to the ROCK 5T device tree, mirroring what's in the ROCK 5B+ device
+tree.
+
+Reported-by: FUKAUMI Naoki <naoki@radxa.com>
+Closes: https://libera.catirclogs.org/linux-rockchip/2025-08-25#38610630;
+Fixes: 0ea651de9b79 ("arm64: dts: rockchip: add ROCK 5T device tree")
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
+@@ -68,6 +68,22 @@
+ status = "okay";
+ };
+
++&pcie30phy {
++ data-lanes = <1 1 2 2>;
++};
++
++&pcie3x2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie3x2_rst>;
++ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pcie30>;
++ status = "okay";
++};
++
++&pcie3x4 {
++ num-lanes = <2>;
++};
++
+ &pinctrl {
+ hdmirx {
+ hdmirx_hpd: hdmirx-5v-detection {
+@@ -90,6 +106,12 @@
+ };
+ };
+
++ pcie3 {
++ pcie3x2_rst: pcie3x2-rst {
++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ sound {
+ hp_detect: hp-detect {
+ rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
--- /dev/null
+From 3ca743f8a5b568dc5e5d5f1bab0298a4a43c2360 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Fri, 27 Sep 2024 14:42:22 +0200
+Subject: arm64: dts: rockchip: Switch to hp-det-gpios
+
+Replace the deprecated "hp-det-gpio" property by "hp-det-gpios" in Audio
+Graph Card and Realtek RT5651 Audio Codec device nodes.
+
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
+Link: https://lore.kernel.org/r/717e7c9527139c3a3e5246dd367a3ad98c5c81b6.1727438777.git.geert+renesas@glider.be
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -46,7 +46,7 @@
+ compatible = "audio-graph-card";
+ label = "rk3588-es8316";
+ dais = <&i2s0_8ch_p0>;
+- hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
++ hp-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hp_detect>;
+ routing = "MIC2", "Mic Jack",
--- /dev/null
+From e684f02492f99d6f6f037a35a613607339cf8e8f Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Fri, 6 Sep 2024 10:25:11 +0200
+Subject: arm64: dts: rockchip: fix the pcie refclock oscillator on Rock 5 ITX
+
+The Rock 5 ITX uses two PCIe controllers to drive both a M.2 slot and its
+SATA controller with 2 lanes each. The supply for the refclk oscillator is
+the same that supplies the M.2 slot, but the SATA controller port is
+supplied by a different rail.
+
+This leads to the effect that if the PCIe30x4 controller for the M.2
+probes first, everything works normally. But if the PCIe30x2 controller
+that is connected to the SATA controller probes first, it will hang on
+the first DBI read as nothing will have enabled the refclock before.
+
+Fix this by describing the clock generator with its supplies so that
+both controllers can reference it as needed.
+
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20240906082511.2963890-6-heiko@sntech.de
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -72,6 +72,15 @@
+ };
+ };
+
++ /* Unnamed gated oscillator: 100MHz,3.3V,3225 */
++ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
++ compatible = "gated-fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <100000000>;
++ clock-output-names = "pcie30_refclk";
++ vdd-supply = <&vcc3v3_pi6c_05>;
++ };
++
+ fan0: pwm-fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+@@ -146,13 +155,14 @@
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+- vcc3v3_mkey: regulator-vcc3v3-mkey {
++ /* The PCIE30x4_PWREN_H controls two regulators */
++ vcc3v3_mkey: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x4_pwren_h>;
+- regulator-name = "vcc3v3_mkey";
++ regulator-name = "vcc3v3_pi6c_05";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+@@ -513,6 +523,18 @@
+
+ /* ASMedia ASM1164 Sata controller */
+ &pcie3x2 {
++ /*
++ * The board has a "pcie_refclk" oscillator that needs enabling,
++ * so add it to the list of clocks.
++ */
++ clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
++ <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
++ <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>,
++ <&pcie30_port1_refclk>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk",
++ "aux", "pipe",
++ "ref";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x2_perstn_m1_l>;
+ reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+@@ -522,6 +544,18 @@
+
+ /* M.2 M.key */
+ &pcie3x4 {
++ /*
++ * The board has a "pcie_refclk" oscillator that needs enabling,
++ * so add it to the list of clocks.
++ */
++ clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
++ <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
++ <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
++ <&pcie30_port0_refclk>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk",
++ "aux", "pipe",
++ "ref";
+ num-lanes = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie30x4_perstn_m1_l>;
--- /dev/null
+From b36402e4a0772d1b3da06a4f5fbd1cfe4d6f1cc0 Mon Sep 17 00:00:00 2001
+From: Jianfeng Liu <liujianfeng1994@gmail.com>
+Date: Fri, 28 Feb 2025 22:33:08 +0800
+Subject: arm64: dts: rockchip: slow down emmc freq for rock 5 itx
+
+The current max-frequency 200000000 of emmc is not stable. When doing
+heavy write there will be I/O Error. After setting max-frequency to
+150000000 the emmc is stable under write.
+
+Also remove property mmc-hs200-1_8v because we are already running at
+HS400 mode.
+
+Tested with fio command:
+fio -filename=./test_randread -direct=1 -iodepth 1 -thread \
+-rw=randwrite -ioengine=psync -bs=16k -size=1G -numjobs=10 \
+-runtime=600 -group_reporting -name=mytest
+
+Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
+Link: https://lore.kernel.org/r/20250228143341.70244-1-liujianfeng1994@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -690,10 +690,9 @@
+
+ &sdhci {
+ bus-width = <8>;
+- max-frequency = <200000000>;
++ max-frequency = <150000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+- mmc-hs200-1_8v;
+ no-sdio;
+ no-sd;
+ non-removable;
--- /dev/null
+From 3eac9319af62dbc56d1f06fcb240e4a092fa5b2f Mon Sep 17 00:00:00 2001
+From: Jianfeng Liu <liujianfeng1994@gmail.com>
+Date: Tue, 25 Feb 2025 11:08:48 +0800
+Subject: arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX
+
+Enable the HDMI port next to ethernet port.
+
+Signed-off-by: Jianfeng Liu <liujianfeng1994@gmail.com>
+Link: https://lore.kernel.org/r/20250225030904.2813023-1-liujianfeng1994@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -11,6 +11,7 @@
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "dt-bindings/usb/pd.h"
+ #include "rk3588.dtsi"
+
+@@ -72,6 +73,17 @@
+ };
+ };
+
++ hdmi1-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi1_con_in: endpoint {
++ remote-endpoint = <&hdmi1_out_con>;
++ };
++ };
++ };
++
+ /* Unnamed gated oscillator: 100MHz,3.3V,3225 */
+ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
+ compatible = "gated-fixed-clock";
+@@ -261,6 +273,28 @@
+ status = "okay";
+ };
+
++&hdmi1 {
++ pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd
++ &hdmim1_tx1_scl &hdmim1_tx1_sda>;
++ status = "okay";
++};
++
++&hdmi1_in {
++ hdmi1_in_vp1: endpoint {
++ remote-endpoint = <&vp1_out_hdmi1>;
++ };
++};
++
++&hdmi1_out {
++ hdmi1_out_con: endpoint {
++ remote-endpoint = <&hdmi1_con_in>;
++ };
++};
++
++&hdptxphy1 {
++ status = "okay";
++};
++
+ &i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
+@@ -1208,3 +1242,18 @@
+ rockchip,dp-lane-mux = <2 3>;
+ status = "okay";
+ };
++
++&vop {
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp1 {
++ vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI1>;
++ remote-endpoint = <&hdmi1_in_vp1>;
++ };
++};
--- /dev/null
+From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 20 Feb 2025 19:58:11 +0100
+Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
+ RK3588
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Enabling the GPU power domain requires that the GPU regulator is
+enabled. The regulator is enabled at boot time, but gets disabled
+automatically when there are no users.
+
+This means the system might run into a failure state hanging the
+whole system for the following use cases:
+
+ * if the GPU driver is being probed late (e.g. build as a
+ module and firmware is not in initramfs), the regulator
+ might already have been disabled. In that case the power
+ domain is enabled before the regulator.
+ * unbinding the GPU driver will disable the PM domain and
+ the regulator. When the driver is bound again, the PM
+ domain will be enabled before the regulator and error
+ appears.
+
+Avoid this by adding an explicit regulator dependency to the
+power domain.
+
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Reported-by: Adrián MartÃnez Larumbe <adrian.larumbe@collabora.com>
+Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -598,6 +598,10 @@
+ status = "okay";
+ };
+
++&pd_gpu {
++ domain-supply = <&vdd_gpu_s0>;
++};
++
+ &pinctrl {
+ hym8563 {
+ rtc_int: rtc-int {
--- /dev/null
+From 3ddf5cdb77e6efd6fe9b70f36dec935e324a3cd2 Mon Sep 17 00:00:00 2001
+From: FUKAUMI Naoki <naoki@radxa.com>
+Date: Mon, 21 Oct 2024 09:05:47 +0000
+Subject: arm64: dts: rockchip: add Radxa ROCK 5C
+
+Radxa ROCK 5C is a 8K computer for everything[1] using the Rockchip
+RK3588S2 chip:
+
+- Rockchip RK3588S2
+- Quad A76 and Quad A55 CPU
+- 6 TOPS NPU
+- up to 32GB LPDDR4x RAM
+- eMMC / SPI flash connector
+- Micro SD Card slot
+- Gigabit ethernet port (supports PoE with add-on PoE HAT)
+- WiFi6 / BT5.4
+- 1x USB 3.0 Type-A HOST port
+- 1x USB 3.0 Type-A OTG port
+- 2x USB 2.0 Type-A HOST port
+- 1x USB Type-C 5V power port
+
+[1] https://radxa.com/products/rock5/5c
+
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+Link: https://lore.kernel.org/r/20241021090548.1052-2-naoki@radxa.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -156,3 +156,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-n
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-odroid-m2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5c.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+@@ -0,0 +1,920 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3588s.dtsi"
++
++/ {
++ model = "Radxa ROCK 5C";
++ compatible = "radxa,rock-5c", "rockchip,rk3588s";
++
++ aliases {
++ ethernet0 = &gmac1;
++ mmc0 = &sdhci;
++ mmc1 = &sdmmc;
++ };
++
++ chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ analog-sound {
++ compatible = "audio-graph-card";
++ label = "rk3588-es8316";
++ dais = <&i2s0_8ch_p0>;
++ routing = "MIC2", "Mic Jack",
++ "Headphones", "HPOL",
++ "Headphones", "HPOR";
++ widgets = "Microphone", "Mic Jack",
++ "Headphone", "Headphones";
++ };
++
++ hdmi0-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi0_con_in: endpoint {
++ remote-endpoint = <&hdmi0_out_con>;
++ };
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&led_pins>;
++
++ led-0 {
++ color = <LED_COLOR_ID_GREEN>;
++ default-state = "on";
++ function = LED_FUNCTION_POWER;
++ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
++ };
++
++ led-1 {
++ color = <LED_COLOR_ID_BLUE>;
++ default-state = "on";
++ function = LED_FUNCTION_HEARTBEAT;
++ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ fan {
++ compatible = "pwm-fan";
++ #cooling-cells = <2>;
++ cooling-levels = <0 64 128 192 255>;
++ fan-supply = <&vcc_5v0>;
++ pwms = <&pwm3 0 10000 0>;
++ };
++
++ pcie2x1l2_3v3: regulator-pcie2x1l2-3v3 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pow_en>;
++ regulator-name = "pcie2x1l2_3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_sysin>;
++ };
++
++ vcc5v_dcin: regulator-vcc5v-dcin {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v_dcin";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vcc5v0_usb_host: regulator-vcc5v0-usb-host {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_host_pwren_h>;
++ regulator-name = "vcc5v0_usb_host";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc_sysin>;
++ };
++
++ vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_otg_pwren_h>;
++ regulator-name = "vcc5v0_usb_otg0";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc_sysin>;
++ };
++
++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_1v1_nldo_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
++ vin-supply = <&vcc_sysin>;
++ };
++
++ vcc_3v3_pmu: regulator-vcc-3v3-pmu {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_3v3_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_3v3_s3>;
++ };
++
++ vcc_3v3_s0: regulator-vcc-3v3-s0 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_3v3_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_1v8_s0>;
++ };
++
++ vcc_5v0: regulator-vcc-5v0 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vcc_5v0_pwren_h>;
++ regulator-name = "vcc_5v0";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc_sysin>;
++ };
++
++ vcc_sysin: regulator-vcc-sysin {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_sysin";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v_dcin>;
++ };
++
++ vcca: regulator-vcca {
++ compatible = "regulator-fixed";
++ regulator-name = "vcca";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <4000000>;
++ regulator-max-microvolt = <4000000>;
++ vin-supply = <&vcc_sysin>;
++ };
++
++ vdd_3v3: regulator-vdd-3v3 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_wifi_pwr>;
++ regulator-name = "vdd_3v3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_3v3_s3>;
++ };
++};
++
++&combphy0_ps {
++ status = "okay";
++};
++
++&combphy2_psu {
++ status = "okay";
++};
++
++&cpu_b0 {
++ cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b1 {
++ cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b2 {
++ cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_b3 {
++ cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_l0 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l1 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l2 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l3 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&gmac1 {
++ phy-handle = <&rgmii_phy1>;
++ phy-mode = "rgmii-id";
++ phy-supply = <&vcc_3v3_s0>;
++ pinctrl-0 = <&gmac1_miim
++ &gmac1_tx_bus2
++ &gmac1_rx_bus2
++ &gmac1_rgmii_clk
++ &gmac1_rgmii_bus
++ &gmac1_clkinout>;
++ pinctrl-names = "default";
++ status = "okay";
++};
++
++&gpu {
++ mali-supply = <&vdd_gpu_s0>;
++ status = "okay";
++};
++
++&hdmi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&hdmim0_tx0_cec
++ &hdmim1_tx0_hpd
++ &hdmim0_tx0_scl
++ &hdmim0_tx0_sda>;
++ status = "okay";
++};
++
++&hdmi0_in {
++ hdmi0_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi0>;
++ };
++};
++
++&hdmi0_out {
++ hdmi0_out_con: endpoint {
++ remote-endpoint = <&hdmi0_con_in>;
++ };
++};
++
++&hdptxphy_hdmi0 {
++ status = "okay";
++};
++
++&i2c0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0m2_xfer>;
++ status = "okay";
++
++ vdd_cpu_big0_s0: regulator@42 {
++ compatible = "rockchip,rk8602";
++ reg = <0x42>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu_big0_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1050000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc_sysin>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_big1_s0: regulator@43 {
++ compatible = "rockchip,rk8603", "rockchip,rk8602";
++ reg = <0x43>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu_big1_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1050000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc_sysin>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ eeprom@50 {
++ compatible = "belling,bl24c16a", "atmel,24c16";
++ reg = <0x50>;
++ pagesize = <16>;
++ vcc-supply = <&vcc_3v3_pmu>;
++ };
++};
++
++&i2c2 {
++ status = "okay";
++
++ vdd_npu_s0: regulator@42 {
++ compatible = "rockchip,rk8602";
++ reg = <0x42>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_npu_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc_sysin>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++};
++
++&i2c5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c5m2_xfer>;
++ status = "okay";
++
++ rtc@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ #clock-cells = <0>;
++ clock-output-names = "rtcic_32kout";
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtc_int_l>;
++ };
++};
++
++&i2c7 {
++ status = "okay";
++
++ audio-codec@11 {
++ compatible = "everest,es8316";
++ reg = <0x11>;
++ assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
++ assigned-clock-rates = <12288000>;
++ clocks = <&cru I2S0_8CH_MCLKOUT>;
++ clock-names = "mclk";
++ #sound-dai-cells = <0>;
++
++ port {
++ es8316_p0_0: endpoint {
++ remote-endpoint = <&i2s0_8ch_p0_0>;
++ };
++ };
++ };
++};
++
++&i2s0_8ch {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2s0_lrck
++ &i2s0_mclk
++ &i2s0_sclk
++ &i2s0_sdi0
++ &i2s0_sdo0>;
++ status = "okay";
++
++ i2s0_8ch_p0: port {
++ i2s0_8ch_p0_0: endpoint {
++ dai-format = "i2s";
++ mclk-fs = <256>;
++ remote-endpoint = <&es8316_p0_0>;
++ };
++ };
++};
++
++&mdio1 {
++ rgmii_phy1: ethernet-phy@1 {
++ compatible = "ethernet-phy-id001c.c916";
++ reg = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac1_rstn>;
++ reset-assert-us = <20000>;
++ reset-deassert-us = <100000>;
++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++ };
++};
++
++&pcie2x1l2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie20x1_2_perstn_m0>;
++ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&pcie2x1l2_3v3>;
++ status = "okay";
++};
++
++&pinctrl {
++ leds {
++ led_pins: led-pins {
++ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
++ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ mdio {
++ gmac1_rstn: gmac1-rstn {
++ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie {
++ pcie20x1_2_perstn_m0: pcie20x1-2-perstn-m0 {
++ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ pow_en: pow-en {
++ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ rtc {
++ rtc_int_l: rtc-int-l {
++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ usb {
++ usb_host_pwren_h: usb-host-pwren-h {
++ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ usb_otg_pwren_h: usb-otg-pwren-h {
++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ usb_wifi_pwr: usb-wifi-pwr {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ vcc_5v0_pwren_h: vcc-5v0-pwren-h {
++ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm3m1_pins>;
++ status = "okay";
++};
++
++&saradc {
++ vref-supply = <&vcca_1v8_s0>;
++ status = "okay";
++};
++
++&sdhci {
++ bus-width = <8>;
++ mmc-hs400-1_8v;
++ mmc-hs400-enhanced-strobe;
++ no-sdio;
++ no-sd;
++ non-removable;
++ status = "okay";
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ no-sdio;
++ no-mmc;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3_s3>;
++ vqmmc-supply = <&vccio_sd_s0>;
++ status = "okay";
++};
++
++&sfc {
++ pinctrl-names = "default";
++ pinctrl-0 = <&fspim0_pins>;
++
++ flash@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <104000000>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <1>;
++ };
++};
++
++&spi2 {
++ status = "okay";
++ assigned-clocks = <&cru CLK_SPI2>;
++ assigned-clock-rates = <200000000>;
++ num-cs = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
++
++ pmic@0 {
++ compatible = "rockchip,rk806";
++ reg = <0>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
++ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
++ spi-max-frequency = <1000000>;
++ system-power-controller;
++
++ vcc1-supply = <&vcc_sysin>;
++ vcc2-supply = <&vcc_sysin>;
++ vcc3-supply = <&vcc_sysin>;
++ vcc4-supply = <&vcc_sysin>;
++ vcc5-supply = <&vcc_sysin>;
++ vcc6-supply = <&vcc_sysin>;
++ vcc7-supply = <&vcc_sysin>;
++ vcc8-supply = <&vcc_sysin>;
++ vcc9-supply = <&vcc_sysin>;
++ vcc10-supply = <&vcc_sysin>;
++ vcc11-supply = <&vcc_2v0_pldo_s3>;
++ vcc12-supply = <&vcc_sysin>;
++ vcc13-supply = <&vcc_1v1_nldo_s3>;
++ vcc14-supply = <&vcc_1v1_nldo_s3>;
++ vcca-supply = <&vcca>;
++
++ rk806_dvs1_null: dvs1-null-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs2_null: dvs2-null-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs3_null: dvs3-null-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun0";
++ };
++
++ regulators {
++ vdd_gpu_s0: dcdc-reg1 {
++ regulator-name = "vdd_gpu_s0";
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++ regulator-enable-ramp-delay = <400>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_lit_s0: dcdc-reg2 {
++ regulator-name = "vdd_cpu_lit_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_logic_s0: dcdc-reg3 {
++ regulator-name = "vdd_logic_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <675000>;
++ regulator-max-microvolt = <750000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdd_vdenc_s0: dcdc-reg4 {
++ regulator-name = "vdd_vdenc_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_ddr_s0: dcdc-reg5 {
++ regulator-name = "vdd_ddr_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <675000>;
++ regulator-max-microvolt = <900000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ vdd2_ddr_s3: dcdc-reg6 {
++ regulator-name = "vdd2_ddr_s3";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_2v0_pldo_s3: dcdc-reg7 {
++ regulator-name = "vdd_2v0_pldo_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <2000000>;
++ regulator-max-microvolt = <2000000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <2000000>;
++ };
++ };
++
++ vcc_3v3_s3: dcdc-reg8 {
++ regulator-name = "vcc_3v3_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vddq_ddr_s0: dcdc-reg9 {
++ regulator-name = "vddq_ddr_s0";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc1v8_pmu_ddr_s3: dcdc-reg10 {
++ regulator-name = "vcc1v8_pmu_ddr_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcc_1v8_s0: pldo-reg1 {
++ regulator-name = "vcc_1v8_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcca_1v8_s0: pldo-reg2 {
++ regulator-name = "vcca_1v8_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdda_1v2_s0: pldo-reg3 {
++ regulator-name = "vdda_1v2_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca_3v3_s0: pldo-reg4 {
++ regulator-name = "vcca_3v3_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vccio_sd_s0: pldo-reg5 {
++ regulator-name = "vccio_sd_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ pldo6_s3: pldo-reg6 {
++ regulator-name = "pldo6_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_0v75_s3: nldo-reg1 {
++ regulator-name = "vdd_0v75_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdda_ddr_pll_s0: nldo-reg2 {
++ regulator-name = "vdda_ddr_pll_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ vdda_0v75_s0: nldo-reg3 {
++ regulator-name = "vdda_0v75_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_0v85_s0: nldo-reg4 {
++ regulator-name = "vdda_0v85_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_0v75_s0: nldo-reg5 {
++ regulator-name = "vdd_0v75_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++&tsadc {
++ status = "okay";
++};
++
++&u2phy0 {
++ status = "okay";
++};
++
++&u2phy0_otg {
++ phy-supply = <&vcc5v0_usb_otg0>;
++ status = "okay";
++};
++
++&u2phy2 {
++ status = "okay";
++};
++
++&u2phy2_host {
++ /* connected to USB hub, which is powered by vcc_5v0 */
++ phy-supply = <&vcc_5v0>;
++ status = "okay";
++};
++
++&u2phy3 {
++ status = "okay";
++};
++
++&u2phy3_host {
++ phy-supply = <&vcc5v0_usb_host>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-0 = <&uart2m0_xfer>;
++ status = "okay";
++};
++
++&usbdp_phy0 {
++ status = "okay";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_xhci {
++ dr_mode = "host";
++ status = "okay";
++};
++
++&usb_host1_ehci {
++ status = "okay";
++};
++
++&usb_host1_ohci {
++ status = "okay";
++};
++
++&usb_host2_xhci {
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vop {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi0_in_vp0>;
++ };
++};
--- /dev/null
+From 6ed35e6ff556626734c400fff5a636b38b91fe19 Mon Sep 17 00:00:00 2001
+From: Alexey Charkov <alchark@gmail.com>
+Date: Mon, 20 Jan 2025 23:22:46 +0400
+Subject: arm64: dts: rockchip: Add finer-grained PWM states for the fan on
+ Rock 5C
+
+Radxa Heatsink 6540B, which is the official cooling accessory for the
+Rock 5C board, includes a small 5V fan, which in my testing spins up
+reliably at a PWM setting of 24 (out of 255). It is also quite loud
+at the current minimum setting of 64, and noticeably less so at 24.
+
+Introduce two intermediate PWM states at the lower end of the fan's
+operating range to enable better balance between noise and cooling.
+
+Note further that, in my testing, having the fan run at 44 is enough
+to keep the system from thermal throttling with sustained 100% load
+on its 8 CPU cores (in 22C ambient temperature and no case)
+
+Signed-off-by: Alexey Charkov <alchark@gmail.com>
+Acked-by: Dragan Simic <dsimic@manjaro.org>
+Link: https://lore.kernel.org/r/20250120-rock-5c-fan-v1-1-5fb8446c981b@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+@@ -71,7 +71,7 @@
+ fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+- cooling-levels = <0 64 128 192 255>;
++ cooling-levels = <0 24 44 64 128 192 255>;
+ fan-supply = <&vcc_5v0>;
+ pwms = <&pwm3 0 10000 0>;
+ };
--- /dev/null
+From cd5681e63fb9887bd05d4ef59151d6a6b39c9d33 Mon Sep 17 00:00:00 2001
+From: Alexey Charkov <alchark@gmail.com>
+Date: Mon, 20 Jan 2025 23:22:47 +0400
+Subject: arm64: dts: rockchip: Enable automatic fan control on Radxa Rock 5C
+
+Add the necessary cooling map to enable the kernel's thermal subsystem
+to manage the fan speed automatically depending on the overall SoC
+package temperature on Radxa Rock 5C
+
+Signed-off-by: Alexey Charkov <alchark@gmail.com>
+Reviewed-by: Dragan Simic <dsimic@manjaro.org>
+Link: https://lore.kernel.org/r/20250120-rock-5c-fan-v1-2-5fb8446c981b@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+@@ -68,7 +68,7 @@
+ };
+ };
+
+- fan {
++ fan: fan {
+ compatible = "pwm-fan";
+ #cooling-cells = <2>;
+ cooling-levels = <0 24 44 64 128 192 255>;
+@@ -417,6 +417,36 @@
+ };
+ };
+
++&package_thermal {
++ polling-delay = <1000>;
++
++ trips {
++ package_fan0: package-fan0 {
++ temperature = <55000>;
++ hysteresis = <2000>;
++ type = "active";
++ };
++
++ package_fan1: package-fan1 {
++ temperature = <65000>;
++ hysteresis = <2000>;
++ type = "active";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&package_fan0>;
++ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
++ };
++
++ map1 {
++ trip = <&package_fan1>;
++ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
++ };
++ };
++};
++
+ &pcie2x1l2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie20x1_2_perstn_m0>;
--- /dev/null
+From 2efdb041019fd6c58abefba3eb6fdc4d659e576c Mon Sep 17 00:00:00 2001
+From: Damon Ding <damon.ding@rock-chips.com>
+Date: Thu, 6 Feb 2025 11:03:30 +0800
+Subject: arm64: dts: rockchip: Fix label name of hdptxphy for RK3588
+
+The hdptxphy is a combo transmit-PHY for HDMI2.1 TMDS Link, FRL Link, DP
+and eDP Link. Therefore, it is better to name it hdptxphy0 other than
+hdptxphy_hdmi0, which will be referenced by both hdmi0 and edp0 nodes.
+
+Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
+Link: https://lore.kernel.org/r/20250206030330.680424-3-damon.ding@rock-chips.com
+[added armsom-sige7, where hdmi-support was added recently and also
+ the hdptxphy0-as-dclk source I just added]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+@@ -278,7 +278,7 @@
+ };
+ };
+
+-&hdptxphy_hdmi0 {
++&hdptxphy0 {
+ status = "okay";
+ };
+
--- /dev/null
+From 52cababc9c1914ebf50929bfb9a67c8f74cd60ab Mon Sep 17 00:00:00 2001
+From: Alexey Charkov <alchark@gmail.com>
+Date: Tue, 4 Feb 2025 13:02:28 +0400
+Subject: arm64: dts: rockchip: switch Rock 5C to PMIC-based TSHUT reset
+
+Radxa Rock 5C supports both CRU-based (default) and PMIC-based reset
+upon thermal runaway conditions. The former resets the SoC by internally
+poking the CRU from TSADC, while the latter power-cycles the whole board
+by pulling the PMIC reset line low in case of uncontrolled overheating.
+
+Switch to a PMIC-based reset, as the more 'thorough' of the two.
+
+Tested by temporarily setting rockchip,hw-tshut-temp to 65C to simulate
+overheating - this causes the board to reset when any of the on-chip
+temperature sensors surpasses the tshut temperature.
+
+Requires Alexander's patch [1] fixing TSADC pinctrl assignment
+
+[1] https://lore.kernel.org/r/20250130053849.4902-1-eagle.alexander923@gmail.com
+
+Signed-off-by: Alexey Charkov <alchark@gmail.com>
+Reviewed-by: Dragan Simic <dsimic@manjaro.org>
+Link: https://lore.kernel.org/r/20250204-rock-5c-tshut-v1-1-33301e4eef64@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+@@ -873,6 +873,8 @@
+ };
+
+ &tsadc {
++ rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
++ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+ status = "okay";
+ };
+
--- /dev/null
+From f94500eb7328b35f3d0927635b1aba26c85ea4b0 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 20 Feb 2025 19:58:11 +0100
+Subject: arm64: dts: rockchip: Add GPU power domain regulator dependency for
+ RK3588
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Enabling the GPU power domain requires that the GPU regulator is
+enabled. The regulator is enabled at boot time, but gets disabled
+automatically when there are no users.
+
+This means the system might run into a failure state hanging the
+whole system for the following use cases:
+
+ * if the GPU driver is being probed late (e.g. build as a
+ module and firmware is not in initramfs), the regulator
+ might already have been disabled. In that case the power
+ domain is enabled before the regulator.
+ * unbinding the GPU driver will disable the PM domain and
+ the regulator. When the driver is bound again, the PM
+ domain will be enabled before the regulator and error
+ appears.
+
+Avoid this by adding an explicit regulator dependency to the
+power domain.
+
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Reported-by: Adrián MartÃnez Larumbe <adrian.larumbe@collabora.com>
+Tested-by: Adrian Larumbe <adrian.larumbe@collabora.com> # On Rock 5B
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20250220-rk3588-gpu-pwr-domain-regulator-v6-8-a4f9c24e5b81@kernel.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+@@ -455,6 +455,10 @@
+ status = "okay";
+ };
+
++&pd_gpu {
++ domain-supply = <&vdd_gpu_s0>;
++};
++
+ &pinctrl {
+ leds {
+ led_pins: led-pins {
--- /dev/null
+From 9be4171219b659a8f0fa0a7913af2c6ab20c714e Mon Sep 17 00:00:00 2001
+From: FUKAUMI Naoki <naoki@radxa.com>
+Date: Thu, 26 Dec 2024 02:46:30 +0000
+Subject: arm64: dts: rockchip: Add Radxa E52C
+
+Radxa E52C[1] is a compact network computer based on the Rockchip
+RK3582 SoC:
+
+- Dual Cortex-A76 and quad Cortex-A55 CPU
+- 5TOPS NPU
+- 2GB/4GB/8GB LPDDR4 RAM
+- 16GB/32GB/64GB on-board eMMC
+- microSD card slot
+- USB 3.0 Type-A HOST port
+- USB Type-C debug port
+- USB Type-C power port (5V only)
+- 2x 2.5GbE ports
+
+[1] https://radxa.com/products/network-computer/e52c
+
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+Link: https://lore.kernel.org/r/20241226024630.13702-3-naoki@radxa.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -124,6 +124,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-genbook.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts
+@@ -0,0 +1,743 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/pwm/pwm.h>
++#include "rk3588s.dtsi"
++
++/ {
++ model = "Radxa E52C";
++ compatible = "radxa,e52c", "rockchip,rk3582", "rockchip,rk3588s";
++
++ aliases {
++ mmc0 = &sdhci;
++ mmc1 = &sdmmc;
++ };
++
++ chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ keys-0 {
++ compatible = "adc-keys";
++ io-channels = <&saradc 0>;
++ io-channel-names = "buttons";
++ keyup-threshold-microvolt = <18000>;
++ poll-interval = <100>;
++
++ button-0 {
++ label = "Maskrom";
++ linux,code = <KEY_VENDOR>;
++ press-threshold-microvolt = <0>;
++ };
++ };
++
++ keys-1 {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&btn_0>;
++
++ button-1 {
++ label = "User";
++ gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
++ linux,code = <BTN_0>;
++ wakeup-source;
++ };
++ };
++
++ leds-0 {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&led_0>;
++
++ led-0 {
++ color = <LED_COLOR_ID_GREEN>;
++ default-state = "on";
++ function = LED_FUNCTION_STATUS;
++ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ leds-1 {
++ compatible = "pwm-leds";
++
++ led-1 {
++ color = <LED_COLOR_ID_GREEN>;
++ default-state = "on";
++ function = LED_FUNCTION_LAN;
++ linux,default-trigger = "netdev";
++ pwms = <&pwm14 0 1000000 PWM_POLARITY_INVERTED>;
++ max-brightness = <255>;
++ };
++
++ led-2 {
++ color = <LED_COLOR_ID_GREEN>;
++ default-state = "on";
++ function = LED_FUNCTION_WAN;
++ linux,default-trigger = "netdev";
++ pwms = <&pwm11 0 1000000 PWM_POLARITY_INVERTED>;
++ max-brightness = <255>;
++ };
++ };
++
++ vcc_1v1_nldo_s3: regulator-1v1 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_1v1_nldo_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
++ vin-supply = <&vcc_sysin>;
++ };
++
++ vcc_3v3_pmu: regulator-3v3-0 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_3v3_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_3v3_s3>;
++ };
++
++ vcc_3v3_s0: regulator-3v3-1 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_3v3_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_3v3_s3>;
++ };
++
++ vcca: regulator-4v0 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcca";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <4000000>;
++ regulator-max-microvolt = <4000000>;
++ vin-supply = <&vcc_sysin>;
++ };
++
++ vcc5v0_usb_otg0: regulator-5v0-0 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_otg_pwren_h>;
++ regulator-name = "vcc5v0_usb_otg0";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc_sysin>;
++ };
++
++ vcc_5v0: regulator-5v0-1 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vcc_5v0_pwren_h>;
++ regulator-name = "vcc_5v0";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc_sysin>;
++ };
++
++ vcc_sysin: regulator-5v0-2 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_sysin";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++};
++
++&combphy0_ps {
++ status = "okay";
++};
++
++&combphy2_psu {
++ status = "okay";
++};
++
++/*
++ * In the Rockchip RK3582 SoC, some CPU cores end up disabled
++ * and unused because they're marked in the efuses as defective.
++ * The disabling in the DT is performed by the boot loader.
++ */
++&cpu_b0 {
++ cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b1 {
++ cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b2 {
++ cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_b3 {
++ cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_l0 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l1 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l2 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l3 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&i2c0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0m2_xfer>;
++ status = "okay";
++
++ vdd_cpu_big0_s0: regulator@42 {
++ compatible = "rockchip,rk8602";
++ reg = <0x42>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu_big0_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1050000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc_sysin>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_big1_s0: regulator@43 {
++ compatible = "rockchip,rk8603", "rockchip,rk8602";
++ reg = <0x43>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu_big1_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1050000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc_sysin>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ eeprom@50 {
++ compatible = "belling,bl24c16a", "atmel,24c16";
++ reg = <0x50>;
++ pagesize = <16>;
++ vcc-supply = <&vcc_3v3_pmu>;
++ };
++};
++
++&i2c2 {
++ status = "okay";
++
++ vdd_npu_s0: regulator@42 {
++ compatible = "rockchip,rk8602";
++ reg = <0x42>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_npu_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc_sysin>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++};
++
++&i2c5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c5m2_xfer>;
++ status = "okay";
++
++ rtc@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ #clock-cells = <0>;
++ clock-output-names = "rtcic_32kout";
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtc_int_l>;
++ wakeup-source;
++ };
++};
++
++&pcie2x1l1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie20x1_1_perstn_m1>;
++ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3_s3>;
++ status = "okay";
++};
++
++&pcie2x1l2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie20x1_2_perstn_m0>;
++ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3_s3>;
++ status = "okay";
++};
++
++&pinctrl {
++ keys {
++ btn_0: button-0 {
++ rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ leds {
++ led_0: led-0 {
++ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie {
++ pcie20x1_1_perstn_m1: pcie-1 {
++ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ pcie20x1_2_perstn_m0: pcie-2 {
++ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ regulators {
++ vcc_5v0_pwren_h: regulator-5v0-1 {
++ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ rtc {
++ rtc_int_l: rtc-0 {
++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ usb {
++ usb_otg_pwren_h: regulator-5v0-0 {
++ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&pwm11 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm11m1_pins>;
++ status = "okay";
++};
++
++&pwm14 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm14m1_pins>;
++ status = "okay";
++};
++
++&saradc {
++ vref-supply = <&vcca_1v8_s0>;
++ status = "okay";
++};
++
++&sdhci {
++ bus-width = <8>;
++ cap-mmc-highspeed;
++ mmc-hs400-1_8v;
++ mmc-hs400-enhanced-strobe;
++ no-sd;
++ no-sdio;
++ non-removable;
++ vmmc-supply = <&vcc_3v3_s0>;
++ vqmmc-supply = <&vcc_1v8_s3>;
++ status = "okay";
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
++ disable-wp;
++ no-sdio;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3_s3>;
++ vqmmc-supply = <&vccio_sd_s0>;
++ status = "okay";
++};
++
++&spi2 {
++ status = "okay";
++ assigned-clocks = <&cru CLK_SPI2>;
++ assigned-clock-rates = <200000000>;
++ num-cs = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
++
++ pmic@0 {
++ compatible = "rockchip,rk806";
++ reg = <0>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
++ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
++ spi-max-frequency = <1000000>;
++ system-power-controller;
++
++ vcc1-supply = <&vcc_sysin>;
++ vcc2-supply = <&vcc_sysin>;
++ vcc3-supply = <&vcc_sysin>;
++ vcc4-supply = <&vcc_sysin>;
++ vcc5-supply = <&vcc_sysin>;
++ vcc6-supply = <&vcc_sysin>;
++ vcc7-supply = <&vcc_sysin>;
++ vcc8-supply = <&vcc_sysin>;
++ vcc9-supply = <&vcc_sysin>;
++ vcc10-supply = <&vcc_sysin>;
++ vcc11-supply = <&vcc_2v0_pldo_s3>;
++ vcc12-supply = <&vcc_sysin>;
++ vcc13-supply = <&vcc_1v1_nldo_s3>;
++ vcc14-supply = <&vcc_1v1_nldo_s3>;
++ vcca-supply = <&vcca>;
++
++ rk806_dvs1_null: dvs1-null-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs2_null: dvs2-null-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs3_null: dvs3-null-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun0";
++ };
++
++ regulators {
++ vdd_gpu_s0: dcdc-reg1 {
++ regulator-name = "vdd_gpu_s0";
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++ regulator-enable-ramp-delay = <400>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_lit_s0: dcdc-reg2 {
++ regulator-name = "vdd_cpu_lit_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_logic_s0: dcdc-reg3 {
++ regulator-name = "vdd_logic_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <675000>;
++ regulator-max-microvolt = <750000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdd_vdenc_s0: dcdc-reg4 {
++ regulator-name = "vdd_vdenc_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_ddr_s0: dcdc-reg5 {
++ regulator-name = "vdd_ddr_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <675000>;
++ regulator-max-microvolt = <900000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ vdd2_ddr_s3: dcdc-reg6 {
++ regulator-name = "vdd2_ddr_s3";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_2v0_pldo_s3: dcdc-reg7 {
++ regulator-name = "vcc_2v0_pldo_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <2000000>;
++ regulator-max-microvolt = <2000000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <2000000>;
++ };
++ };
++
++ vcc_3v3_s3: dcdc-reg8 {
++ regulator-name = "vcc_3v3_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vddq_ddr_s0: dcdc-reg9 {
++ regulator-name = "vddq_ddr_s0";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8_s3: dcdc-reg10 {
++ regulator-name = "vcc_1v8_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcc_1v8_s0: pldo-reg1 {
++ regulator-name = "vcc_1v8_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcca_1v8_s0: pldo-reg2 {
++ regulator-name = "vcca_1v8_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdda_1v2_s0: pldo-reg3 {
++ regulator-name = "vdda_1v2_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca_3v3_s0: pldo-reg4 {
++ regulator-name = "vcca_3v3_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vccio_sd_s0: pldo-reg5 {
++ regulator-name = "vccio_sd_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ pldo6_s3: pldo-reg6 {
++ regulator-name = "pldo6_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_0v75_s3: nldo-reg1 {
++ regulator-name = "vdd_0v75_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdda_ddr_pll_s0: nldo-reg2 {
++ regulator-name = "vdda_ddr_pll_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ vdda_0v75_s0: nldo-reg3 {
++ regulator-name = "vdda_0v75_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdda_0v85_s0: nldo-reg4 {
++ regulator-name = "vdda_0v85_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_0v75_s0: nldo-reg5 {
++ regulator-name = "vdd_0v75_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++&tsadc {
++ status = "okay";
++};
++
++&u2phy0 {
++ status = "okay";
++};
++
++&u2phy0_otg {
++ phy-supply = <&vcc5v0_usb_otg0>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-0 = <&uart2m0_xfer>;
++ status = "okay";
++};
++
++&usb_host0_xhci {
++ dr_mode = "host";
++ status = "okay";
++};
++
++&usbdp_phy0 {
++ status = "okay";
++};
--- /dev/null
+From 50decd493c8394c52d04561fe4ede34df27a46ba Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Mon, 21 Oct 2024 01:39:46 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board
+
+The NanoPi R3S(as "R3S") is an open source platform with dual-Gbps
+Ethernet ports designed and developed by FriendlyElec for IoT
+applications.
+
+Specification:
+- Rockchip RK3566
+- 2GB LPDDR4X RAM
+- optional 32GB eMMC module
+- SD card slot
+- 2x 1000 Base-T
+- 3x LEDs (POWER, LAN, WAN)
+- 2x Buttons (Reset, MaskROM)
+- 1x USB 3.0 Port
+- Type-C 5V 2A Power
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20241020173946.225960-2-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../boot/dts/rockchip/rk3566-nanopi-r3s.dts | 554 ++++++++++++++++++
+ 2 files changed, 555 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-an
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-nanopi-r3s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-odroid-m1s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v1.1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v2.1.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+@@ -0,0 +1,554 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
++ *
++ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ *
++ * Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3566.dtsi"
++
++/ {
++ model = "FriendlyARM NanoPi R3S";
++ compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566";
++
++ aliases {
++ ethernet0 = &gmac1;
++ mmc0 = &sdmmc0;
++ mmc1 = &sdhci;
++ };
++
++ chosen: chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&reset_button_pin>;
++
++ button-reset {
++ label = "reset";
++ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_RESTART>;
++ debounce-interval = <50>;
++ };
++ };
++
++ gpio-leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&power_led_pin>, <&lan_led_pin>, <&wan_led_pin>;
++
++ power_led: led-0 {
++ color = <LED_COLOR_ID_RED>;
++ function = LED_FUNCTION_POWER;
++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ };
++
++ lan_led: led-1 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_LAN;
++ gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
++ };
++
++ wan_led: led-2 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_WAN;
++ gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ vcc3v3_sys: regulator-vcc3v3-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc5v0_sys: regulator-vcc5v0-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vdd_usbc>;
++ };
++
++ vcc5v0_usb: regulator-vcc5v0_usb {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vcc5v0_usb_host_en>;
++ regulator-name = "vcc5v0_usb";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vdd_usbc: regulator-vdd-usbc {
++ compatible = "regulator-fixed";
++ regulator-name = "vdd_usbc";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++};
++
++&combphy1 {
++ status = "okay";
++};
++
++&combphy2 {
++ status = "okay";
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&gmac1 {
++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
++ assigned-clock-rates = <0>, <125000000>;
++ clock_in_out = "output";
++ phy-mode = "rgmii-id";
++ phy-handle = <&rgmii_phy1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac1m0_miim
++ &gmac1m0_tx_bus2_level3
++ &gmac1m0_rx_bus2
++ &gmac1m0_rgmii_clk_level2
++ &gmac1m0_rgmii_bus_level3>;
++ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
++ snps,reset-active-low;
++ /* Reset time is 20ms, 100ms for rtl8211f */
++ snps,reset-delays-us = <0 20000 100000>;
++ status = "okay";
++};
++
++&gpu {
++ mali-supply = <&vdd_gpu>;
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++
++ vdd_cpu: regulator@1c {
++ compatible = "tcs,tcs4525";
++ reg = <0x1c>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1150000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ rk809: pmic@20 {
++ compatible = "rockchip,rk809";
++ reg = <0x20>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++ #clock-cells = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_int>;
++ system-power-controller;
++ vcc1-supply = <&vcc3v3_sys>;
++ vcc2-supply = <&vcc3v3_sys>;
++ vcc3-supply = <&vcc3v3_sys>;
++ vcc4-supply = <&vcc3v3_sys>;
++ vcc5-supply = <&vcc3v3_sys>;
++ vcc6-supply = <&vcc3v3_sys>;
++ vcc7-supply = <&vcc3v3_sys>;
++ vcc8-supply = <&vcc3v3_sys>;
++ vcc9-supply = <&vcc3v3_sys>;
++ wakeup-source;
++
++ regulators {
++ vdd_logic: DCDC_REG1 {
++ regulator-name = "vdd_logic";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_gpu: DCDC_REG2 {
++ regulator-name = "vdd_gpu";
++ regulator-always-on;
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-initial-mode = <0x2>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vdd_npu: DCDC_REG4 {
++ regulator-name = "vdd_npu";
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8: DCDC_REG5 {
++ regulator-name = "vcc_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda0v9_image: LDO_REG1 {
++ regulator-name = "vdda0v9_image";
++ regulator-min-microvolt = <950000>;
++ regulator-max-microvolt = <950000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_0v9: LDO_REG2 {
++ regulator-name = "vdda_0v9";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda0v9_pmu: LDO_REG3 {
++ regulator-name = "vdda0v9_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <900000>;
++ };
++ };
++
++ vccio_acodec: LDO_REG4 {
++ regulator-name = "vccio_acodec";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vccio_sd: LDO_REG5 {
++ regulator-name = "vccio_sd";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc3v3_pmu: LDO_REG6 {
++ regulator-name = "vcc3v3_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcca_1v8: LDO_REG7 {
++ regulator-name = "vcca_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca1v8_pmu: LDO_REG8 {
++ regulator-name = "vcca1v8_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcca1v8_image: LDO_REG9 {
++ regulator-name = "vcca1v8_image";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_3v3: SWITCH_REG1 {
++ regulator-name = "vcc_3v3";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc3v3_sd: SWITCH_REG2 {
++ regulator-name = "vcc3v3_sd";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++&i2c1 {
++ status = "okay";
++
++ hym8563: rtc@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ #clock-cells = <0>;
++ clock-output-names = "hym8563";
++ pinctrl-names = "default";
++ pinctrl-0 = <&hym8563_int>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
++ wakeup-source;
++ };
++};
++
++&mdio1 {
++ rgmii_phy1: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ interrupt-parent = <&gpio4>;
++ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <ð_phy_reset_pin>;
++ };
++};
++
++&pcie2x1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie_reset_h>;
++ reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&pinctrl {
++ gpio-leds {
++ lan_led_pin: lan-led-pin {
++ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ power_led_pin: power-led-pin {
++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ wan_led_pin: wan-led-pin {
++ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ gmac {
++ eth_phy_reset_pin: eth-phy-reset-pin {
++ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ pcie {
++ pcie_reset_h: pcie-reset-h {
++ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++ };
++
++ pmic {
++ pmic_int: pmic-int {
++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ rockchip-key {
++ reset_button_pin: reset-button-pin {
++ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ rtc {
++ hym8563_int: hym8563-int {
++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ usb {
++ vcc5v0_usb_host_en: vcc5v0-usb-host-en {
++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&pmu_io_domains {
++ status = "okay";
++ pmuio1-supply = <&vcc3v3_pmu>;
++ pmuio2-supply = <&vcc3v3_pmu>;
++ vccio1-supply = <&vccio_acodec>;
++ vccio2-supply = <&vcc_1v8>;
++ vccio3-supply = <&vccio_sd>;
++ vccio4-supply = <&vcc_3v3>;
++ vccio5-supply = <&vcc_1v8>;
++ vccio6-supply = <&vcc_3v3>;
++ vccio7-supply = <&vcc_3v3>;
++};
++
++&sdhci {
++ bus-width = <8>;
++ max-frequency = <200000000>;
++ non-removable;
++ pinctrl-names = "default";
++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
++ status = "okay";
++};
++
++&sdmmc0 {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ no-sdio;
++ no-mmc;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++ sd-uhs-sdr50;
++ vmmc-supply = <&vcc3v3_sd>;
++ vqmmc-supply = <&vccio_sd>;
++ status = "okay";
++};
++
++&tsadc {
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&usb2phy0 {
++ status = "okay";
++};
++
++&usb2phy0_host {
++ phy-supply = <&vcc5v0_usb>;
++ status = "okay";
++};
++
++&usb2phy0_otg {
++ status = "okay";
++};
++
++&usb_host0_xhci {
++ extcon = <&usb2phy0>;
++ status = "okay";
++};
++
++&usb_host1_xhci {
++ status = "okay";
++};
++
++&vop {
++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
--- /dev/null
+From b5bf84206a5c77528f9dd4cbca4e72caa063c102 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Wed, 23 Oct 2024 03:35:26 +0800
+Subject: [PATCH] arm64: dts: rockchip: fix model name for FriendlyElec NanoPi
+ R3S
+
+Use the marketing name for model name, this matches the dt-binding.
+Also update the website url in copyright.
+
+Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
+Suggested-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20241022193537.1117919-2-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+@@ -3,7 +3,7 @@
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ *
+ * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd.
+- * (http://www.friendlyarm.com)
++ * (http://www.friendlyelec.com)
+ *
+ * Copyright (c) 2024 Tianling Shen <cnsztl@gmail.com>
+ */
+@@ -17,7 +17,7 @@
+ #include "rk3566.dtsi"
+
+ / {
+- model = "FriendlyARM NanoPi R3S";
++ model = "FriendlyElec NanoPi R3S";
+ compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566";
+
+ aliases {
--- /dev/null
+From 82b2868937883b65732da498b26366d34db61510 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Wed, 23 Oct 2024 03:35:27 +0800
+Subject: [PATCH] arm64: dts: rockchip: replace deprecated snps,reset props for
+ NanoPi R3S
+
+Replace deprecated snps,reset props and move them to the PHY node.
+
+Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
+Suggested-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20241022193537.1117919-3-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+@@ -149,10 +149,6 @@
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk_level2
+ &gmac1m0_rgmii_bus_level3>;
+- snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+- snps,reset-active-low;
+- /* Reset time is 20ms, 100ms for rtl8211f */
+- snps,reset-delays-us = <0 20000 100000>;
+ status = "okay";
+ };
+
+@@ -414,6 +410,9 @@
+ interrupts = <RK_PC3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <ð_phy_reset_pin>;
++ reset-assert-us = <20000>;
++ reset-deassert-us = <100000>;
++ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
--- /dev/null
+From 17e150fdd983c7e59b9240e34a166285f3c3fb39 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Wed, 23 Oct 2024 03:35:28 +0800
+Subject: [PATCH] arm64: dts: rockchip: sort props in pmu_io_domains node for
+ NanoPi R3S
+
+The status prop is typically the last prop.
+
+Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
+Suggested-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20241022193537.1117919-4-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+@@ -476,7 +476,6 @@
+ };
+
+ &pmu_io_domains {
+- status = "okay";
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+@@ -486,6 +485,7 @@
+ vccio5-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
++ status = "okay";
+ };
+
+ &sdhci {
--- /dev/null
+From 1b5365034410f1ca21adadadd492b99bdf4f2c55 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Wed, 23 Oct 2024 03:35:29 +0800
+Subject: [PATCH] arm64: dts: rockchip: enable eMMC HS200 mode for NanoPi R3S
+
+It is required to boot from eMMC without additional patch in u-boot.
+
+Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
+Suggested-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20241022193537.1117919-5-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+@@ -491,6 +491,7 @@
+ &sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
++ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
--- /dev/null
+From b7cd1115456d312f8c5e60c80fdc35fd35ea6eab Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Wed, 23 Oct 2024 03:35:30 +0800
+Subject: [PATCH] arm64: dts: rockchip: reorder mmc aliases for NanoPi R3S
+
+Typically any non-removable storage (emmc) is listed before removable
+storage (sd-card) options. Also U-Boot will try to override and use
+mmc0=sdhci and mmc1=sdmmc0 for all rk356x boards.
+
+Fixes: 50decd493c83 ("arm64: dts: rockchip: Add FriendlyARM NanoPi R3S board")
+Suggested-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20241022193537.1117919-6-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+@@ -22,8 +22,8 @@
+
+ aliases {
+ ethernet0 = &gmac1;
+- mmc0 = &sdmmc0;
+- mmc1 = &sdhci;
++ mmc0 = &sdhci;
++ mmc1 = &sdmmc0;
+ };
+
+ chosen: chosen {
--- /dev/null
+From f15be3d4a0a55db2b50f319c378a2d16ceb21f86 Mon Sep 17 00:00:00 2001
+From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Date: Mon, 17 Feb 2025 01:16:33 +0300
+Subject: [PATCH] arm64: dts: rockchip: rk356x: Add MSI controller node
+
+Rockchip 356x SoC's GIC has two hardware integration issues that
+affect MSI functionality of the GIC. Previously, both these GIC
+issues were worked around by using MBI for MSI instead of ITS
+because kernel GIC driver didn't have necessary quirks.
+
+First issue is about RK356x GIC not supporting programmable
+shareability, while reporting it as supported in a GIC's feature
+register. Rockchip assigned Erratum ID #3568001 for this issue. This
+patch adds dma-noncoherent property to the GIC node, denoting that a SW
+workaround is required for mitigating the issue.
+
+Second issue is about GIC AXI master interface addressing limited to
+the first 4GB of physical address space. Rockchip assigned Erratum
+ID #3568002 for this issue.
+
+Now that kernel supports quirks for both of the erratums, add
+MSI controller node to RK356x device-tree.
+
+Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Link: https://lore.kernel.org/all/20250216221634.364158-3-dmitry.osipenko@collabora.com
+---
+ arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -364,6 +364,18 @@
+ mbi-alias = <0x0 0xfd410000>;
+ mbi-ranges = <296 24>;
+ msi-controller;
++ ranges;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ dma-noncoherent;
++
++ its: msi-controller@fd440000 {
++ compatible = "arm,gic-v3-its";
++ reg = <0x0 0xfd440000 0 0x20000>;
++ dma-noncoherent;
++ msi-controller;
++ #msi-cells = <1>;
++ };
+ };
+
+ usb_host0_ehci: usb@fd800000 {
--- /dev/null
+From b956c9de91757c9478e24fc9f6a57fd46f0a49f0 Mon Sep 17 00:00:00 2001
+From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Date: Mon, 17 Feb 2025 01:16:34 +0300
+Subject: [PATCH] arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC
+ ITS instead of MBI
+
+Rockchip 356x device-tree now supports GIC ITS. Move PCIe controller's
+MSI to use ITS instead of MBI. This removes extra CPU overhead of handling
+PCIe MBIs by letting GIC's ITS to serve the PCIe MSIs.
+
+Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Link: https://lore.kernel.org/all/20250216221634.364158-4-dmitry.osipenko@collabora.com
+---
+ arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1050,7 +1050,7 @@
+ num-ib-windows = <6>;
+ num-ob-windows = <2>;
+ max-link-speed = <2>;
+- msi-map = <0x0 &gic 0x0 0x1000>;
++ msi-map = <0x0 &its 0x0 0x1000>;
+ num-lanes = <1>;
+ phys = <&combphy2 PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
--- /dev/null
+From fbea35a661ed100cee2f3bab8015fb0155508106 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Sat, 8 Mar 2025 17:30:08 +0800
+Subject: [PATCH] arm64: dts: rockchip: Move rk3568 PCIe3 MSI to use GIC ITS
+
+Following commit b956c9de9175 ("arm64: dts: rockchip: rk356x: Move
+PCIe MSI to use GIC ITS instead of MBI"), change the PCIe3 controller's
+MSI on rk3568 to use ITS, so that all MSI-X can work properly.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20250308093008.568437-2-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+@@ -64,7 +64,7 @@
+ compatible = "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+- bus-range = <0x0 0xf>;
++ bus-range = <0x10 0x1f>;
+ clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
+ <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
+ <&cru CLK_PCIE30X1_AUX_NDFT>;
+@@ -87,7 +87,7 @@
+ num-ib-windows = <6>;
+ num-ob-windows = <2>;
+ max-link-speed = <3>;
+- msi-map = <0x0 &gic 0x1000 0x1000>;
++ msi-map = <0x1000 &its 0x1000 0x1000>;
+ num-lanes = <1>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
+@@ -117,7 +117,7 @@
+ compatible = "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+- bus-range = <0x0 0xf>;
++ bus-range = <0x20 0x2f>;
+ clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
+ <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
+ <&cru CLK_PCIE30X2_AUX_NDFT>;
+@@ -140,7 +140,7 @@
+ num-ib-windows = <6>;
+ num-ob-windows = <2>;
+ max-link-speed = <3>;
+- msi-map = <0x0 &gic 0x2000 0x1000>;
++ msi-map = <0x2000 &its 0x2000 0x1000>;
+ num-lanes = <2>;
+ phys = <&pcie30phy>;
+ phy-names = "pcie-phy";
--- /dev/null
+From a6ae420439dc47a58550a6e61e596e9dd1562caf Mon Sep 17 00:00:00 2001
+From: Rick Wertenbroek <rick.wertenbroek@gmail.com>
+Date: Wed, 6 Nov 2024 14:03:13 +0100
+Subject: [PATCH] arm64: dts: rockchip: enable USB3 on NanoPC-T6
+
+Enable the USB3 port on FriendlyELEC NanoPC-T6.
+
+Signed-off-by: Rick Wertenbroek <rick.wertenbroek@gmail.com>
+Link: https://lore.kernel.org/r/20241106130314.1289055-1-rick.wertenbroek@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 36 +++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
+@@ -159,6 +159,20 @@
+ vin-supply = <&vcc5v0_sys>;
+ };
+
++ vbus5v0_usb: vbus5v0-usb-regulator {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb5v_pwren>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vbus5v0_usb";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
+ vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+@@ -575,6 +589,10 @@
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
++ usb5v_pwren: usb5v_pwren {
++ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
+ usbc0_int: usbc0-int {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+@@ -973,6 +991,14 @@
+ status = "okay";
+ };
+
++&u2phy1 {
++ status = "okay";
++};
++
++&u2phy1_otg {
++ status = "okay";
++};
++
+ &u2phy2_host {
+ status = "okay";
+ };
+@@ -1012,6 +1038,11 @@
+ };
+ };
+
++&usbdp_phy1 {
++ phy-supply = <&vbus5v0_usb>;
++ status = "okay";
++};
++
+ &usb_host0_ehci {
+ status = "okay";
+ };
+@@ -1032,6 +1063,11 @@
+ };
+ };
+
++&usb_host1_xhci {
++ dr_mode = "host";
++ status = "okay";
++};
++
+ &usb_host1_ehci {
+ status = "okay";
+ };
--- /dev/null
+From deaefeaf3df433d50935b9a85076041040f06d74 Mon Sep 17 00:00:00 2001
+From: Liangbin Lian <jjm2473@gmail.com>
+Date: Tue, 14 Oct 2025 13:12:26 +0800
+Subject: [PATCH] arm64: dts: rockchip: add LinkEase EasePi R1
+
+LinkEase EasePi R1 [1] is a high-performance mini router.
+
+Specification:
+- Rockchip RK3568
+- 2GB/4GB LPDDR4 RAM
+- 16GB on-board eMMC
+- 1x M.2 key for 2280 NVMe (PCIe 3.0)
+- 1x USB 3.0 Type-A
+- 1x USB 2.0 Type-C (for USB flashing)
+- 2x 1000 Base-T (native, RTL8211F)
+- 2x 2500 Base-T (PCIe, RTL8125B)
+- 1x HDMI 2.0 Output
+- 12v DC Jack
+- 1x Power key connected to PMIC
+- 2x LEDs (one static power supplied, one GPIO controlled)
+
+[1] https://doc.linkease.com/zh/guide/easepi-r1/hardware.html
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Liangbin Lian <jjm2473@gmail.com>
+Link: https://patch.msgid.link/20251014051226.64255-4-jjm2473@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../boot/dts/rockchip/rk3568-easepi-r1.dts | 623 ++++++++++++++++++
+ 2 files changed, 624 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -109,6 +109,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bo
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lckfb-tspi.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-easepi-r1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts
+@@ -0,0 +1,623 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3568.dtsi"
++
++/ {
++ model = "LinkEase EasePi R1";
++ compatible = "linkease,easepi-r1", "rockchip,rk3568";
++
++ aliases {
++ ethernet0 = &gmac0;
++ ethernet1 = &gmac1;
++ mmc0 = &sdhci;
++ };
++
++ chosen: chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ adc-keys {
++ compatible = "adc-keys";
++ io-channels = <&saradc 0>;
++ io-channel-names = "buttons";
++ keyup-threshold-microvolt = <1800000>;
++
++ button-recovery {
++ label = "Recovery";
++ linux,code = <KEY_VENDOR>;
++ press-threshold-microvolt = <1750>;
++ };
++ };
++
++ gpio-leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&status_led_pin>;
++
++ status_led: led-status {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_STATUS;
++ gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ hdmi-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
++ dc_12v: regulator-dc-12v {
++ compatible = "regulator-fixed";
++ regulator-name = "dc_12v";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <12000000>;
++ regulator-max-microvolt = <12000000>;
++ };
++
++ vcc5v0_sys: regulator-vcc5v0-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&dc_12v>;
++ };
++
++ vcc3v3_sys: regulator-vcc3v3-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&dc_12v>;
++ };
++
++ pcie30_avdd0v9: regulator-pcie30-avdd0v9 {
++ compatible = "regulator-fixed";
++ regulator-name = "pcie30_avdd0v9";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
++ compatible = "regulator-fixed";
++ regulator-name = "pcie30_avdd1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ regulator-vdd0v95-25glan {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vdd0v95_25glan_en>;
++ regulator-name = "vdd0v95_25glan";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <950000>;
++ regulator-max-microvolt = <950000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ vcc3v3_nvme: regulator-vcc3v3-nvme {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vcc3v3_nvme_en>;
++ regulator-name = "vcc3v3_nvme";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&dc_12v>;
++ };
++
++};
++
++&combphy1 {
++ status = "okay";
++};
++
++&combphy2 {
++ status = "okay";
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&gmac0 {
++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
++ assigned-clock-rates = <0>, <125000000>;
++ phy-handle = <&rgmii_phy0>;
++ phy-mode = "rgmii-id";
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac0_miim
++ &gmac0_tx_bus2
++ &gmac0_rx_bus2
++ &gmac0_rgmii_clk
++ &gmac0_rgmii_bus>;
++ status = "okay";
++};
++
++&gmac1 {
++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
++ assigned-clock-rates = <0>, <125000000>;
++ phy-handle = <&rgmii_phy1>;
++ phy-mode = "rgmii-id";
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac1m1_miim
++ &gmac1m1_tx_bus2
++ &gmac1m1_rx_bus2
++ &gmac1m1_rgmii_clk
++ &gmac1m1_rgmii_bus>;
++ status = "okay";
++};
++
++&gpu {
++ mali-supply = <&vdd_gpu>;
++ status = "okay";
++};
++
++&hdmi {
++ avdd-0v9-supply = <&vdda0v9_image>;
++ avdd-1v8-supply = <&vcca1v8_image>;
++ status = "okay";
++};
++
++&hdmi_in {
++ hdmi_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi>;
++ };
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
++&hdmi_sound {
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++
++ vdd_cpu: regulator@1c {
++ compatible = "tcs,tcs4525";
++ reg = <0x1c>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1150000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ rk809: pmic@20 {
++ compatible = "rockchip,rk809";
++ reg = <0x20>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++ #clock-cells = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_int>;
++ system-power-controller;
++ vcc1-supply = <&vcc3v3_sys>;
++ vcc2-supply = <&vcc3v3_sys>;
++ vcc3-supply = <&vcc3v3_sys>;
++ vcc4-supply = <&vcc3v3_sys>;
++ vcc5-supply = <&vcc3v3_sys>;
++ vcc6-supply = <&vcc3v3_sys>;
++ vcc7-supply = <&vcc3v3_sys>;
++ vcc8-supply = <&vcc3v3_sys>;
++ vcc9-supply = <&vcc3v3_sys>;
++ wakeup-source;
++
++ regulators {
++ vdd_logic: DCDC_REG1 {
++ regulator-name = "vdd_logic";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_gpu: DCDC_REG2 {
++ regulator-name = "vdd_gpu";
++ regulator-always-on;
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-initial-mode = <0x2>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vdd_npu: DCDC_REG4 {
++ regulator-name = "vdd_npu";
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8: DCDC_REG5 {
++ regulator-name = "vcc_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda0v9_image: LDO_REG1 {
++ regulator-name = "vdda0v9_image";
++ regulator-min-microvolt = <950000>;
++ regulator-max-microvolt = <950000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_0v9: LDO_REG2 {
++ regulator-name = "vdda_0v9";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda0v9_pmu: LDO_REG3 {
++ regulator-name = "vdda0v9_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <900000>;
++ };
++ };
++
++ vccio_acodec: LDO_REG4 {
++ regulator-name = "vccio_acodec";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vccio_sd: LDO_REG5 {
++ regulator-name = "vccio_sd";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc3v3_pmu: LDO_REG6 {
++ regulator-name = "vcc3v3_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcca_1v8: LDO_REG7 {
++ regulator-name = "vcca_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca1v8_pmu: LDO_REG8 {
++ regulator-name = "vcca1v8_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcca1v8_image: LDO_REG9 {
++ regulator-name = "vcca1v8_image";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_3v3: SWITCH_REG1 {
++ regulator-name = "vcc_3v3";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc3v3_sd: SWITCH_REG2 {
++ regulator-name = "vcc3v3_sd";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++&i2s0_8ch {
++ status = "okay";
++};
++
++&mdio0 {
++ rgmii_phy0: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0x1>;
++ pinctrl-0 = <ð_phy0_reset_pin>;
++ pinctrl-names = "default";
++ reset-assert-us = <20000>;
++ reset-deassert-us = <100000>;
++ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
++ };
++};
++
++&mdio1 {
++ rgmii_phy1: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0x1>;
++ pinctrl-0 = <ð_phy1_reset_pin>;
++ pinctrl-names = "default";
++ reset-assert-us = <20000>;
++ reset-deassert-us = <100000>;
++ reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
++ };
++};
++
++/* ETH3 */
++&pcie2x1 {
++ reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_sys>;
++ status = "okay";
++};
++
++&pcie30phy {
++ data-lanes = <1 2>;
++ status = "okay";
++};
++
++/* ETH2 */
++&pcie3x1 {
++ num-lanes = <1>;
++ reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_sys>;
++ status = "okay";
++};
++
++/* M.2 Key for 2280 NVMe */
++&pcie3x2 {
++ num-lanes = <1>;
++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_nvme>;
++ status = "okay";
++};
++
++&pinctrl {
++ gmac0 {
++ eth_phy0_reset_pin: eth-phy0-reset-pin {
++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ gmac1 {
++ eth_phy1_reset_pin: eth-phy1-reset-pin {
++ rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ gpio-leds {
++ status_led_pin: status-led-pin {
++ rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ nvme {
++ vcc3v3_nvme_en: vcc3v3-nvme-en {
++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie-nic {
++ vdd0v95_25glan_en: vdd0v95-25glan-en {
++ rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pmic {
++ pmic_int: pmic-int {
++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++};
++
++&pmu_io_domains {
++ pmuio1-supply = <&vcc3v3_pmu>;
++ pmuio2-supply = <&vcc3v3_pmu>;
++ vccio1-supply = <&vccio_acodec>;
++ vccio3-supply = <&vccio_sd>;
++ vccio4-supply = <&vcc_1v8>;
++ vccio5-supply = <&vcc_3v3>;
++ vccio6-supply = <&vcc_1v8>;
++ vccio7-supply = <&vcc_3v3>;
++ status = "okay";
++};
++
++&saradc {
++ vref-supply = <&vcca_1v8>;
++ status = "okay";
++};
++
++&sdhci {
++ bus-width = <8>;
++ max-frequency = <200000000>;
++ non-removable;
++ pinctrl-names = "default";
++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
++ status = "okay";
++};
++
++&tsadc {
++ rockchip,hw-tshut-mode = <1>;
++ rockchip,hw-tshut-polarity = <0>;
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++/* OTG Only USB2.0, Only device mode */
++&usb_host0_xhci {
++ dr_mode = "peripheral";
++ extcon = <&usb2phy0>;
++ maximum-speed = "high-speed";
++ phys = <&usb2phy0_otg>;
++ phy-names = "usb2-phy";
++ status = "okay";
++};
++
++&usb_host1_xhci {
++ status = "okay";
++};
++
++&usb2phy0 {
++ status = "okay";
++};
++
++&usb2phy0_host {
++ phy-supply = <&vcc5v0_sys>;
++ status = "okay";
++};
++
++&usb2phy0_otg {
++ status = "okay";
++};
++
++&vop {
++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi_in_vp0>;
++ };
++};
--- /dev/null
+From 954f07012794a3aa7ae89e56f070eaa1643af50b Mon Sep 17 00:00:00 2001
+From: Diederik de Haas <didi.debian@cknow.org>
+Date: Fri, 11 Jul 2025 16:20:37 +0200
+Subject: [PATCH] arm64: dts: rockchip: Add reset button to NanoPi R5S
+
+The NanoPi R5S LTS version has a reset button, which is connected via
+GPIO. Note that the non-LTS version does not have the reset button and
+therefore on page 19 of the schematic version 2204 it is marked 'NC',
+but it is connected on the LTS version.
+
+Link: https://lore.kernel.org/r/20250711142138.197445-1-didi.debian@cknow.org
+Signed-off-by: Diederik de Haas <didi.debian@cknow.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+@@ -17,6 +17,19 @@
+ ethernet0 = &gmac0;
+ };
+
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-0 = <&gpio4_a0_k1_pin>;
++ pinctrl-names = "default";
++
++ button-reset {
++ debounce-interval = <50>;
++ gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
++ label = "RESET";
++ linux,code = <KEY_RESTART>;
++ };
++ };
++
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+@@ -116,6 +129,12 @@
+ };
+ };
+
++ gpio-keys {
++ gpio4_a0_k1_pin: gpio4-a0-k1-pin {
++ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ gpio-leds {
+ lan1_led_pin: lan1-led-pin {
+ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
--- /dev/null
+From b08e2f42e86b5848add254da45b56fc672e2bced Mon Sep 17 00:00:00 2001
+From: Steven Price <steven.price@arm.com>
+Date: Wed, 2 Oct 2024 15:16:29 +0100
+Subject: [PATCH] irqchip/gic-v3-its: Share ITS tables with a non-trusted
+ hypervisor
+
+Within a realm guest the ITS is emulated by the host. This means the
+allocations must have been made available to the host by a call to
+set_memory_decrypted(). Introduce an allocation function which performs
+this extra call.
+
+For the ITT use a custom genpool-based allocator that calls
+set_memory_decrypted() for each page allocated, but then suballocates the
+size needed for each ITT. Note that there is no mechanism implemented to
+return pages from the genpool, but it is unlikely that the peak number of
+devices will be much larger than the normal level - so this isn't expected
+to be an issue.
+
+Co-developed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
+Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
+Signed-off-by: Steven Price <steven.price@arm.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Tested-by: Will Deacon <will@kernel.org>
+Reviewed-by: Marc Zyngier <maz@kernel.org>
+Link: https://lore.kernel.org/all/20241002141630.433502-2-steven.price@arm.com
+---
+ drivers/irqchip/irq-gic-v3-its.c | 138 +++++++++++++++++++++++++------
+ 1 file changed, 115 insertions(+), 23 deletions(-)
+
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -12,12 +12,14 @@
+ #include <linux/crash_dump.h>
+ #include <linux/delay.h>
+ #include <linux/efi.h>
++#include <linux/genalloc.h>
+ #include <linux/interrupt.h>
+ #include <linux/iommu.h>
+ #include <linux/iopoll.h>
+ #include <linux/irqdomain.h>
+ #include <linux/list.h>
+ #include <linux/log2.h>
++#include <linux/mem_encrypt.h>
+ #include <linux/memblock.h>
+ #include <linux/mm.h>
+ #include <linux/msi.h>
+@@ -27,6 +29,7 @@
+ #include <linux/of_pci.h>
+ #include <linux/of_platform.h>
+ #include <linux/percpu.h>
++#include <linux/set_memory.h>
+ #include <linux/slab.h>
+ #include <linux/syscore_ops.h>
+
+@@ -166,6 +169,7 @@ struct its_device {
+ struct its_node *its;
+ struct event_lpi_map event_map;
+ void *itt;
++ u32 itt_sz;
+ u32 nr_ites;
+ u32 device_id;
+ bool shared;
+@@ -201,6 +205,87 @@ static DEFINE_IDA(its_vpeid_ida);
+ #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
+ #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
+
++static struct page *its_alloc_pages_node(int node, gfp_t gfp,
++ unsigned int order)
++{
++ struct page *page;
++ int ret = 0;
++
++ page = alloc_pages_node(node, gfp, order);
++
++ if (!page)
++ return NULL;
++
++ ret = set_memory_decrypted((unsigned long)page_address(page),
++ 1 << order);
++ /*
++ * If set_memory_decrypted() fails then we don't know what state the
++ * page is in, so we can't free it. Instead we leak it.
++ * set_memory_decrypted() will already have WARNed.
++ */
++ if (ret)
++ return NULL;
++
++ return page;
++}
++
++static struct page *its_alloc_pages(gfp_t gfp, unsigned int order)
++{
++ return its_alloc_pages_node(NUMA_NO_NODE, gfp, order);
++}
++
++static void its_free_pages(void *addr, unsigned int order)
++{
++ /*
++ * If the memory cannot be encrypted again then we must leak the pages.
++ * set_memory_encrypted() will already have WARNed.
++ */
++ if (set_memory_encrypted((unsigned long)addr, 1 << order))
++ return;
++ free_pages((unsigned long)addr, order);
++}
++
++static struct gen_pool *itt_pool;
++
++static void *itt_alloc_pool(int node, int size)
++{
++ unsigned long addr;
++ struct page *page;
++
++ if (size >= PAGE_SIZE) {
++ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, get_order(size));
++
++ return page ? page_address(page) : NULL;
++ }
++
++ do {
++ addr = gen_pool_alloc(itt_pool, size);
++ if (addr)
++ break;
++
++ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 1);
++ if (!page)
++ break;
++
++ gen_pool_add(itt_pool, (unsigned long)page_address(page), PAGE_SIZE, node);
++ } while (!addr);
++
++ return (void *)addr;
++}
++
++static void itt_free_pool(void *addr, int size)
++{
++ if (!addr)
++ return;
++
++ if (size >= PAGE_SIZE) {
++ its_free_pages(addr, get_order(size));
++ return;
++ }
++
++ gen_pool_free(itt_pool, (unsigned long)addr, size);
++}
++
+ /*
+ * Skip ITSs that have no vLPIs mapped, unless we're on GICv4.1, as we
+ * always have vSGIs mapped.
+@@ -2183,7 +2268,8 @@ static struct page *its_allocate_prop_ta
+ {
+ struct page *prop_page;
+
+- prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
++ prop_page = its_alloc_pages(gfp_flags,
++ get_order(LPI_PROPBASE_SZ));
+ if (!prop_page)
+ return NULL;
+
+@@ -2194,8 +2280,7 @@ static struct page *its_allocate_prop_ta
+
+ static void its_free_prop_table(struct page *prop_page)
+ {
+- free_pages((unsigned long)page_address(prop_page),
+- get_order(LPI_PROPBASE_SZ));
++ its_free_pages(page_address(prop_page), get_order(LPI_PROPBASE_SZ));
+ }
+
+ static bool gic_check_reserved_range(phys_addr_t addr, unsigned long size)
+@@ -2317,7 +2402,7 @@ static int its_setup_baser(struct its_no
+ order = get_order(GITS_BASER_PAGES_MAX * psz);
+ }
+
+- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
++ page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
+ if (!page)
+ return -ENOMEM;
+
+@@ -2330,7 +2415,7 @@ static int its_setup_baser(struct its_no
+ /* 52bit PA is supported only when PageSize=64K */
+ if (psz != SZ_64K) {
+ pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
+- free_pages((unsigned long)base, order);
++ its_free_pages(base, order);
+ return -ENXIO;
+ }
+
+@@ -2386,7 +2471,7 @@ retry_baser:
+ pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
+ &its->phys_base, its_base_type_string[type],
+ val, tmp);
+- free_pages((unsigned long)base, order);
++ its_free_pages(base, order);
+ return -ENXIO;
+ }
+
+@@ -2525,8 +2610,7 @@ static void its_free_tables(struct its_n
+
+ for (i = 0; i < GITS_BASER_NR_REGS; i++) {
+ if (its->tables[i].base) {
+- free_pages((unsigned long)its->tables[i].base,
+- its->tables[i].order);
++ its_free_pages(its->tables[i].base, its->tables[i].order);
+ its->tables[i].base = NULL;
+ }
+ }
+@@ -2792,7 +2876,7 @@ static bool allocate_vpe_l2_table(int cp
+
+ /* Allocate memory for 2nd level table */
+ if (!table[idx]) {
+- page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
++ page = its_alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(psz));
+ if (!page)
+ return false;
+
+@@ -2911,7 +2995,7 @@ static int allocate_vpe_l1_table(void)
+
+ pr_debug("np = %d, npg = %lld, psz = %d, epp = %d, esz = %d\n",
+ np, npg, psz, epp, esz);
+- page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
++ page = its_alloc_pages(GFP_ATOMIC | __GFP_ZERO, get_order(np * PAGE_SIZE));
+ if (!page)
+ return -ENOMEM;
+
+@@ -2957,8 +3041,7 @@ static struct page *its_allocate_pending
+ {
+ struct page *pend_page;
+
+- pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
+- get_order(LPI_PENDBASE_SZ));
++ pend_page = its_alloc_pages(gfp_flags | __GFP_ZERO, get_order(LPI_PENDBASE_SZ));
+ if (!pend_page)
+ return NULL;
+
+@@ -2970,7 +3053,7 @@ static struct page *its_allocate_pending
+
+ static void its_free_pending_table(struct page *pt)
+ {
+- free_pages((unsigned long)page_address(pt), get_order(LPI_PENDBASE_SZ));
++ its_free_pages(page_address(pt), get_order(LPI_PENDBASE_SZ));
+ }
+
+ /*
+@@ -3305,8 +3388,8 @@ static bool its_alloc_table_entry(struct
+
+ /* Allocate memory for 2nd level table */
+ if (!table[idx]) {
+- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
+- get_order(baser->psz));
++ page = its_alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
++ get_order(baser->psz));
+ if (!page)
+ return false;
+
+@@ -3402,7 +3485,6 @@ static struct its_device *its_create_dev
+ if (WARN_ON(!is_power_of_2(nvecs)))
+ nvecs = roundup_pow_of_two(nvecs);
+
+- dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ /*
+ * Even if the device wants a single LPI, the ITT must be
+ * sized as a power of two (and you need at least one bit...).
+@@ -3413,7 +3495,11 @@ static struct its_device *its_create_dev
+ nr_ites = max(2, nvecs);
+ sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
+ sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
+- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
++
++ itt = itt_alloc_pool(its->numa_node, sz);
++
++ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
++
+ if (alloc_lpis) {
+ lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
+ if (lpi_map)
+@@ -3425,9 +3511,9 @@ static struct its_device *its_create_dev
+ lpi_base = 0;
+ }
+
+- if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
++ if (!dev || !itt || !col_map || (!lpi_map && alloc_lpis)) {
+ kfree(dev);
+- kfree(itt);
++ itt_free_pool(itt, sz);
+ bitmap_free(lpi_map);
+ kfree(col_map);
+ return NULL;
+@@ -3437,6 +3523,7 @@ static struct its_device *its_create_dev
+
+ dev->its = its;
+ dev->itt = itt;
++ dev->itt_sz = sz;
+ dev->nr_ites = nr_ites;
+ dev->event_map.lpi_map = lpi_map;
+ dev->event_map.col_map = col_map;
+@@ -3464,7 +3551,7 @@ static void its_free_device(struct its_d
+ list_del(&its_dev->entry);
+ raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
+ kfree(its_dev->event_map.col_map);
+- kfree(its_dev->itt);
++ itt_free_pool(its_dev->itt, its_dev->itt_sz);
+ kfree(its_dev);
+ }
+
+@@ -5164,8 +5251,9 @@ static int __init its_probe_one(struct i
+ }
+ }
+
+- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
+- get_order(ITS_CMD_QUEUE_SZ));
++ page = its_alloc_pages_node(its->numa_node,
++ GFP_KERNEL | __GFP_ZERO,
++ get_order(ITS_CMD_QUEUE_SZ));
+ if (!page) {
+ err = -ENOMEM;
+ goto out_unmap_sgir;
+@@ -5229,7 +5317,7 @@ static int __init its_probe_one(struct i
+ out_free_tables:
+ its_free_tables(its);
+ out_free_cmd:
+- free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
++ its_free_pages(its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
+ out_unmap_sgir:
+ if (its->sgir_base)
+ iounmap(its->sgir_base);
+@@ -5715,6 +5803,10 @@ int __init its_init(struct fwnode_handle
+ bool has_v4_1 = false;
+ int err;
+
++ itt_pool = gen_pool_create(get_order(ITS_ITT_ALIGN), -1);
++ if (!itt_pool)
++ return -ENOMEM;
++
+ gic_rdists = rdists;
+
+ lpi_prop_prio = irq_prio;
--- /dev/null
+From bc88d44bd7e45b992cf8c2c2ffbc7bb3e24db4a7 Mon Sep 17 00:00:00 2001
+From: Steven Price <steven.price@arm.com>
+Date: Mon, 21 Oct 2024 11:41:05 +0100
+Subject: [PATCH] irqchip/gic-v3-its: Fix over allocation in
+ itt_alloc_pool()
+
+itt_alloc_pool() calls its_alloc_pages_node() to allocate an individual
+page to add to the pool (for allocations <PAGE_SIZE). However the final
+argument of its_alloc_pages_node() is the page order not the number of
+pages. Currently it allocates two pages and leaks the second page.
+Fix it by passing 0 instead (1 << 0 = 1 page).
+
+Fixes: b08e2f42e86b ("irqchip/gic-v3-its: Share ITS tables with a non-trusted hypervisor")
+Reported-by: Shanker Donthineni <sdonthineni@nvidia.com>
+Signed-off-by: Steven Price <steven.price@arm.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Link: https://lore.kernel.org/all/1f6e19c4-1fb9-43ab-a8a2-a465c9cff84b@arm.com
+Closes: https://lore.kernel.org/r/ed65312a-245c-4fa5-91ad-5d620cab7c6b%40nvidia.com
+---
+ drivers/irqchip/irq-gic-v3-its.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -263,7 +263,7 @@ static void *itt_alloc_pool(int node, in
+ if (addr)
+ break;
+
+- page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 1);
++ page = its_alloc_pages_node(node, GFP_KERNEL | __GFP_ZERO, 0);
+ if (!page)
+ break;
+
--- /dev/null
+From 2d81e1bb625238d40a686ed909ff3e1abab7556a Mon Sep 17 00:00:00 2001
+From: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Date: Mon, 17 Feb 2025 01:16:32 +0300
+Subject: [PATCH] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround
+
+Rockchip RK3566/RK3568 GIC600 integration has DDR addressing
+limited to the first 32bit of physical address space. Rockchip
+assigned Erratum ID #3568002 for this issue. Add driver quirk for
+this Rockchip GIC Erratum.
+
+Note, that the 0x0201743b GIC600 ID is not Rockchip-specific and is
+common for many ARM GICv3 implementations. Hence, there is an extra
+of_machine_is_compatible() check.
+
+Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
+Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
+Acked-by: Marc Zyngier <maz@kernel.org>
+Link: https://lore.kernel.org/all/20250216221634.364158-2-dmitry.osipenko@collabora.com
+---
+ Documentation/arch/arm64/silicon-errata.rst | 2 ++
+ arch/arm64/Kconfig | 9 ++++++++
+ drivers/irqchip/irq-gic-v3-its.c | 23 ++++++++++++++++++++-
+ 3 files changed, 33 insertions(+), 1 deletion(-)
+
+--- a/Documentation/arch/arm64/silicon-errata.rst
++++ b/Documentation/arch/arm64/silicon-errata.rst
+@@ -285,6 +285,8 @@ stable kernels.
+ +----------------+-----------------+-----------------+-----------------------------+
+ | Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_3588001 |
+ +----------------+-----------------+-----------------+-----------------------------+
++| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_3568002 |
+++----------------+-----------------+-----------------+-----------------------------+
+ +----------------+-----------------+-----------------+-----------------------------+
+ | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
+ +----------------+-----------------+-----------------+-----------------------------+
+--- a/arch/arm64/Kconfig
++++ b/arch/arm64/Kconfig
+@@ -1298,6 +1298,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM
+
+ If unsure, say Y.
+
++config ROCKCHIP_ERRATUM_3568002
++ bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB"
++ default y
++ help
++ The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI
++ addressing limited to the first 32bit of physical address space.
++
++ If unsure, say Y.
++
+ config ROCKCHIP_ERRATUM_3588001
+ bool "Rockchip 3588001: GIC600 can not support shareability attributes"
+ default y
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -205,13 +205,15 @@ static DEFINE_IDA(its_vpeid_ida);
+ #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
+ #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K)
+
++static gfp_t gfp_flags_quirk;
++
+ static struct page *its_alloc_pages_node(int node, gfp_t gfp,
+ unsigned int order)
+ {
+ struct page *page;
+ int ret = 0;
+
+- page = alloc_pages_node(node, gfp, order);
++ page = alloc_pages_node(node, gfp | gfp_flags_quirk, order);
+
+ if (!page)
+ return NULL;
+@@ -4892,6 +4894,17 @@ static bool __maybe_unused its_enable_qu
+ return true;
+ }
+
++static bool __maybe_unused its_enable_rk3568002(void *data)
++{
++ if (!of_machine_is_compatible("rockchip,rk3566") &&
++ !of_machine_is_compatible("rockchip,rk3568"))
++ return false;
++
++ gfp_flags_quirk |= GFP_DMA32;
++
++ return true;
++}
++
+ static const struct gic_quirk its_quirks[] = {
+ #ifdef CONFIG_CAVIUM_ERRATUM_22375
+ {
+@@ -4959,6 +4972,14 @@ static const struct gic_quirk its_quirks
+ .property = "dma-noncoherent",
+ .init = its_set_non_coherent,
+ },
++#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002
++ {
++ .desc = "ITS: Rockchip erratum RK3568002",
++ .iidr = 0x0201743b,
++ .mask = 0xffffffff,
++ .init = its_enable_rk3568002,
++ },
++#endif
+ {
+ }
+ };
--- /dev/null
+From 849d9db170fc8a03ce9f64133a1d0cd46c135105 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 4 Feb 2025 16:35:46 +0100
+Subject: [PATCH] dt-bindings: reset: Add SCMI reset IDs for RK3588
+
+When TF-A is used to assert/deassert the resets through SCMI, the
+IDs communicated to it are different than the ones mainline Linux uses.
+
+Import the list of SCMI reset IDs from mainline TF-A so that devicetrees
+can use these IDs more easily.
+
+Co-developed-by: XiaoDong Huang <derrick.huang@rock-chips.com>
+Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+---
+ .../dt-bindings/reset/rockchip,rk3588-cru.h | 41 ++++++++++++++++++-
+ 1 file changed, 40 insertions(+), 1 deletion(-)
+
+--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
++++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
+@@ -1,6 +1,6 @@
+ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+ /*
+- * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ * Copyright (c) 2021, 2024 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2022 Collabora Ltd.
+ *
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+@@ -753,4 +753,43 @@
+
+ #define SRST_A_HDMIRX_BIU 660
+
++/* SCMI Secure Resets */
++
++/* Name=SECURE_SOFTRST_CON00,Offset=0xA00 */
++#define SCMI_SRST_A_SECURE_NS_BIU 10
++#define SCMI_SRST_H_SECURE_NS_BIU 11
++#define SCMI_SRST_A_SECURE_S_BIU 12
++#define SCMI_SRST_H_SECURE_S_BIU 13
++#define SCMI_SRST_P_SECURE_S_BIU 14
++#define SCMI_SRST_CRYPTO_CORE 15
++/* Name=SECURE_SOFTRST_CON01,Offset=0xA04 */
++#define SCMI_SRST_CRYPTO_PKA 16
++#define SCMI_SRST_CRYPTO_RNG 17
++#define SCMI_SRST_A_CRYPTO 18
++#define SCMI_SRST_H_CRYPTO 19
++#define SCMI_SRST_KEYLADDER_CORE 25
++#define SCMI_SRST_KEYLADDER_RNG 26
++#define SCMI_SRST_A_KEYLADDER 27
++#define SCMI_SRST_H_KEYLADDER 28
++#define SCMI_SRST_P_OTPC_S 29
++#define SCMI_SRST_OTPC_S 30
++#define SCMI_SRST_WDT_S 31
++/* Name=SECURE_SOFTRST_CON02,Offset=0xA08 */
++#define SCMI_SRST_T_WDT_S 32
++#define SCMI_SRST_H_BOOTROM 33
++#define SCMI_SRST_A_DCF 34
++#define SCMI_SRST_P_DCF 35
++#define SCMI_SRST_H_BOOTROM_NS 37
++#define SCMI_SRST_P_KEYLADDER 46
++#define SCMI_SRST_H_TRNG_S 47
++/* Name=SECURE_SOFTRST_CON03,Offset=0xA0C */
++#define SCMI_SRST_H_TRNG_NS 48
++#define SCMI_SRST_D_SDMMC_BUFFER 49
++#define SCMI_SRST_H_SDMMC 50
++#define SCMI_SRST_H_SDMMC_BUFFER 51
++#define SCMI_SRST_SDMMC 52
++#define SCMI_SRST_P_TRNG_CHK 53
++#define SCMI_SRST_TRNG_S 54
++
++
+ #endif
--- /dev/null
+From e00fc3d6e7c2d0b2ab5cf03a576df39cd94479aa Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 4 Feb 2025 16:35:47 +0100
+Subject: [PATCH] dt-bindings: rng: add binding for Rockchip RK3588 RNG
+
+The Rockchip RK3588 SoC has two hardware RNGs accessible to the
+non-secure world: an RNG in the Crypto IP, and a standalone RNG that is
+new to this SoC.
+
+Add a binding for this new standalone RNG. It is distinct hardware from
+the existing rockchip,rk3568-rng, and therefore gets its own binding as
+the two hardware IPs are unrelated other than both being made by the
+same vendor.
+
+The RNG is capable of firing an interrupt when entropy is ready.
+
+The reset is optional, as the hardware does a power-on reset, and
+functions without the software manually resetting it.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+---
+ .../bindings/rng/rockchip,rk3588-rng.yaml | 60 +++++++++++++++++++
+ MAINTAINERS | 1 +
+ 2 files changed, 61 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml
+@@ -0,0 +1,60 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/rng/rockchip,rk3588-rng.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip RK3588 TRNG
++
++description: True Random Number Generator on Rockchip RK3588 SoC
++
++maintainers:
++ - Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
++
++properties:
++ compatible:
++ enum:
++ - rockchip,rk3588-rng
++
++ reg:
++ maxItems: 1
++
++ clocks:
++ items:
++ - description: TRNG AHB clock
++
++ interrupts:
++ maxItems: 1
++
++ resets:
++ maxItems: 1
++
++required:
++ - compatible
++ - reg
++ - clocks
++ - interrupts
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
++ #include <dt-bindings/interrupt-controller/arm-gic.h>
++ #include <dt-bindings/interrupt-controller/irq.h>
++ #include <dt-bindings/reset/rockchip,rk3588-cru.h>
++ bus {
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ rng@fe378000 {
++ compatible = "rockchip,rk3588-rng";
++ reg = <0x0 0xfe378000 0x0 0x200>;
++ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
++ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
++ resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>;
++ status = "okay";
++ };
++ };
++
++...
--- /dev/null
+From 52b3b329d8e589575d16d8d9adbca9e08041ee82 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Fri, 7 Mar 2025 10:33:09 +0100
+Subject: [PATCH] dt-bindings: rng: rockchip,rk3588-rng: Drop unnecessary
+ status from example
+
+Device nodes are enabled by default, so no need for 'status = "okay"' in
+the DTS example.
+
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Acked-by: Rob Herring (Arm) <robh@kernel.org>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+---
+ Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml
++++ b/Documentation/devicetree/bindings/rng/rockchip,rk3588-rng.yaml
+@@ -53,7 +53,6 @@ examples:
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>;
+ resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>;
+- status = "okay";
+ };
+ };
+
--- /dev/null
+From 8bb8609293ff3d8998d75c8db605c0529e83bcd9 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 4 Feb 2025 16:35:48 +0100
+Subject: [PATCH] hwrng: rockchip - store dev pointer in driver struct
+
+The rockchip rng driver does a dance to store the dev pointer in the
+hwrng's unsigned long "priv" member. However, since the struct hwrng
+member of rk_rng is not a pointer, we can use container_of to get the
+struct rk_rng instance from just the struct hwrng*, which means we don't
+have to subvert what little there is in C of a type system and can
+instead store a pointer to the device struct in the rk_rng itself.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+---
+ drivers/char/hw_random/rockchip-rng.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/char/hw_random/rockchip-rng.c
++++ b/drivers/char/hw_random/rockchip-rng.c
+@@ -54,6 +54,7 @@ struct rk_rng {
+ void __iomem *base;
+ int clk_num;
+ struct clk_bulk_data *clk_bulks;
++ struct device *dev;
+ };
+
+ /* The mask in the upper 16 bits determines the bits that are updated */
+@@ -70,8 +71,7 @@ static int rk_rng_init(struct hwrng *rng
+ /* start clocks */
+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
+ if (ret < 0) {
+- dev_err((struct device *) rk_rng->rng.priv,
+- "Failed to enable clks %d\n", ret);
++ dev_err(rk_rng->dev, "Failed to enable clocks: %d\n", ret);
+ return ret;
+ }
+
+@@ -105,7 +105,7 @@ static int rk_rng_read(struct hwrng *rng
+ u32 reg;
+ int ret = 0;
+
+- ret = pm_runtime_resume_and_get((struct device *) rk_rng->rng.priv);
++ ret = pm_runtime_resume_and_get(rk_rng->dev);
+ if (ret < 0)
+ return ret;
+
+@@ -122,8 +122,8 @@ static int rk_rng_read(struct hwrng *rng
+ /* Read random data stored in the registers */
+ memcpy_fromio(buf, rk_rng->base + TRNG_RNG_DOUT, to_read);
+ out:
+- pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv);
+- pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv);
++ pm_runtime_mark_last_busy(rk_rng->dev);
++ pm_runtime_put_sync_autosuspend(rk_rng->dev);
+
+ return (ret < 0) ? ret : to_read;
+ }
+@@ -164,7 +164,7 @@ static int rk_rng_probe(struct platform_
+ rk_rng->rng.cleanup = rk_rng_cleanup;
+ }
+ rk_rng->rng.read = rk_rng_read;
+- rk_rng->rng.priv = (unsigned long) dev;
++ rk_rng->dev = dev;
+ rk_rng->rng.quality = 900;
+
+ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
--- /dev/null
+From 24aaa42ed65c0811b598674a593fc653d643a7e6 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 4 Feb 2025 16:35:49 +0100
+Subject: [PATCH] hwrng: rockchip - eliminate some unnecessary dereferences
+
+Despite assigning a temporary variable the value of &pdev->dev early on
+in the probe function, the probe function then continues to use this
+construct when it could just use the local dev variable instead.
+
+Simplify this by using the local dev variable directly.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+---
+ drivers/char/hw_random/rockchip-rng.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/char/hw_random/rockchip-rng.c
++++ b/drivers/char/hw_random/rockchip-rng.c
+@@ -148,7 +148,7 @@ static int rk_rng_probe(struct platform_
+ return dev_err_probe(dev, rk_rng->clk_num,
+ "Failed to get clks property\n");
+
+- rst = devm_reset_control_array_get_exclusive(&pdev->dev);
++ rst = devm_reset_control_array_get_exclusive(dev);
+ if (IS_ERR(rst))
+ return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset property\n");
+
+@@ -171,11 +171,11 @@ static int rk_rng_probe(struct platform_
+ pm_runtime_use_autosuspend(dev);
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+- return dev_err_probe(&pdev->dev, ret, "Runtime pm activation failed.\n");
++ return dev_err_probe(dev, ret, "Runtime pm activation failed.\n");
+
+ ret = devm_hwrng_register(dev, &rk_rng->rng);
+ if (ret)
+- return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n");
++ return dev_err_probe(dev, ret, "Failed to register Rockchip hwrng\n");
+
+ return 0;
+ }
--- /dev/null
+From 8eff8eb83fc0ae8b5f76220e2bb8644d836e99ff Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 4 Feb 2025 16:35:50 +0100
+Subject: [PATCH] hwrng: rockchip - add support for rk3588's standalone TRNG
+
+The RK3588 SoC includes several TRNGs, one part of the Crypto IP block,
+and the other one (referred to as "trngv1") as a standalone new IP.
+
+Add support for this new standalone TRNG to the driver by both
+generalising it to support multiple different rockchip RNGs and then
+implementing the required functionality for the new hardware.
+
+This work was partly based on the downstream vendor driver by Rockchip's
+Lin Jinhan, which is why they are listed as a Co-author.
+
+While the hardware does support notifying the CPU with an IRQ when the
+random data is ready, I've discovered while implementing the code to use
+this interrupt that this results in significantly slower throughput of
+the TRNG even when under heavy CPU load. I assume this is because with
+only 32 bytes of data per invocation, the overhead of reinitialising a
+completion, enabling the interrupt, sleeping and then triggering the
+completion in the IRQ handler is way more expensive than busylooping.
+
+Speaking of busylooping, the poll interval for reading the ISTAT is an
+atomic read with a delay of 0. In my testing, I've found that this gives
+us the largest throughput, and it appears the random data is ready
+pretty much the moment we begin polling, as increasing the poll delay
+leads to a drop in throughput significant enough to not just be due to
+the poll interval missing the ideal timing by a microsecond or two.
+
+According to downstream, the IP should take 1024 clock cycles to
+generate 56 bits of random data, which at 150MHz should work out to
+6.8us. I did not test whether the data really does take 256/56*6.8us
+to arrive, though changing the readl to a __raw_readl makes no
+difference in throughput, and this data does pass the rngtest FIPS
+checks, so I'm not entirely sure what's going on but I presume it's got
+something to do with the AHB bus speed and the memory barriers that
+mainline's readl/writel functions insert.
+
+The only other current SoC that uses this new IP is the Rockchip RV1106,
+but that SoC does not have mainline support as of the time of writing,
+so we make no effort to declare it as supported for now.
+
+Co-developed-by: Lin Jinhan <troy.lin@rock-chips.com>
+Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+---
+ drivers/char/hw_random/Kconfig | 3 +-
+ drivers/char/hw_random/rockchip-rng.c | 234 +++++++++++++++++++++++---
+ 2 files changed, 216 insertions(+), 21 deletions(-)
+
+--- a/drivers/char/hw_random/Kconfig
++++ b/drivers/char/hw_random/Kconfig
+@@ -581,7 +581,8 @@ config HW_RANDOM_ROCKCHIP
+ default HW_RANDOM
+ help
+ This driver provides kernel-side support for the True Random Number
+- Generator hardware found on some Rockchip SoC like RK3566 or RK3568.
++ Generator hardware found on some Rockchip SoCs like RK3566, RK3568
++ or RK3588.
+
+ To compile this driver as a module, choose M here: the
+ module will be called rockchip-rng.
+--- a/drivers/char/hw_random/rockchip-rng.c
++++ b/drivers/char/hw_random/rockchip-rng.c
+@@ -1,12 +1,14 @@
+ // SPDX-License-Identifier: GPL-2.0
+ /*
+- * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC
++ * rockchip-rng.c True Random Number Generator driver for Rockchip SoCs
+ *
+ * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022, Aurelien Jarno
++ * Copyright (c) 2025, Collabora Ltd.
+ * Authors:
+ * Lin Jinhan <troy.lin@rock-chips.com>
+ * Aurelien Jarno <aurelien@aurel32.net>
++ * Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+ */
+ #include <linux/clk.h>
+ #include <linux/hw_random.h>
+@@ -32,6 +34,9 @@
+ */
+ #define RK_RNG_SAMPLE_CNT 1000
+
++/* after how many bytes of output TRNGv1 implementations should be reseeded */
++#define RK_TRNG_V1_AUTO_RESEED_CNT 16000
++
+ /* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */
+ #define TRNG_RST_CTL 0x0004
+ #define TRNG_RNG_CTL 0x0400
+@@ -49,25 +54,85 @@
+ #define TRNG_RNG_SAMPLE_CNT 0x0404
+ #define TRNG_RNG_DOUT 0x0410
+
++/*
++ * TRNG V1 register definitions
++ * The TRNG V1 IP is a stand-alone TRNG implementation (not part of a crypto IP)
++ * and can be found in the Rockchip RK3588 SoC
++ */
++#define TRNG_V1_CTRL 0x0000
++#define TRNG_V1_CTRL_NOP 0x00
++#define TRNG_V1_CTRL_RAND 0x01
++#define TRNG_V1_CTRL_SEED 0x02
++
++#define TRNG_V1_STAT 0x0004
++#define TRNG_V1_STAT_SEEDED BIT(9)
++#define TRNG_V1_STAT_GENERATING BIT(30)
++#define TRNG_V1_STAT_RESEEDING BIT(31)
++
++#define TRNG_V1_MODE 0x0008
++#define TRNG_V1_MODE_128_BIT (0x00 << 3)
++#define TRNG_V1_MODE_256_BIT (0x01 << 3)
++
++/* Interrupt Enable register; unused because polling is faster */
++#define TRNG_V1_IE 0x0010
++#define TRNG_V1_IE_GLBL_EN BIT(31)
++#define TRNG_V1_IE_SEED_DONE_EN BIT(1)
++#define TRNG_V1_IE_RAND_RDY_EN BIT(0)
++
++#define TRNG_V1_ISTAT 0x0014
++#define TRNG_V1_ISTAT_RAND_RDY BIT(0)
++
++/* RAND0 ~ RAND7 */
++#define TRNG_V1_RAND0 0x0020
++#define TRNG_V1_RAND7 0x003C
++
++/* Auto Reseed Register */
++#define TRNG_V1_AUTO_RQSTS 0x0060
++
++#define TRNG_V1_VERSION 0x00F0
++#define TRNG_v1_VERSION_CODE 0x46bc
++/* end of TRNG_V1 register definitions */
++
++/* Before removing this assert, give rk3588_rng_read an upper bound of 32 */
++static_assert(RK_RNG_MAX_BYTE <= (TRNG_V1_RAND7 + 4 - TRNG_V1_RAND0),
++ "You raised RK_RNG_MAX_BYTE and broke rk3588-rng, congrats.");
++
+ struct rk_rng {
+ struct hwrng rng;
+ void __iomem *base;
+ int clk_num;
+ struct clk_bulk_data *clk_bulks;
++ const struct rk_rng_soc_data *soc_data;
+ struct device *dev;
+ };
+
++struct rk_rng_soc_data {
++ int (*rk_rng_init)(struct hwrng *rng);
++ int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
++ void (*rk_rng_cleanup)(struct hwrng *rng);
++ unsigned short quality;
++ bool reset_optional;
++};
++
+ /* The mask in the upper 16 bits determines the bits that are updated */
+ static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask)
+ {
+ writel((mask << 16) | val, rng->base + TRNG_RNG_CTL);
+ }
+
+-static int rk_rng_init(struct hwrng *rng)
++static inline void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
+ {
+- struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+- int ret;
++ writel(val, rng->base + offset);
++}
+
++static inline u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
++{
++ return readl(rng->base + offset);
++}
++
++static int rk_rng_enable_clks(struct rk_rng *rk_rng)
++{
++ int ret;
+ /* start clocks */
+ ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
+ if (ret < 0) {
+@@ -75,6 +140,18 @@ static int rk_rng_init(struct hwrng *rng
+ return ret;
+ }
+
++ return 0;
++}
++
++static int rk3568_rng_init(struct hwrng *rng)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++ int ret;
++
++ ret = rk_rng_enable_clks(rk_rng);
++ if (ret < 0)
++ return ret;
++
+ /* set the sample period */
+ writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT);
+
+@@ -87,7 +164,7 @@ static int rk_rng_init(struct hwrng *rng
+ return 0;
+ }
+
+-static void rk_rng_cleanup(struct hwrng *rng)
++static void rk3568_rng_cleanup(struct hwrng *rng)
+ {
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+
+@@ -98,7 +175,7 @@ static void rk_rng_cleanup(struct hwrng
+ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
+ }
+
+-static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++static int rk3568_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+ {
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+ size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE);
+@@ -128,6 +205,114 @@ out:
+ return (ret < 0) ? ret : to_read;
+ }
+
++static int rk3588_rng_init(struct hwrng *rng)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++ u32 version, status, mask, istat;
++ int ret;
++
++ ret = rk_rng_enable_clks(rk_rng);
++ if (ret < 0)
++ return ret;
++
++ version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
++ if (version != TRNG_v1_VERSION_CODE) {
++ dev_err(rk_rng->dev,
++ "wrong trng version, expected = %08x, actual = %08x\n",
++ TRNG_V1_VERSION, version);
++ ret = -EFAULT;
++ goto err_disable_clk;
++ }
++
++ mask = TRNG_V1_STAT_SEEDED | TRNG_V1_STAT_GENERATING |
++ TRNG_V1_STAT_RESEEDING;
++ if (readl_poll_timeout(rk_rng->base + TRNG_V1_STAT, status,
++ (status & mask) == TRNG_V1_STAT_SEEDED,
++ RK_RNG_POLL_PERIOD_US, RK_RNG_POLL_TIMEOUT_US) < 0) {
++ dev_err(rk_rng->dev, "timed out waiting for hwrng to reseed\n");
++ ret = -ETIMEDOUT;
++ goto err_disable_clk;
++ }
++
++ /*
++ * clear ISTAT flag, downstream advises to do this to avoid
++ * auto-reseeding "on power on"
++ */
++ istat = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
++ rk_rng_writel(rk_rng, istat, TRNG_V1_ISTAT);
++
++ /* auto reseed after RK_TRNG_V1_AUTO_RESEED_CNT bytes */
++ rk_rng_writel(rk_rng, RK_TRNG_V1_AUTO_RESEED_CNT / 16, TRNG_V1_AUTO_RQSTS);
++
++ return 0;
++err_disable_clk:
++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
++ return ret;
++}
++
++static void rk3588_rng_cleanup(struct hwrng *rng)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++ clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
++}
++
++static int rk3588_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++ size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE);
++ int ret = 0;
++ u32 reg;
++
++ ret = pm_runtime_resume_and_get(rk_rng->dev);
++ if (ret < 0)
++ return ret;
++
++ /* Clear ISTAT, even without interrupts enabled, this will be updated */
++ reg = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
++ rk_rng_writel(rk_rng, reg, TRNG_V1_ISTAT);
++
++ /* generate 256 bits of random data */
++ rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
++ rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
++
++ ret = readl_poll_timeout_atomic(rk_rng->base + TRNG_V1_ISTAT, reg,
++ (reg & TRNG_V1_ISTAT_RAND_RDY), 0,
++ RK_RNG_POLL_TIMEOUT_US);
++ if (ret < 0)
++ goto out;
++
++ /* Read random data that's in registers TRNG_V1_RAND0 through RAND7 */
++ memcpy_fromio(buf, rk_rng->base + TRNG_V1_RAND0, to_read);
++
++out:
++ /* Clear ISTAT */
++ rk_rng_writel(rk_rng, reg, TRNG_V1_ISTAT);
++ /* close the TRNG */
++ rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
++
++ pm_runtime_mark_last_busy(rk_rng->dev);
++ pm_runtime_put_sync_autosuspend(rk_rng->dev);
++
++ return (ret < 0) ? ret : to_read;
++}
++
++static const struct rk_rng_soc_data rk3568_soc_data = {
++ .rk_rng_init = rk3568_rng_init,
++ .rk_rng_read = rk3568_rng_read,
++ .rk_rng_cleanup = rk3568_rng_cleanup,
++ .quality = 900,
++ .reset_optional = false,
++};
++
++static const struct rk_rng_soc_data rk3588_soc_data = {
++ .rk_rng_init = rk3588_rng_init,
++ .rk_rng_read = rk3588_rng_read,
++ .rk_rng_cleanup = rk3588_rng_cleanup,
++ .quality = 999, /* as determined by actual testing */
++ .reset_optional = true,
++};
++
+ static int rk_rng_probe(struct platform_device *pdev)
+ {
+ struct device *dev = &pdev->dev;
+@@ -139,6 +324,7 @@ static int rk_rng_probe(struct platform_
+ if (!rk_rng)
+ return -ENOMEM;
+
++ rk_rng->soc_data = of_device_get_match_data(dev);
+ rk_rng->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rk_rng->base))
+ return PTR_ERR(rk_rng->base);
+@@ -148,24 +334,30 @@ static int rk_rng_probe(struct platform_
+ return dev_err_probe(dev, rk_rng->clk_num,
+ "Failed to get clks property\n");
+
+- rst = devm_reset_control_array_get_exclusive(dev);
+- if (IS_ERR(rst))
+- return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset property\n");
+-
+- reset_control_assert(rst);
+- udelay(2);
+- reset_control_deassert(rst);
++ if (rk_rng->soc_data->reset_optional)
++ rst = devm_reset_control_array_get_optional_exclusive(dev);
++ else
++ rst = devm_reset_control_array_get_exclusive(dev);
++
++ if (rst) {
++ if (IS_ERR(rst))
++ return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset property\n");
++
++ reset_control_assert(rst);
++ udelay(2);
++ reset_control_deassert(rst);
++ }
+
+ platform_set_drvdata(pdev, rk_rng);
+
+ rk_rng->rng.name = dev_driver_string(dev);
+ if (!IS_ENABLED(CONFIG_PM)) {
+- rk_rng->rng.init = rk_rng_init;
+- rk_rng->rng.cleanup = rk_rng_cleanup;
++ rk_rng->rng.init = rk_rng->soc_data->rk_rng_init;
++ rk_rng->rng.cleanup = rk_rng->soc_data->rk_rng_cleanup;
+ }
+- rk_rng->rng.read = rk_rng_read;
++ rk_rng->rng.read = rk_rng->soc_data->rk_rng_read;
+ rk_rng->dev = dev;
+- rk_rng->rng.quality = 900;
++ rk_rng->rng.quality = rk_rng->soc_data->quality;
+
+ pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY);
+ pm_runtime_use_autosuspend(dev);
+@@ -184,7 +376,7 @@ static int __maybe_unused rk_rng_runtime
+ {
+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
+
+- rk_rng_cleanup(&rk_rng->rng);
++ rk_rng->soc_data->rk_rng_cleanup(&rk_rng->rng);
+
+ return 0;
+ }
+@@ -193,7 +385,7 @@ static int __maybe_unused rk_rng_runtime
+ {
+ struct rk_rng *rk_rng = dev_get_drvdata(dev);
+
+- return rk_rng_init(&rk_rng->rng);
++ return rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
+ }
+
+ static const struct dev_pm_ops rk_rng_pm_ops = {
+@@ -204,7 +396,8 @@ static const struct dev_pm_ops rk_rng_pm
+ };
+
+ static const struct of_device_id rk_rng_dt_match[] = {
+- { .compatible = "rockchip,rk3568-rng", },
++ { .compatible = "rockchip,rk3568-rng", .data = (void *)&rk3568_soc_data },
++ { .compatible = "rockchip,rk3588-rng", .data = (void *)&rk3588_soc_data },
+ { /* sentinel */ },
+ };
+
+@@ -221,8 +414,9 @@ static struct platform_driver rk_rng_dri
+
+ module_platform_driver(rk_rng_driver);
+
+-MODULE_DESCRIPTION("Rockchip RK3568 True Random Number Generator driver");
++MODULE_DESCRIPTION("Rockchip True Random Number Generator driver");
+ MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
+ MODULE_AUTHOR("Aurelien Jarno <aurelien@aurel32.net>");
+ MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_AUTHOR("Nicolas Frattaroli <nicolas.frattaroli@collabora.com>");
+ MODULE_LICENSE("GPL");
--- /dev/null
+From 8f66ccbd8f67ab41b29f54f383f8a8516be7696c Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Wed, 30 Apr 2025 18:16:35 +0200
+Subject: [PATCH] hwrng: rockchip - add support for RK3576's RNG
+
+The Rockchip RK3576 SoC uses a new hardware random number generator IP.
+It's also used on the Rockchip RK3562 and the Rockchip RK3528.
+
+It has several modes of operation and self-checking features that are
+not implemented here. For starters, it has a DRNG output, which is an
+AES-CTR pseudo-random number generator that can be reseeded from the
+true entropy regularly.
+
+However, it also allows for access of the true entropy generator
+directly. This entropy is generated from an oscillator.
+
+There are several configuration registers which we don't touch here. The
+oscillator can be switched between a "CRO" and "STR" oscillator, and the
+length of the oscillator can be configured.
+
+The hardware also supports some automatic continuous entropy quality
+checking, which is also not implemented in this driver for the time
+being.
+
+The output as-is has been deemed sufficient to be useful:
+
+ rngtest: starting FIPS tests...
+ rngtest: bits received from input: 20000032
+ rngtest: FIPS 140-2 successes: 997
+ rngtest: FIPS 140-2 failures: 3
+ rngtest: FIPS 140-2(2001-10-10) Monobit: 0
+ rngtest: FIPS 140-2(2001-10-10) Poker: 1
+ rngtest: FIPS 140-2(2001-10-10) Runs: 1
+ rngtest: FIPS 140-2(2001-10-10) Long run: 1
+ rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
+ rngtest: input channel speed: (min=17.050; avg=1897.272;
+ max=19531250.000)Kibits/s
+ rngtest: FIPS tests speed: (min=44.773; avg=71.179; max=96.820)Mibits/s
+ rngtest: Program run time: 11760715 microseconds
+ rngtest: bits received from input: 40000032
+ rngtest: FIPS 140-2 successes: 1997
+ rngtest: FIPS 140-2 failures: 3
+ rngtest: FIPS 140-2(2001-10-10) Monobit: 0
+ rngtest: FIPS 140-2(2001-10-10) Poker: 1
+ rngtest: FIPS 140-2(2001-10-10) Runs: 1
+ rngtest: FIPS 140-2(2001-10-10) Long run: 1
+ rngtest: FIPS 140-2(2001-10-10) Continuous run: 0
+ rngtest: input channel speed: (min=17.050; avg=1798.618;
+ max=19531250.000)Kibits/s
+ rngtest: FIPS tests speed: (min=44.773; avg=64.561; max=96.820)Mibits/s
+ rngtest: Program run time: 23507723 microseconds
+
+Stretching the entropy can then be left up to Linux's actual entropy
+pool.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
+---
+ drivers/char/hw_random/rockchip-rng.c | 73 +++++++++++++++++++++++++++
+ 1 file changed, 73 insertions(+)
+
+--- a/drivers/char/hw_random/rockchip-rng.c
++++ b/drivers/char/hw_random/rockchip-rng.c
+@@ -93,6 +93,30 @@
+ #define TRNG_v1_VERSION_CODE 0x46bc
+ /* end of TRNG_V1 register definitions */
+
++/*
++ * RKRNG register definitions
++ * The RKRNG IP is a stand-alone TRNG implementation (not part of a crypto IP)
++ * and can be found in the Rockchip RK3576, Rockchip RK3562 and Rockchip RK3528
++ * SoCs. It can either output true randomness (TRNG) or "deterministic"
++ * randomness derived from hashing the true entropy (DRNG). This driver
++ * implementation uses just the true entropy, and leaves stretching the entropy
++ * up to Linux.
++ */
++#define RKRNG_CFG 0x0000
++#define RKRNG_CTRL 0x0010
++#define RKRNG_CTRL_REQ_TRNG BIT(4)
++#define RKRNG_STATE 0x0014
++#define RKRNG_STATE_TRNG_RDY BIT(4)
++#define RKRNG_TRNG_DATA0 0x0050
++#define RKRNG_TRNG_DATA1 0x0054
++#define RKRNG_TRNG_DATA2 0x0058
++#define RKRNG_TRNG_DATA3 0x005C
++#define RKRNG_TRNG_DATA4 0x0060
++#define RKRNG_TRNG_DATA5 0x0064
++#define RKRNG_TRNG_DATA6 0x0068
++#define RKRNG_TRNG_DATA7 0x006C
++#define RKRNG_READ_LEN 32
++
+ /* Before removing this assert, give rk3588_rng_read an upper bound of 32 */
+ static_assert(RK_RNG_MAX_BYTE <= (TRNG_V1_RAND7 + 4 - TRNG_V1_RAND0),
+ "You raised RK_RNG_MAX_BYTE and broke rk3588-rng, congrats.");
+@@ -205,6 +229,46 @@ out:
+ return (ret < 0) ? ret : to_read;
+ }
+
++static int rk3576_rng_init(struct hwrng *rng)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++
++ return rk_rng_enable_clks(rk_rng);
++}
++
++static int rk3576_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
++{
++ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
++ size_t to_read = min_t(size_t, max, RKRNG_READ_LEN);
++ int ret = 0;
++ u32 val;
++
++ ret = pm_runtime_resume_and_get(rk_rng->dev);
++ if (ret < 0)
++ return ret;
++
++ rk_rng_writel(rk_rng, RKRNG_CTRL_REQ_TRNG | (RKRNG_CTRL_REQ_TRNG << 16),
++ RKRNG_CTRL);
++
++ if (readl_poll_timeout(rk_rng->base + RKRNG_STATE, val,
++ (val & RKRNG_STATE_TRNG_RDY), RK_RNG_POLL_PERIOD_US,
++ RK_RNG_POLL_TIMEOUT_US)) {
++ dev_err(rk_rng->dev, "timed out waiting for data\n");
++ ret = -ETIMEDOUT;
++ goto out;
++ }
++
++ rk_rng_writel(rk_rng, RKRNG_STATE_TRNG_RDY, RKRNG_STATE);
++
++ memcpy_fromio(buf, rk_rng->base + RKRNG_TRNG_DATA0, to_read);
++
++out:
++ pm_runtime_mark_last_busy(rk_rng->dev);
++ pm_runtime_put_sync_autosuspend(rk_rng->dev);
++
++ return (ret < 0) ? ret : to_read;
++}
++
+ static int rk3588_rng_init(struct hwrng *rng)
+ {
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+@@ -305,6 +369,14 @@ static const struct rk_rng_soc_data rk35
+ .reset_optional = false,
+ };
+
++static const struct rk_rng_soc_data rk3576_soc_data = {
++ .rk_rng_init = rk3576_rng_init,
++ .rk_rng_read = rk3576_rng_read,
++ .rk_rng_cleanup = rk3588_rng_cleanup,
++ .quality = 999, /* as determined by actual testing */
++ .reset_optional = true,
++};
++
+ static const struct rk_rng_soc_data rk3588_soc_data = {
+ .rk_rng_init = rk3588_rng_init,
+ .rk_rng_read = rk3588_rng_read,
+@@ -397,6 +469,7 @@ static const struct dev_pm_ops rk_rng_pm
+
+ static const struct of_device_id rk_rng_dt_match[] = {
+ { .compatible = "rockchip,rk3568-rng", .data = (void *)&rk3568_soc_data },
++ { .compatible = "rockchip,rk3576-rng", .data = (void *)&rk3576_soc_data },
+ { .compatible = "rockchip,rk3588-rng", .data = (void *)&rk3588_soc_data },
+ { /* sentinel */ },
+ };
--- /dev/null
+From 9e89f02da718bc912f7f253b58804d4a52efed30 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 11 Dec 2024 17:58:50 +0100
+Subject: [PATCH] clk: rockchip: support clocks registered late
+
+When some clocks are registered late and some clocks are registered
+early we need to make sure the late registered clocks report probe defer
+until the final registration has happened.
+
+But we do not want to keep reporting probe defer after the late
+registration has happened. Also not all Rockchip SoCs have late
+registered clocks and may not need to report probe defer at all.
+
+This restructures code a bit, so that there is a new function
+rockchip_clk_init_early(), which should be used for initializing the CRU
+structure on SoCs making use of late initialization in addition to the
+early init. These platforms should call rockchip_clk_finalize()
+once all clocks have been registered.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+[added EXPORT_SYMBOL_GPL(rockchip_clk_finalize) to match the early function]
+Link: https://lore.kernel.org/r/20241211165957.94922-2-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk.c | 36 ++++++++++++++++++++++++++++++++----
+ drivers/clk/rockchip/clk.h | 3 +++
+ 2 files changed, 35 insertions(+), 4 deletions(-)
+
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -359,14 +359,17 @@ static struct clk *rockchip_clk_register
+ return hw->clk;
+ }
+
+-struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+- void __iomem *base,
+- unsigned long nr_clks)
++static struct rockchip_clk_provider *rockchip_clk_init_base(
++ struct device_node *np, void __iomem *base,
++ unsigned long nr_clks, bool has_late_clocks)
+ {
+ struct rockchip_clk_provider *ctx;
+ struct clk **clk_table;
++ struct clk *default_clk_val;
+ int i;
+
++ default_clk_val = ERR_PTR(has_late_clocks ? -EPROBE_DEFER : -ENOENT);
++
+ ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
+ if (!ctx)
+ return ERR_PTR(-ENOMEM);
+@@ -376,7 +379,7 @@ struct rockchip_clk_provider *rockchip_c
+ goto err_free;
+
+ for (i = 0; i < nr_clks; ++i)
+- clk_table[i] = ERR_PTR(-ENOENT);
++ clk_table[i] = default_clk_val;
+
+ ctx->reg_base = base;
+ ctx->clk_data.clks = clk_table;
+@@ -393,8 +396,33 @@ err_free:
+ kfree(ctx);
+ return ERR_PTR(-ENOMEM);
+ }
++
++struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
++ void __iomem *base,
++ unsigned long nr_clks)
++{
++ return rockchip_clk_init_base(np, base, nr_clks, false);
++}
+ EXPORT_SYMBOL_GPL(rockchip_clk_init);
+
++struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
++ void __iomem *base,
++ unsigned long nr_clks)
++{
++ return rockchip_clk_init_base(np, base, nr_clks, true);
++}
++EXPORT_SYMBOL_GPL(rockchip_clk_init_early);
++
++void rockchip_clk_finalize(struct rockchip_clk_provider *ctx)
++{
++ int i;
++
++ for (i = 0; i < ctx->clk_data.clk_num; ++i)
++ if (ctx->clk_data.clks[i] == ERR_PTR(-EPROBE_DEFER))
++ ctx->clk_data.clks[i] = ERR_PTR(-ENOENT);
++}
++EXPORT_SYMBOL_GPL(rockchip_clk_finalize);
++
+ void rockchip_clk_of_add_provider(struct device_node *np,
+ struct rockchip_clk_provider *ctx)
+ {
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -1024,6 +1024,9 @@ struct rockchip_clk_branch {
+
+ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+ void __iomem *base, unsigned long nr_clks);
++struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
++ void __iomem *base, unsigned long nr_clks);
++void rockchip_clk_finalize(struct rockchip_clk_provider *ctx);
+ void rockchip_clk_of_add_provider(struct device_node *np,
+ struct rockchip_clk_provider *ctx);
+ unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
--- /dev/null
+From 33af96244a66f855baa43d424844bb437c79c30c Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 11 Dec 2024 17:58:51 +0100
+Subject: [PATCH] clk: rockchip: rk3588: register GATE_LINK later
+
+The proper GATE_LINK implementation will use runtime PM to handle the
+linked gate clocks, which requires device context. Currently all clocks
+are registered early via CLK_OF_DECLARE, which is before the kernel
+knows about devices.
+
+Moving the full clocks registration to the probe routine does not work,
+since the clocks needed for timers must be registered early.
+
+To work around this issue, most of the clock tree is registered early,
+but GATE_LINK clocks are handled in the probe routine. Since the resets
+are not needed early either, they have also been moved to the probe
+routine.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20241211165957.94922-3-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3588.c | 66 +++++++++++++++++++++++++++----
+ 1 file changed, 58 insertions(+), 8 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-rk3588.c
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -266,6 +266,8 @@ static struct rockchip_pll_rate_table rk
+ }, \
+ }
+
++static struct rockchip_clk_provider *early_ctx;
++
+ static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = {
+ RK3588_CPUB01CLK_RATE(2496000000, 1),
+ RK3588_CPUB01CLK_RATE(2400000000, 1),
+@@ -694,7 +696,7 @@ static struct rockchip_pll_clock rk3588_
+ RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
+ };
+
+-static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
++static struct rockchip_clk_branch rk3588_early_clk_branches[] __initdata = {
+ /*
+ * CRU Clock-Architecture
+ */
+@@ -2428,7 +2430,9 @@ static struct rockchip_clk_branch rk3588
+ RK3588_CLKGATE_CON(68), 5, GFLAGS),
+ GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
+ RK3588_CLKGATE_CON(68), 2, GFLAGS),
++};
+
++static struct rockchip_clk_branch rk3588_clk_branches[] = {
+ GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
+ GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
+@@ -2453,26 +2457,31 @@ static struct rockchip_clk_branch rk3588
+ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
+ };
+
+-static void __init rk3588_clk_init(struct device_node *np)
++static void __init rk3588_clk_early_init(struct device_node *np)
+ {
+ struct rockchip_clk_provider *ctx;
+- unsigned long clk_nr_clks;
++ unsigned long clk_nr_clks, max_clk_id1, max_clk_id2;
+ void __iomem *reg_base;
+
+- clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches,
+- ARRAY_SIZE(rk3588_clk_branches)) + 1;
++ max_clk_id1 = rockchip_clk_find_max_clk_id(rk3588_clk_branches,
++ ARRAY_SIZE(rk3588_clk_branches));
++ max_clk_id2 = rockchip_clk_find_max_clk_id(rk3588_early_clk_branches,
++ ARRAY_SIZE(rk3588_early_clk_branches));
++ clk_nr_clks = max(max_clk_id1, max_clk_id2) + 1;
++
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+- ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
++ ctx = rockchip_clk_init_early(np, reg_base, clk_nr_clks);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+ iounmap(reg_base);
+ return;
+ }
++ early_ctx = ctx;
+
+ rockchip_clk_register_plls(ctx, rk3588_pll_clks,
+ ARRAY_SIZE(rk3588_pll_clks),
+@@ -2491,14 +2500,55 @@ static void __init rk3588_clk_init(struc
+ &rk3588_cpub1clk_data, rk3588_cpub1clk_rates,
+ ARRAY_SIZE(rk3588_cpub1clk_rates));
+
++ rockchip_clk_register_branches(ctx, rk3588_early_clk_branches,
++ ARRAY_SIZE(rk3588_early_clk_branches));
++
++ rockchip_clk_of_add_provider(np, ctx);
++}
++CLK_OF_DECLARE_DRIVER(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_early_init);
++
++static int clk_rk3588_probe(struct platform_device *pdev)
++{
++ struct rockchip_clk_provider *ctx = early_ctx;
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++
+ rockchip_clk_register_branches(ctx, rk3588_clk_branches,
+ ARRAY_SIZE(rk3588_clk_branches));
+
+- rk3588_rst_init(np, reg_base);
++ rockchip_clk_finalize(ctx);
+
++ rk3588_rst_init(np, ctx->reg_base);
+ rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL);
+
++ /*
++ * Re-add clock provider, so that the newly added clocks are also
++ * re-parented and get their defaults configured.
++ */
++ of_clk_del_provider(np);
+ rockchip_clk_of_add_provider(np, ctx);
++
++ return 0;
+ }
+
+-CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
++static const struct of_device_id clk_rk3588_match_table[] = {
++ {
++ .compatible = "rockchip,rk3588-cru",
++ },
++ { }
++};
++
++static struct platform_driver clk_rk3588_driver = {
++ .probe = clk_rk3588_probe,
++ .driver = {
++ .name = "clk-rk3588",
++ .of_match_table = clk_rk3588_match_table,
++ .suppress_bind_attrs = true,
++ },
++};
++
++static int __init rockchip_clk_rk3588_drv_register(void)
++{
++ return platform_driver_register(&clk_rk3588_driver);
++}
++core_initcall(rockchip_clk_rk3588_drv_register);
--- /dev/null
+From fe0fb6675fa48cade97d8bcd46226479c4a704df Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 11 Dec 2024 17:58:52 +0100
+Subject: [PATCH] clk: rockchip: expose rockchip_clk_set_lookup
+
+Move rockchip_clk_add_lookup to clk.h, so that it can be used
+by sub-devices with their own driver. These might also have to
+do a lookup, so rename the function to rockchip_clk_set_lookup
+and add a matching rockchip_clk_get_lookup.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20241211165957.94922-4-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk.c | 14 ++++----------
+ drivers/clk/rockchip/clk.h | 12 ++++++++++++
+ 2 files changed, 16 insertions(+), 10 deletions(-)
+
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -197,12 +197,6 @@ static void rockchip_fractional_approxim
+ clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n);
+ }
+
+-static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
+- struct clk *clk, unsigned int id)
+-{
+- ctx->clk_data.clks[id] = clk;
+-}
+-
+ static struct clk *rockchip_clk_register_frac_branch(
+ struct rockchip_clk_provider *ctx, const char *name,
+ const char *const *parent_names, u8 num_parents,
+@@ -292,7 +286,7 @@ static struct clk *rockchip_clk_register
+ return mux_clk;
+ }
+
+- rockchip_clk_add_lookup(ctx, mux_clk, child->id);
++ rockchip_clk_set_lookup(ctx, mux_clk, child->id);
+
+ /* notifier on the fraction divider to catch rate changes */
+ if (frac->mux_frac_idx >= 0) {
+@@ -452,7 +446,7 @@ void rockchip_clk_register_plls(struct r
+ continue;
+ }
+
+- rockchip_clk_add_lookup(ctx, clk, list->id);
++ rockchip_clk_set_lookup(ctx, clk, list->id);
+ }
+ }
+ EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
+@@ -614,7 +608,7 @@ void rockchip_clk_register_branches(stru
+ continue;
+ }
+
+- rockchip_clk_add_lookup(ctx, clk, list->id);
++ rockchip_clk_set_lookup(ctx, clk, list->id);
+ }
+ }
+ EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
+@@ -638,7 +632,7 @@ void rockchip_clk_register_armclk(struct
+ return;
+ }
+
+- rockchip_clk_add_lookup(ctx, clk, lookup_id);
++ rockchip_clk_set_lookup(ctx, clk, lookup_id);
+ }
+ EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
+
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -1022,6 +1022,18 @@ struct rockchip_clk_branch {
+ #define SGRF_GATE(_id, cname, pname) \
+ FACTOR(_id, cname, pname, 0, 1, 1)
+
++static inline struct clk *rockchip_clk_get_lookup(struct rockchip_clk_provider *ctx,
++ unsigned int id)
++{
++ return ctx->clk_data.clks[id];
++}
++
++static inline void rockchip_clk_set_lookup(struct rockchip_clk_provider *ctx,
++ struct clk *clk, unsigned int id)
++{
++ ctx->clk_data.clks[id] = clk;
++}
++
+ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+ void __iomem *base, unsigned long nr_clks);
+ struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
--- /dev/null
+From c62fa612cfa66ab58ab215e5afc95c43c613b513 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 11 Dec 2024 17:58:53 +0100
+Subject: [PATCH] clk: rockchip: implement linked gate clock support
+
+Recent Rockchip SoCs have a new hardware block called Native Interface
+Unit (NIU), which gates clocks to devices behind them. These clock
+gates will only have a running output clock when all of the following
+conditions are met:
+
+1. the parent clock is enabled
+2. the enable bit is set correctly
+3. the linked clock is enabled
+
+To handle them this code registers them as a normal gate type clock,
+which takes care of condition 1 + 2. The linked clock is handled by
+using runtime PM clocks. Handling it via runtime PM requires setting
+up a struct device for each of these clocks with a driver attached
+to use the correct runtime PM operations. Thus the complete handling
+of these clocks has been moved into its own driver.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20241211165957.94922-5-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/Makefile | 1 +
+ drivers/clk/rockchip/clk-rk3588.c | 23 +--------
+ drivers/clk/rockchip/clk.c | 52 +++++++++++++++++++
+ drivers/clk/rockchip/clk.h | 25 +++++++++
+ drivers/clk/rockchip/gate-link.c | 85 +++++++++++++++++++++++++++++++
+ 5 files changed, 165 insertions(+), 21 deletions(-)
+ create mode 100644 drivers/clk/rockchip/gate-link.c
+
+--- a/drivers/clk/rockchip/Makefile
++++ b/drivers/clk/rockchip/Makefile
+@@ -13,6 +13,7 @@ clk-rockchip-y += clk-inverter.o
+ clk-rockchip-y += clk-mmc-phase.o
+ clk-rockchip-y += clk-muxgrf.o
+ clk-rockchip-y += clk-ddr.o
++clk-rockchip-y += gate-link.o
+ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
+
+ obj-$(CONFIG_CLK_PX30) += clk-px30.o
+--- a/drivers/clk/rockchip/clk-rk3588.c
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -12,25 +12,6 @@
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include "clk.h"
+
+-/*
+- * Recent Rockchip SoCs have a new hardware block called Native Interface
+- * Unit (NIU), which gates clocks to devices behind them. These effectively
+- * need two parent clocks.
+- *
+- * Downstream enables the linked clock via runtime PM whenever the gate is
+- * enabled. This implementation uses separate clock nodes for each of the
+- * linked gate clocks, which leaks parts of the clock tree into DT.
+- *
+- * The GATE_LINK macro instead takes the second parent via 'linkname', but
+- * ignores the information. Once the clock framework is ready to handle it, the
+- * information should be passed on here. But since these clocks are required to
+- * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
+- * clocks critical until a better solution is available. This will waste some
+- * power, but avoids leaking implementation details into DT or hanging the
+- * system.
+- */
+-#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
+- GATE(_id, cname, pname, f, o, b, gf)
+ #define RK3588_LINKED_CLK CLK_IS_CRITICAL
+
+
+@@ -2513,8 +2494,8 @@ static int clk_rk3588_probe(struct platf
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+
+- rockchip_clk_register_branches(ctx, rk3588_clk_branches,
+- ARRAY_SIZE(rk3588_clk_branches));
++ rockchip_clk_register_late_branches(dev, ctx, rk3588_clk_branches,
++ ARRAY_SIZE(rk3588_clk_branches));
+
+ rockchip_clk_finalize(ctx);
+
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -19,6 +19,7 @@
+ #include <linux/clk-provider.h>
+ #include <linux/io.h>
+ #include <linux/mfd/syscon.h>
++#include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ #include <linux/reboot.h>
+
+@@ -468,6 +469,29 @@ unsigned long rockchip_clk_find_max_clk_
+ }
+ EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id);
+
++static struct platform_device *rockchip_clk_register_gate_link(
++ struct device *parent_dev,
++ struct rockchip_clk_provider *ctx,
++ struct rockchip_clk_branch *clkbr)
++{
++ struct rockchip_gate_link_platdata gate_link_pdata = {
++ .ctx = ctx,
++ .clkbr = clkbr,
++ };
++
++ struct platform_device_info pdevinfo = {
++ .parent = parent_dev,
++ .name = "rockchip-gate-link-clk",
++ .id = clkbr->id,
++ .fwnode = dev_fwnode(parent_dev),
++ .of_node_reused = true,
++ .data = &gate_link_pdata,
++ .size_data = sizeof(gate_link_pdata),
++ };
++
++ return platform_device_register_full(&pdevinfo);
++}
++
+ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk)
+@@ -593,6 +617,9 @@ void rockchip_clk_register_branches(stru
+ list->div_width, list->div_flags,
+ ctx->reg_base, &ctx->lock);
+ break;
++ case branch_linked_gate:
++ /* must be registered late, fall-through for error message */
++ break;
+ }
+
+ /* none of the cases above matched */
+@@ -613,6 +640,31 @@ void rockchip_clk_register_branches(stru
+ }
+ EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
+
++void rockchip_clk_register_late_branches(struct device *dev,
++ struct rockchip_clk_provider *ctx,
++ struct rockchip_clk_branch *list,
++ unsigned int nr_clk)
++{
++ unsigned int idx;
++
++ for (idx = 0; idx < nr_clk; idx++, list++) {
++ struct platform_device *pdev = NULL;
++
++ switch (list->branch_type) {
++ case branch_linked_gate:
++ pdev = rockchip_clk_register_gate_link(dev, ctx, list);
++ break;
++ default:
++ dev_err(dev, "unknown clock type %d\n", list->branch_type);
++ break;
++ }
++
++ if (!pdev)
++ dev_err(dev, "failed to register device for clock %s\n", list->name);
++ }
++}
++EXPORT_SYMBOL_GPL(rockchip_clk_register_late_branches);
++
+ void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
+ unsigned int lookup_id,
+ const char *name, const char *const *parent_names,
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -570,6 +570,7 @@ enum rockchip_clk_branch_type {
+ branch_divider,
+ branch_fraction_divider,
+ branch_gate,
++ branch_linked_gate,
+ branch_mmc,
+ branch_inverter,
+ branch_factor,
+@@ -597,6 +598,7 @@ struct rockchip_clk_branch {
+ int gate_offset;
+ u8 gate_shift;
+ u8 gate_flags;
++ unsigned int linked_clk_id;
+ struct rockchip_clk_branch *child;
+ };
+
+@@ -895,6 +897,20 @@ struct rockchip_clk_branch {
+ .gate_flags = gf, \
+ }
+
++#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
++ { \
++ .id = _id, \
++ .branch_type = branch_linked_gate, \
++ .name = cname, \
++ .parent_names = (const char *[]){ pname }, \
++ .linked_clk_id = linkedclk, \
++ .num_parents = 1, \
++ .flags = f, \
++ .gate_offset = o, \
++ .gate_shift = b, \
++ .gate_flags = gf, \
++ }
++
+ #define MMC(_id, cname, pname, offset, shift) \
+ { \
+ .id = _id, \
+@@ -1034,6 +1050,11 @@ static inline void rockchip_clk_set_look
+ ctx->clk_data.clks[id] = clk;
+ }
+
++struct rockchip_gate_link_platdata {
++ struct rockchip_clk_provider *ctx;
++ struct rockchip_clk_branch *clkbr;
++};
++
+ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+ void __iomem *base, unsigned long nr_clks);
+ struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
+@@ -1046,6 +1067,10 @@ unsigned long rockchip_clk_find_max_clk_
+ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk);
++void rockchip_clk_register_late_branches(struct device *dev,
++ struct rockchip_clk_provider *ctx,
++ struct rockchip_clk_branch *list,
++ unsigned int nr_clk);
+ void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
+ struct rockchip_pll_clock *pll_list,
+ unsigned int nr_pll, int grf_lock_offset);
+--- /dev/null
++++ b/drivers/clk/rockchip/gate-link.c
+@@ -0,0 +1,85 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2024 Collabora Ltd.
++ * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/platform_device.h>
++#include <linux/pm_clock.h>
++#include <linux/pm_runtime.h>
++#include <linux/property.h>
++#include "clk.h"
++
++static int rk_clk_gate_link_register(struct device *dev,
++ struct rockchip_clk_provider *ctx,
++ struct rockchip_clk_branch *clkbr)
++{
++ unsigned long flags = clkbr->flags | CLK_SET_RATE_PARENT;
++ struct clk *clk;
++
++ clk = clk_register_gate(dev, clkbr->name, clkbr->parent_names[0],
++ flags, ctx->reg_base + clkbr->gate_offset,
++ clkbr->gate_shift, clkbr->gate_flags,
++ &ctx->lock);
++
++ if (IS_ERR(clk))
++ return PTR_ERR(clk);
++
++ rockchip_clk_set_lookup(ctx, clk, clkbr->id);
++ return 0;
++}
++
++static int rk_clk_gate_link_probe(struct platform_device *pdev)
++{
++ struct rockchip_gate_link_platdata *pdata;
++ struct device *dev = &pdev->dev;
++ struct clk *linked_clk;
++ int ret;
++
++ pdata = dev_get_platdata(dev);
++ if (!pdata)
++ return dev_err_probe(dev, -ENODEV, "missing platform data");
++
++ ret = devm_pm_runtime_enable(dev);
++ if (ret)
++ return ret;
++
++ ret = devm_pm_clk_create(dev);
++ if (ret)
++ return ret;
++
++ linked_clk = rockchip_clk_get_lookup(pdata->ctx, pdata->clkbr->linked_clk_id);
++ ret = pm_clk_add_clk(dev, linked_clk);
++ if (ret)
++ return ret;
++
++ ret = rk_clk_gate_link_register(dev, pdata->ctx, pdata->clkbr);
++ if (ret)
++ goto err;
++
++ return 0;
++
++err:
++ pm_clk_remove_clk(dev, linked_clk);
++ return ret;
++}
++
++static const struct dev_pm_ops rk_clk_gate_link_pm_ops = {
++ SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
++};
++
++static struct platform_driver rk_clk_gate_link_driver = {
++ .probe = rk_clk_gate_link_probe,
++ .driver = {
++ .name = "rockchip-gate-link-clk",
++ .pm = &rk_clk_gate_link_pm_ops,
++ .suppress_bind_attrs = true,
++ },
++};
++
++static int __init rk_clk_gate_link_drv_register(void)
++{
++ return platform_driver_register(&rk_clk_gate_link_driver);
++}
++core_initcall(rk_clk_gate_link_drv_register);
--- /dev/null
+From e9cdd7d6cf2a5031a968dc21f4f566101b602150 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 11 Dec 2024 17:58:54 +0100
+Subject: [PATCH] clk: rockchip: rk3588: drop RK3588_LINKED_CLK
+
+With the proper GATE_LINK support, we no longer need to keep the
+linked clocks always on. Thus it's time to drop the CLK_IS_CRITICAL
+flag for them.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20241211165957.94922-6-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3588.c | 27 ++++++++++++---------------
+ 1 file changed, 12 insertions(+), 15 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-rk3588.c
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -12,9 +12,6 @@
+ #include <dt-bindings/clock/rockchip,rk3588-cru.h>
+ #include "clk.h"
+
+-#define RK3588_LINKED_CLK CLK_IS_CRITICAL
+-
+-
+ #define RK3588_GRF_SOC_STATUS0 0x600
+ #define RK3588_PHYREF_ALT_GATE 0xc38
+
+@@ -1439,7 +1436,7 @@ static struct rockchip_clk_branch rk3588
+ COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
+ RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
+ RK3588_CLKGATE_CON(31), 0, GFLAGS),
+- COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK,
++ COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,
+ RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
+ RK3588_CLKGATE_CON(31), 1, GFLAGS),
+ GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
+@@ -1668,13 +1665,13 @@ static struct rockchip_clk_branch rk3588
+ RK3588_CLKGATE_CON(42), 9, GFLAGS),
+
+ /* vdpu */
+- COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK,
++ COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,
+ RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3588_CLKGATE_CON(44), 0, GFLAGS),
+ COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
+ RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
+ RK3588_CLKGATE_CON(44), 1, GFLAGS),
+- COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
++ COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,
+ RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
+ RK3588_CLKGATE_CON(44), 2, GFLAGS),
+ COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
+@@ -1725,9 +1722,9 @@ static struct rockchip_clk_branch rk3588
+ COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
+ RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
+ RK3588_CLKGATE_CON(47), 1, GFLAGS),
+- GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK,
++ GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,
+ RK3588_CLKGATE_CON(47), 4, GFLAGS),
+- GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK,
++ GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,
+ RK3588_CLKGATE_CON(47), 5, GFLAGS),
+ COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
+ RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
+@@ -1737,10 +1734,10 @@ static struct rockchip_clk_branch rk3588
+ RK3588_CLKGATE_CON(48), 6, GFLAGS),
+
+ /* vi */
+- COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK,
++ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,
+ RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RK3588_CLKGATE_CON(49), 0, GFLAGS),
+- COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
++ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,
+ RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
+ RK3588_CLKGATE_CON(49), 1, GFLAGS),
+ COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
+@@ -1910,10 +1907,10 @@ static struct rockchip_clk_branch rk3588
+ COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
+ RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ RK3588_CLKGATE_CON(52), 0, GFLAGS),
+- COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK,
++ COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,
+ RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
+ RK3588_CLKGATE_CON(52), 1, GFLAGS),
+- COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
++ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,
+ RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
+ RK3588_CLKGATE_CON(52), 2, GFLAGS),
+ COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
+@@ -2416,7 +2413,7 @@ static struct rockchip_clk_branch rk3588
+ static struct rockchip_clk_branch rk3588_clk_branches[] = {
+ GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
+ GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
+- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
++ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, 0, RK3588_CLKGATE_CON(31), 2, GFLAGS),
+ GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
+ GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
+ GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
+@@ -2428,9 +2425,9 @@ static struct rockchip_clk_branch rk3588
+ GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
+ GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
+ GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
+- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
++ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
+ GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
+- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
++ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
+ GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
+ GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
+ GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
--- /dev/null
+From cd8b5366636bdff0449b789fb2d33abb20804255 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko.stuebner@cherry.de>
+Date: Sat, 14 Dec 2024 23:48:19 +0100
+Subject: [PATCH] clk: rockchip: rk3588: make refclko25m_ethX critical
+
+Ethernet phys normally need a 25MHz refclk input. On a lot of boards
+this is done with a dedicated 25MHz crystal. But the rk3588 CRU also
+provides a means for that via the refclko25m_ethX clock outputs that
+can be used for that function.
+
+The mdio bus normally probes devices on the bus at runtime, by reading
+specific phy registers. This requires the phy to be running and thus
+also being supplied by its reference clock.
+
+While there exist the possibility and dt-binding to declare these
+input clocks for each phy in the phy-dt-node, this is only relevant
+_after_ the phy has been detected and during the drivers probe-run.
+
+This results in a chicken-and-egg-problem. The refclks in the CRU are
+running on boot of course, but phy-probing can very well happen after
+clk_disable_unused has run.
+
+In the past I tried to make clock-handling part of the mdio bus code [0]
+but that wasn't very well received, due to it being specific to OF and
+clocks with the consensus being that resources needed for detection
+need to be enabled before.
+
+So to make probing ethernet phys using the internal refclks possible,
+make those 2 clocks critical.
+
+[0] https://lore.kernel.org/netdev/13590315.F0gNSz5aLb@diego/T/
+
+Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
+Link: https://lore.kernel.org/r/20241214224820.200665-1-heiko@sntech.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3588.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-rk3588.c
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -772,10 +772,10 @@ static struct rockchip_clk_branch rk3588
+ COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0,
+ RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3588_CLKGATE_CON(5), 3, GFLAGS),
+- COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0,
++ COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS,
+ RK3588_CLKGATE_CON(5), 4, GFLAGS),
+- COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0,
++ COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, CLK_IS_CRITICAL,
+ RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS,
+ RK3588_CLKGATE_CON(5), 5, GFLAGS),
+ COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0,
--- /dev/null
+From 83dbeca33f7422f4a30c8a91a79d6c0dba4fb6af Mon Sep 17 00:00:00 2001
+From: Michael Riesch <michael.riesch@wolfvision.net>
+Date: Mon, 10 Feb 2025 09:29:02 +0100
+Subject: [PATCH] clk: rockchip: rk3568: mark hclk_vi as critical
+
+The clock 'pclk_vi_niu' has a dependency on 'hclk_vi_niu' according
+to the Technical Reference Manual section '2.8.6 NIU Clock gating
+reliance'. However, this kind of dependency cannot be addressed
+properly at the moment (until the support for linked clocks is
+implemented for the RK3568).
+As an intermediate solution, mark the hclk_vi as critical on the
+Rockchip RK3568.
+
+Suggested-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
+Link: https://lore.kernel.org/r/20250210-rk3568-hclk-vi-v1-1-9ade2626f638@wolfvision.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3568.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/clk/rockchip/clk-rk3568.c
++++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -1602,6 +1602,7 @@ static const char *const rk3568_cru_crit
+ "pclk_php",
+ "hclk_usb",
+ "pclk_usb",
++ "hclk_vi",
+ "hclk_vo",
+ };
+
--- /dev/null
+From 831a8ac72264426ccd0ee5d2b0d74491ea7d2bfb Mon Sep 17 00:00:00 2001
+From: Alexander Shiyan <eagle.alexander923@gmail.com>
+Date: Tue, 8 Apr 2025 09:46:12 +0300
+Subject: [PATCH] clk: rockchip: rk3588: Add PLL rate for 1500 MHz
+
+At least one RK3588 clock (CPLL) uses 1.5 GHz, so let's add
+that frequency to the PLL table.
+
+Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
+Link: https://lore.kernel.org/r/20250408064612.41359-1-eagle.alexander923@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3588.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/clk/rockchip/clk-rk3588.c
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -64,6 +64,7 @@ static struct rockchip_pll_rate_table rk
+ RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),
+ RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),
+ RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
++ RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
+ RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),
+ RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),
+ RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),
--- /dev/null
+From 646bfc52bbe184c0579060c3919e5d70885b0dcc Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Wed, 26 Mar 2025 11:35:56 +0000
+Subject: [PATCH] clk: rockchip: Drop empty init callback for rk3588 PLL type
+
+Unlike PLLs in previous geneation of SoCs, PLLs in RK3588 type don't
+require any platform-specific initialization. Drop callback
+rockchip_rk3588_pll_init() that does nothing in fact to clean the
+driver up.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20250326113556.21039-1-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-pll.c | 11 -----------
+ 1 file changed, 11 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-pll.c
++++ b/drivers/clk/rockchip/clk-pll.c
+@@ -1025,16 +1025,6 @@ static int rockchip_rk3588_pll_is_enable
+ return !(pllcon & RK3588_PLLCON1_PWRDOWN);
+ }
+
+-static int rockchip_rk3588_pll_init(struct clk_hw *hw)
+-{
+- struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
+-
+- if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
+- return 0;
+-
+- return 0;
+-}
+-
+ static const struct clk_ops rockchip_rk3588_pll_clk_norate_ops = {
+ .recalc_rate = rockchip_rk3588_pll_recalc_rate,
+ .enable = rockchip_rk3588_pll_enable,
+@@ -1049,7 +1039,6 @@ static const struct clk_ops rockchip_rk3
+ .enable = rockchip_rk3588_pll_enable,
+ .disable = rockchip_rk3588_pll_disable,
+ .is_enabled = rockchip_rk3588_pll_is_enabled,
+- .init = rockchip_rk3588_pll_init,
+ };
+
+ /*
--- /dev/null
+From 184055a9ae2b7b19f6fd6e9c0b7e1edce6930b2f Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Wed, 5 Feb 2025 14:15:51 +0800
+Subject: [PATCH] soc: rockchip: add header for suspend mode SIP interface
+
+Add ROCKCHIP_SIP_SUSPEND_MODE to pass down parameters to Trusted Firmware
+in order to decide suspend mode. Currently only add ROCKCHIP_SLEEP_PD_CONFIG
+which teaches firmware to power down controllers or not.
+
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Acked-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/1738736156-119203-3-git-send-email-shawn.lin@rock-chips.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ include/soc/rockchip/rockchip_sip.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/include/soc/rockchip/rockchip_sip.h
++++ b/include/soc/rockchip/rockchip_sip.h
+@@ -6,6 +6,9 @@
+ #ifndef __SOC_ROCKCHIP_SIP_H
+ #define __SOC_ROCKCHIP_SIP_H
+
++#define ROCKCHIP_SIP_SUSPEND_MODE 0x82000003
++#define ROCKCHIP_SLEEP_PD_CONFIG 0xff
++
+ #define ROCKCHIP_SIP_DRAM_FREQ 0x82000008
+ #define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00
+ #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01
--- /dev/null
+From d934a93bbcccd551c142206b8129903d18126261 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Mon, 10 Feb 2025 23:45:05 +0100
+Subject: [PATCH] clk: rockchip: rk3576: define clk_otp_phy_g
+
+The phy clock of the OTP block is also present, but was not defined
+so far. Though its clk-id already existed, so just define its location.
+
+Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250210224510.1194963-2-heiko@sntech.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3576.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/clk/rockchip/clk-rk3576.c
++++ b/drivers/clk/rockchip/clk-rk3576.c
+@@ -541,6 +541,8 @@ static struct rockchip_clk_branch rk3576
+ RK3576_CLKGATE_CON(5), 14, GFLAGS),
+ GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
+ RK3576_CLKGATE_CON(5), 15, GFLAGS),
++ GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
++ RK3576_CLKGATE_CON(6), 0, GFLAGS),
+ COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", mux_24m_spll_gpll_cpll_p, 0,
+ RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS,
+ RK3576_CLKGATE_CON(6), 3, GFLAGS),
--- /dev/null
+From 28699ca6d9018201674787e7b6bdce68d9cf7256 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Mon, 10 Mar 2025 10:59:56 +0100
+Subject: [PATCH] dt-bindings: clock: rk3576: add SCMI clocks
+
+Mainline Linux uses different clock IDs from both downstream and
+mainline TF-A, which both got them from downstream Linux. If we want to
+control clocks through SCMI, we'll need to know about these IDs.
+
+Add the relevant ones prefixed with SCMI_ to the header.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Acked-by: "Rob Herring (Arm)" <robh@kernel.org>
+Link: https://lore.kernel.org/r/20250310-rk3576-scmi-clocks-v1-1-e165deb034e8@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ include/dt-bindings/clock/rockchip,rk3576-cru.h | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/include/dt-bindings/clock/rockchip,rk3576-cru.h
++++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h
+@@ -589,4 +589,9 @@
+ #define PCLK_EDP_S 569
+ #define ACLK_KLAD 570
+
++/* SCMI clocks, use these when changing clocks through SCMI */
++#define SCMI_ARMCLK_L 10
++#define SCMI_ARMCLK_B 11
++#define SCMI_CLK_GPU 456
++
+ #endif
--- /dev/null
+From 4210f21c004a18aad11c55bdaf552e649a4fd286 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Fri, 2 May 2025 13:03:07 +0200
+Subject: [PATCH] dt-bindings: clock: rk3576: add IOC gated clocks
+
+Certain clocks on the RK3576 are additionally essentially "gated" behind
+some bit toggles in the IOC GRF range. Downstream ungates these by
+adding a separate clock driver that maps over the GRF range and leaks
+their implementation of this into the DT.
+
+Instead, define some new clock IDs for these, so that consumers of these
+types of clocks can properly articulate which clock they're using, so
+that we can then add them to the clock driver for SoCs that need them.
+
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-1-376cef19dd7c@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ include/dt-bindings/clock/rockchip,rk3576-cru.h | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/include/dt-bindings/clock/rockchip,rk3576-cru.h
++++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h
+@@ -594,4 +594,14 @@
+ #define SCMI_ARMCLK_B 11
+ #define SCMI_CLK_GPU 456
+
++/* IOC-controlled output clocks */
++#define CLK_SAI0_MCLKOUT_TO_IO 571
++#define CLK_SAI1_MCLKOUT_TO_IO 572
++#define CLK_SAI2_MCLKOUT_TO_IO 573
++#define CLK_SAI3_MCLKOUT_TO_IO 574
++#define CLK_SAI4_MCLKOUT_TO_IO 575
++#define CLK_SAI4_MCLKOUT_TO_IO 575
++#define CLK_FSPI0_TO_IO 576
++#define CLK_FSPI1_TO_IO 577
++
+ #endif
--- /dev/null
+From 70a114daf2077472e58b3cac23ba8998e35352f4 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Fri, 2 May 2025 13:03:08 +0200
+Subject: [PATCH] clk: rockchip: introduce auxiliary GRFs
+
+The MUXGRF clock branch type depends on having access to some sort of
+GRF as a regmap to be registered. So far, we could easily get away with
+only ever having one GRF stowed away in the context.
+
+However, newer Rockchip SoCs, such as the RK3576, have several GRFs
+which are relevant for clock purposes. It already depends on the pmu0
+GRF for MUXGRF reasons, but could get away with not refactoring this
+because it didn't need the sysgrf at all, so could overwrite the pointer
+in the clock provider to the pmu0 grf regmap handle.
+
+In preparation for needing to finally access more than one GRF per SoC,
+let's untangle this. Introduce an auxiliary GRF hashmap, and a GRF type
+enum. The hashmap is keyed by the enum, and clock branches now have a
+struct member to store the value of that enum, which defaults to the
+system GRF.
+
+The SoC-specific _clk_init function can then insert pointers to GRF
+regmaps into the hashmap based on the grf type.
+
+During clock branch registration, we then pick the right GRF for each
+branch from the hashmap if something other than the sys GRF is
+requested.
+
+The reason for doing it with this grf type indirection in the clock
+branches is so that we don't need to define the MUXGRF branches in a
+separate step, just to have a direct pointer to a regmap available
+already.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-2-376cef19dd7c@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3288.c | 2 +-
+ drivers/clk/rockchip/clk-rk3328.c | 6 +++---
+ drivers/clk/rockchip/clk-rk3568.c | 2 +-
+ drivers/clk/rockchip/clk-rk3576.c | 32 +++++++++++++++++++++----------
+ drivers/clk/rockchip/clk-rv1126.c | 2 +-
+ drivers/clk/rockchip/clk.c | 17 +++++++++++++++-
+ drivers/clk/rockchip/clk.h | 29 +++++++++++++++++++++++++++-
+ 7 files changed, 72 insertions(+), 18 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-rk3288.c
++++ b/drivers/clk/rockchip/clk-rk3288.c
+@@ -418,7 +418,7 @@ static struct rockchip_clk_branch rk3288
+ RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
+ RK3288_CLKGATE_CON(3), 11, GFLAGS),
+ MUXGRF(0, "aclk_vcodec_pre", mux_aclk_vcodec_pre_p, CLK_SET_RATE_PARENT,
+- RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS),
++ RK3288_GRF_SOC_CON(0), 7, 1, MFLAGS, grf_type_sys),
+ GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
+ RK3288_CLKGATE_CON(9), 0, GFLAGS),
+
+--- a/drivers/clk/rockchip/clk-rk3328.c
++++ b/drivers/clk/rockchip/clk-rk3328.c
+@@ -677,9 +677,9 @@ static struct rockchip_clk_branch rk3328
+ RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,
+ RK3328_CLKGATE_CON(3), 5, GFLAGS),
+ MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,
+- RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),
++ RK3328_GRF_MAC_CON1, 10, 1, MFLAGS, grf_type_sys),
+ MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,
+- RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),
++ RK3328_GRF_SOC_CON4, 14, 1, MFLAGS, grf_type_sys),
+
+ COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
+ RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
+@@ -692,7 +692,7 @@ static struct rockchip_clk_branch rk3328
+ RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,
+ RK3328_CLKGATE_CON(9), 2, GFLAGS),
+ MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT,
+- RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),
++ RK3328_GRF_MAC_CON2, 10, 1, MFLAGS, grf_type_sys),
+
+ FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
+
+--- a/drivers/clk/rockchip/clk-rk3568.c
++++ b/drivers/clk/rockchip/clk-rk3568.c
+@@ -590,7 +590,7 @@ static struct rockchip_clk_branch rk3568
+ RK3568_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
+ RK3568_CLKGATE_CON(4), 0, GFLAGS),
+ MUXGRF(CLK_DDR1X, "clk_ddr1x", clk_ddr1x_p, CLK_SET_RATE_PARENT,
+- RK3568_CLKSEL_CON(9), 15, 1, MFLAGS),
++ RK3568_CLKSEL_CON(9), 15, 1, MFLAGS, grf_type_sys),
+
+ COMPOSITE_NOMUX(CLK_MSCH, "clk_msch", "clk_ddr1x", CLK_IGNORE_UNUSED,
+ RK3568_CLKSEL_CON(10), 0, 2, DFLAGS,
+--- a/drivers/clk/rockchip/clk-rk3576.c
++++ b/drivers/clk/rockchip/clk-rk3576.c
+@@ -1678,13 +1678,13 @@ static struct rockchip_clk_branch rk3576
+
+ /* phy ref */
+ MUXGRF(CLK_PHY_REF_SRC, "clk_phy_ref_src", clk_phy_ref_src_p, 0,
+- RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS),
++ RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS, grf_type_pmu0),
+ MUXGRF(CLK_USBPHY_REF_SRC, "clk_usbphy_ref_src", clk_usbphy_ref_src_p, 0,
+- RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS),
++ RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS, grf_type_pmu0),
+ MUXGRF(CLK_CPLL_REF_SRC, "clk_cpll_ref_src", clk_cpll_ref_src_p, 0,
+- RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS),
++ RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS, grf_type_pmu0),
+ MUXGRF(CLK_AUPLL_REF_SRC, "clk_aupll_ref_src", clk_aupll_ref_src_p, 0,
+- RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS),
++ RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS, grf_type_pmu0),
+
+ /* secure ns */
+ COMPOSITE_NODIV(ACLK_SECURE_NS, "aclk_secure_ns", mux_350m_175m_116m_24m_p, CLK_IS_CRITICAL,
+@@ -1727,13 +1727,14 @@ static void __init rk3576_clk_init(struc
+ struct rockchip_clk_provider *ctx;
+ unsigned long clk_nr_clks;
+ void __iomem *reg_base;
+- struct regmap *grf;
++ struct rockchip_aux_grf *pmu0_grf_e;
++ struct regmap *pmu0_grf;
+
+ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3576_clk_branches,
+ ARRAY_SIZE(rk3576_clk_branches)) + 1;
+
+- grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf");
+- if (IS_ERR(grf)) {
++ pmu0_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf");
++ if (IS_ERR(pmu0_grf)) {
+ pr_err("%s: could not get PMU0 GRF syscon\n", __func__);
+ return;
+ }
+@@ -1747,11 +1748,16 @@ static void __init rk3576_clk_init(struc
+ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
+ if (IS_ERR(ctx)) {
+ pr_err("%s: rockchip clk init failed\n", __func__);
+- iounmap(reg_base);
+- return;
++ goto err_unmap;
+ }
+
+- ctx->grf = grf;
++ pmu0_grf_e = kzalloc(sizeof(*pmu0_grf_e), GFP_KERNEL);
++ if (!pmu0_grf_e)
++ goto err_unmap;
++
++ pmu0_grf_e->grf = pmu0_grf;
++ pmu0_grf_e->type = grf_type_pmu0;
++ hash_add(ctx->aux_grf_table, &pmu0_grf_e->node, grf_type_pmu0);
+
+ rockchip_clk_register_plls(ctx, rk3576_pll_clks,
+ ARRAY_SIZE(rk3576_pll_clks),
+@@ -1774,6 +1780,12 @@ static void __init rk3576_clk_init(struc
+ rockchip_register_restart_notifier(ctx, RK3576_GLB_SRST_FST, NULL);
+
+ rockchip_clk_of_add_provider(np, ctx);
++
++ return;
++
++err_unmap:
++ iounmap(reg_base);
++ return;
+ }
+
+ CLK_OF_DECLARE(rk3576_cru, "rockchip,rk3576-cru", rk3576_clk_init);
+--- a/drivers/clk/rockchip/clk-rv1126.c
++++ b/drivers/clk/rockchip/clk-rv1126.c
+@@ -857,7 +857,7 @@ static struct rockchip_clk_branch rv1126
+ RV1126_GMAC_CON, 5, 1, MFLAGS),
+ MUXGRF(CLK_GMAC_SRC, "clk_gmac_src", mux_clk_gmac_src_p, CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT,
+- RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS),
++ RV1126_GRF_IOFUNC_CON1, 12, 1, MFLAGS, grf_type_sys),
+
+ GATE(CLK_GMAC_REF, "clk_gmac_ref", "clk_gmac_src", 0,
+ RV1126_CLKGATE_CON(20), 7, GFLAGS),
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -382,6 +382,8 @@ static struct rockchip_clk_provider *roc
+ ctx->cru_node = np;
+ spin_lock_init(&ctx->lock);
+
++ hash_init(ctx->aux_grf_table);
++
+ ctx->grf = syscon_regmap_lookup_by_phandle(ctx->cru_node,
+ "rockchip,grf");
+
+@@ -496,6 +498,8 @@ void rockchip_clk_register_branches(stru
+ struct rockchip_clk_branch *list,
+ unsigned int nr_clk)
+ {
++ struct regmap *grf = ctx->grf;
++ struct rockchip_aux_grf *agrf;
+ struct clk *clk;
+ unsigned int idx;
+ unsigned long flags;
+@@ -504,6 +508,17 @@ void rockchip_clk_register_branches(stru
+ flags = list->flags;
+ clk = NULL;
+
++ /* for GRF-dependent branches, choose the right grf first */
++ if (list->branch_type == branch_muxgrf &&
++ list->grf_type != grf_type_sys) {
++ hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) {
++ if (agrf->type == list->grf_type) {
++ grf = agrf->grf;
++ break;
++ }
++ }
++ }
++
+ /* catch simple muxes */
+ switch (list->branch_type) {
+ case branch_mux:
+@@ -526,7 +541,7 @@ void rockchip_clk_register_branches(stru
+ case branch_muxgrf:
+ clk = rockchip_clk_register_muxgrf(list->name,
+ list->parent_names, list->num_parents,
+- flags, ctx->grf, list->muxdiv_offset,
++ flags, grf, list->muxdiv_offset,
+ list->mux_shift, list->mux_width,
+ list->mux_flags);
+ break;
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -19,6 +19,7 @@
+
+ #include <linux/io.h>
+ #include <linux/clk-provider.h>
++#include <linux/hashtable.h>
+
+ struct clk;
+
+@@ -381,12 +382,35 @@ enum rockchip_pll_type {
+ .k = _k, \
+ }
+
++enum rockchip_grf_type {
++ grf_type_sys = 0,
++ grf_type_pmu0,
++ grf_type_pmu1,
++ grf_type_ioc,
++};
++
++/* ceil(sqrt(enums in rockchip_grf_type - 1)) */
++#define GRF_HASH_ORDER 2
++
++/**
++ * struct rockchip_aux_grf - entry for the aux_grf_table hashtable
++ * @grf: pointer to the grf this entry references
++ * @type: what type of GRF this is
++ * @node: hlist node
++ */
++struct rockchip_aux_grf {
++ struct regmap *grf;
++ enum rockchip_grf_type type;
++ struct hlist_node node;
++};
++
+ /**
+ * struct rockchip_clk_provider - information about clock provider
+ * @reg_base: virtual address for the register base.
+ * @clk_data: holds clock related data like clk* and number of clocks.
+ * @cru_node: device-node of the clock-provider
+ * @grf: regmap of the general-register-files syscon
++ * @aux_grf_table: hashtable of auxiliary GRF regmaps, indexed by grf_type
+ * @lock: maintains exclusion between callbacks for a given clock-provider.
+ */
+ struct rockchip_clk_provider {
+@@ -394,6 +418,7 @@ struct rockchip_clk_provider {
+ struct clk_onecell_data clk_data;
+ struct device_node *cru_node;
+ struct regmap *grf;
++ DECLARE_HASHTABLE(aux_grf_table, GRF_HASH_ORDER);
+ spinlock_t lock;
+ };
+
+@@ -599,6 +624,7 @@ struct rockchip_clk_branch {
+ u8 gate_shift;
+ u8 gate_flags;
+ unsigned int linked_clk_id;
++ enum rockchip_grf_type grf_type;
+ struct rockchip_clk_branch *child;
+ };
+
+@@ -839,7 +865,7 @@ struct rockchip_clk_branch {
+ .mux_table = mt, \
+ }
+
+-#define MUXGRF(_id, cname, pnames, f, o, s, w, mf) \
++#define MUXGRF(_id, cname, pnames, f, o, s, w, mf, gt) \
+ { \
+ .id = _id, \
+ .branch_type = branch_muxgrf, \
+@@ -852,6 +878,7 @@ struct rockchip_clk_branch {
+ .mux_width = w, \
+ .mux_flags = mf, \
+ .gate_offset = -1, \
++ .grf_type = gt, \
+ }
+
+ #define DIV(_id, cname, pname, f, o, s, w, df) \
--- /dev/null
+From e277168cabe9fd99e647f5dad0bc846d5d6b0093 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Fri, 2 May 2025 13:03:09 +0200
+Subject: [PATCH] clk: rockchip: introduce GRF gates
+
+Some rockchip SoCs, namely the RK3576, have bits in a General Register
+File (GRF) that act just like clock gates. The downstream vendor kernel
+simply maps over the already mapped GRF range with a generic clock gate
+driver. This solution isn't suitable for upstream, as a memory range
+will be in use by multiple drivers at the same time, and it leaks
+implementation details into the device tree.
+
+Instead, implement this with a new clock branch type in the Rockchip
+clock driver: GRF gates. Somewhat akin to MUXGRF, this clock branch
+depends on the type of GRF, but functions like a gate instead.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-3-376cef19dd7c@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/Makefile | 1 +
+ drivers/clk/rockchip/clk.c | 9 ++-
+ drivers/clk/rockchip/clk.h | 20 ++++++
+ drivers/clk/rockchip/gate-grf.c | 105 ++++++++++++++++++++++++++++++++
+ 4 files changed, 134 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/clk/rockchip/gate-grf.c
+
+--- a/drivers/clk/rockchip/Makefile
++++ b/drivers/clk/rockchip/Makefile
+@@ -14,6 +14,7 @@ clk-rockchip-y += clk-mmc-phase.o
+ clk-rockchip-y += clk-muxgrf.o
+ clk-rockchip-y += clk-ddr.o
+ clk-rockchip-y += gate-link.o
++clk-rockchip-y += gate-grf.o
+ clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
+
+ obj-$(CONFIG_CLK_PX30) += clk-px30.o
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -509,7 +509,7 @@ void rockchip_clk_register_branches(stru
+ clk = NULL;
+
+ /* for GRF-dependent branches, choose the right grf first */
+- if (list->branch_type == branch_muxgrf &&
++ if ((list->branch_type == branch_muxgrf || list->branch_type == branch_grf_gate) &&
+ list->grf_type != grf_type_sys) {
+ hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) {
+ if (agrf->type == list->grf_type) {
+@@ -588,6 +588,13 @@ void rockchip_clk_register_branches(stru
+ ctx->reg_base + list->gate_offset,
+ list->gate_shift, list->gate_flags, &ctx->lock);
+ break;
++ case branch_grf_gate:
++ flags |= CLK_SET_RATE_PARENT;
++ clk = rockchip_clk_register_gate_grf(list->name,
++ list->parent_names[0], flags, grf,
++ list->gate_offset, list->gate_shift,
++ list->gate_flags);
++ break;
+ case branch_composite:
+ clk = rockchip_clk_register_branch(list->name,
+ list->parent_names, list->num_parents,
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -586,6 +586,11 @@ struct clk *rockchip_clk_register_muxgrf
+ int flags, struct regmap *grf, int reg,
+ int shift, int width, int mux_flags);
+
++struct clk *rockchip_clk_register_gate_grf(const char *name,
++ const char *parent_name, unsigned long flags,
++ struct regmap *regmap, unsigned int reg,
++ unsigned int shift, u8 gate_flags);
++
+ #define PNAME(x) static const char *const x[] __initconst
+
+ enum rockchip_clk_branch_type {
+@@ -595,6 +600,7 @@ enum rockchip_clk_branch_type {
+ branch_divider,
+ branch_fraction_divider,
+ branch_gate,
++ branch_grf_gate,
+ branch_linked_gate,
+ branch_mmc,
+ branch_inverter,
+@@ -924,6 +930,20 @@ struct rockchip_clk_branch {
+ .gate_flags = gf, \
+ }
+
++#define GATE_GRF(_id, cname, pname, f, o, b, gf, gt) \
++ { \
++ .id = _id, \
++ .branch_type = branch_grf_gate, \
++ .name = cname, \
++ .parent_names = (const char *[]){ pname }, \
++ .num_parents = 1, \
++ .flags = f, \
++ .gate_offset = o, \
++ .gate_shift = b, \
++ .gate_flags = gf, \
++ .grf_type = gt, \
++ }
++
+ #define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
+ { \
+ .id = _id, \
+--- /dev/null
++++ b/drivers/clk/rockchip/gate-grf.c
+@@ -0,0 +1,105 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2025 Collabora Ltd.
++ * Author: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
++ *
++ * Certain clocks on Rockchip are "gated" behind an additional register bit
++ * write in a GRF register, such as the SAI MCLKs on RK3576. This code
++ * implements a clock driver for these types of gates, based on regmaps.
++ */
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/regmap.h>
++#include <linux/slab.h>
++#include "clk.h"
++
++struct rockchip_gate_grf {
++ struct clk_hw hw;
++ struct regmap *regmap;
++ unsigned int reg;
++ unsigned int shift;
++ u8 flags;
++};
++
++#define to_gate_grf(_hw) container_of(_hw, struct rockchip_gate_grf, hw)
++
++static int rockchip_gate_grf_enable(struct clk_hw *hw)
++{
++ struct rockchip_gate_grf *gate = to_gate_grf(hw);
++ u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? BIT(gate->shift) : 0;
++ u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16);
++ int ret;
++
++ ret = regmap_update_bits(gate->regmap, gate->reg,
++ hiword | BIT(gate->shift), hiword | val);
++
++ return ret;
++}
++
++static void rockchip_gate_grf_disable(struct clk_hw *hw)
++{
++ struct rockchip_gate_grf *gate = to_gate_grf(hw);
++ u32 val = !(gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : BIT(gate->shift);
++ u32 hiword = ((gate->flags & CLK_GATE_HIWORD_MASK) ? 1 : 0) << (gate->shift + 16);
++
++ regmap_update_bits(gate->regmap, gate->reg,
++ hiword | BIT(gate->shift), hiword | val);
++}
++
++static int rockchip_gate_grf_is_enabled(struct clk_hw *hw)
++{
++ struct rockchip_gate_grf *gate = to_gate_grf(hw);
++ bool invert = !!(gate->flags & CLK_GATE_SET_TO_DISABLE);
++ int ret;
++
++ ret = regmap_test_bits(gate->regmap, gate->reg, BIT(gate->shift));
++ if (ret < 0)
++ ret = 0;
++
++ return invert ? 1 - ret : ret;
++
++}
++
++static const struct clk_ops rockchip_gate_grf_ops = {
++ .enable = rockchip_gate_grf_enable,
++ .disable = rockchip_gate_grf_disable,
++ .is_enabled = rockchip_gate_grf_is_enabled,
++};
++
++struct clk *rockchip_clk_register_gate_grf(const char *name,
++ const char *parent_name, unsigned long flags,
++ struct regmap *regmap, unsigned int reg, unsigned int shift,
++ u8 gate_flags)
++{
++ struct rockchip_gate_grf *gate;
++ struct clk_init_data init;
++ struct clk *clk;
++
++ if (IS_ERR(regmap)) {
++ pr_err("%s: regmap not available\n", __func__);
++ return ERR_PTR(-EOPNOTSUPP);
++ }
++
++ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
++ if (!gate)
++ return ERR_PTR(-ENOMEM);
++
++ init.name = name;
++ init.flags = flags;
++ init.num_parents = parent_name ? 1 : 0;
++ init.parent_names = parent_name ? &parent_name : NULL;
++ init.ops = &rockchip_gate_grf_ops;
++
++ gate->hw.init = &init;
++ gate->regmap = regmap;
++ gate->reg = reg;
++ gate->shift = shift;
++ gate->flags = gate_flags;
++
++ clk = clk_register(NULL, &gate->hw);
++ if (IS_ERR(clk))
++ kfree(gate);
++
++ return clk;
++}
--- /dev/null
+From 9199ec29f0977efee223791c9ee3eb402d23f8ba Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Fri, 2 May 2025 13:03:10 +0200
+Subject: [PATCH] clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576
+
+The Rockchip RK3576 gates the SAI MCLKOUT clocks behind some IOC GRF
+writes.
+
+Add these clock branches, and add the IOC GRF to the auxiliary GRF
+hashtable.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250502-rk3576-sai-v3-4-376cef19dd7c@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3576.c | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/drivers/clk/rockchip/clk-rk3576.c
++++ b/drivers/clk/rockchip/clk-rk3576.c
+@@ -15,6 +15,7 @@
+
+ #define RK3576_GRF_SOC_STATUS0 0x600
+ #define RK3576_PMU0_GRF_OSC_CON6 0x18
++#define RK3576_VCCIO_IOC_MISC_CON0 0x6400
+
+ enum rk3576_plls {
+ bpll, lpll, vpll, aupll, cpll, gpll, ppll,
+@@ -1481,6 +1482,14 @@ static struct rockchip_clk_branch rk3576
+ RK3576_CLKGATE_CON(10), 0, GFLAGS),
+ GATE(CLK_SAI0_MCLKOUT, "clk_sai0_mclkout", "mclk_sai0_8ch", 0,
+ RK3576_CLKGATE_CON(10), 1, GFLAGS),
++ GATE_GRF(CLK_SAI0_MCLKOUT_TO_IO, "mclk_sai0_to_io", "clk_sai0_mclkout",
++ 0, RK3576_VCCIO_IOC_MISC_CON0, 0, GFLAGS, grf_type_ioc),
++ GATE_GRF(CLK_SAI1_MCLKOUT_TO_IO, "mclk_sai1_to_io", "clk_sai1_mclkout",
++ 0, RK3576_VCCIO_IOC_MISC_CON0, 1, GFLAGS, grf_type_ioc),
++ GATE_GRF(CLK_SAI2_MCLKOUT_TO_IO, "mclk_sai2_to_io", "clk_sai2_mclkout",
++ 0, RK3576_VCCIO_IOC_MISC_CON0, 2, GFLAGS, grf_type_ioc),
++ GATE_GRF(CLK_SAI3_MCLKOUT_TO_IO, "mclk_sai3_to_io", "clk_sai3_mclkout",
++ 0, RK3576_VCCIO_IOC_MISC_CON0, 3, GFLAGS, grf_type_ioc),
+
+ /* sdgmac */
+ COMPOSITE_NODIV(HCLK_SDGMAC_ROOT, "hclk_sdgmac_root", mux_200m_100m_50m_24m_p, 0,
+@@ -1727,7 +1736,9 @@ static void __init rk3576_clk_init(struc
+ struct rockchip_clk_provider *ctx;
+ unsigned long clk_nr_clks;
+ void __iomem *reg_base;
++ struct rockchip_aux_grf *ioc_grf_e;
+ struct rockchip_aux_grf *pmu0_grf_e;
++ struct regmap *ioc_grf;
+ struct regmap *pmu0_grf;
+
+ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3576_clk_branches,
+@@ -1739,6 +1750,12 @@ static void __init rk3576_clk_init(struc
+ return;
+ }
+
++ ioc_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-ioc-grf");
++ if (IS_ERR(ioc_grf)) {
++ pr_err("%s: could not get IOC GRF syscon\n", __func__);
++ return;
++ }
++
+ reg_base = of_iomap(np, 0);
+ if (!reg_base) {
+ pr_err("%s: could not map cru region\n", __func__);
+@@ -1759,6 +1776,14 @@ static void __init rk3576_clk_init(struc
+ pmu0_grf_e->type = grf_type_pmu0;
+ hash_add(ctx->aux_grf_table, &pmu0_grf_e->node, grf_type_pmu0);
+
++ ioc_grf_e = kzalloc(sizeof(*ioc_grf_e), GFP_KERNEL);
++ if (!ioc_grf_e)
++ goto err_free_pmu0;
++
++ ioc_grf_e->grf = ioc_grf;
++ ioc_grf_e->type = grf_type_ioc;
++ hash_add(ctx->aux_grf_table, &ioc_grf_e->node, grf_type_ioc);
++
+ rockchip_clk_register_plls(ctx, rk3576_pll_clks,
+ ARRAY_SIZE(rk3576_pll_clks),
+ RK3576_GRF_SOC_STATUS0);
+@@ -1783,6 +1808,8 @@ static void __init rk3576_clk_init(struc
+
+ return;
+
++err_free_pmu0:
++ kfree(pmu0_grf_e);
+ err_unmap:
+ iounmap(reg_base);
+ return;
--- /dev/null
+From 92da5c3cba23ee4be2c043bb63a551c89c48de18 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Thu, 15 May 2025 10:26:51 +0200
+Subject: [PATCH] clk: rockchip: rk3576: add missing slab.h include
+
+The change for auxiliary GRFs introduced kzalloc usage into the rk3576 clock
+driver, but missed adding the header for its prototype. Add it now.
+
+Reported-by: kernel test robot <lkp@intel.com>
+Closes: https://lore.kernel.org/oe-kbuild-all/202505150941.KWKskr2c-lkp@intel.com/
+Fixes: 70a114daf207 ("clk: rockchip: introduce auxiliary GRFs")
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250515082652.2503063-1-heiko@sntech.de
+---
+ drivers/clk/rockchip/clk-rk3576.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/clk/rockchip/clk-rk3576.c
++++ b/drivers/clk/rockchip/clk-rk3576.c
+@@ -10,6 +10,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/syscore_ops.h>
+ #include <linux/mfd/syscon.h>
++#include <linux/slab.h>
+ #include <dt-bindings/clock/rockchip,rk3576-cru.h>
+ #include "clk.h"
+
--- /dev/null
+From e0c0a97bc308f71b0934e3637ac545ce65195df0 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Mon, 17 Feb 2025 06:11:42 +0000
+Subject: [PATCH] dt-bindings: clock: Document clock and reset unit of RK3528
+
+There are two types of clocks in RK3528 SoC, CRU-managed and
+SCMI-managed. Independent IDs are assigned to them.
+
+For the reset part, differing from previous Rockchip SoCs and
+downstream bindings which embeds register offsets into the IDs, gapless
+numbers starting from zero are used.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20250217061142.38480-6-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../bindings/clock/rockchip,rk3528-cru.yaml | 64 +++
+ .../dt-bindings/clock/rockchip,rk3528-cru.h | 453 ++++++++++++++++++
+ .../dt-bindings/reset/rockchip,rk3528-cru.h | 241 ++++++++++
+ 3 files changed, 758 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml
+ create mode 100644 include/dt-bindings/clock/rockchip,rk3528-cru.h
+ create mode 100644 include/dt-bindings/reset/rockchip,rk3528-cru.h
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml
+@@ -0,0 +1,64 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip RK3528 Clock and Reset Controller
++
++maintainers:
++ - Yao Zi <ziyao@disroot.org>
++
++description: |
++ The RK3528 clock controller generates the clock and also implements a reset
++ controller for SoC peripherals. For example, it provides SCLK_UART0 and
++ PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART
++ module.
++ Each clock is assigned an identifier, consumer nodes can use it to specify
++ the clock. All available clock and reset IDs are defined in dt-binding
++ headers.
++
++properties:
++ compatible:
++ const: rockchip,rk3528-cru
++
++ reg:
++ maxItems: 1
++
++ clocks:
++ items:
++ - description: External 24MHz oscillator clock
++ - description: >
++ 50MHz clock generated by PHY module, for generating GMAC0 clocks only.
++
++ clock-names:
++ items:
++ - const: xin24m
++ - const: gmac0
++
++ "#clock-cells":
++ const: 1
++
++ "#reset-cells":
++ const: 1
++
++required:
++ - compatible
++ - reg
++ - clocks
++ - clock-names
++ - "#clock-cells"
++ - "#reset-cells"
++
++additionalProperties: false
++
++examples:
++ - |
++ clock-controller@ff4a0000 {
++ compatible = "rockchip,rk3528-cru";
++ reg = <0xff4a0000 0x30000>;
++ clocks = <&xin24m>, <&gmac0_clk>;
++ clock-names = "xin24m", "gmac0";
++ #clock-cells = <1>;
++ #reset-cells = <1>;
++ };
+--- /dev/null
++++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h
+@@ -0,0 +1,453 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
++/*
++ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
++ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
++ * Author: Joseph Chen <chenjh@rock-chips.com>
++ */
++
++#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
++#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
++
++/* cru-clocks indices */
++#define PLL_APLL 0
++#define PLL_CPLL 1
++#define PLL_GPLL 2
++#define PLL_PPLL 3
++#define PLL_DPLL 4
++#define ARMCLK 5
++#define XIN_OSC0_HALF 6
++#define CLK_MATRIX_50M_SRC 7
++#define CLK_MATRIX_100M_SRC 8
++#define CLK_MATRIX_150M_SRC 9
++#define CLK_MATRIX_200M_SRC 10
++#define CLK_MATRIX_250M_SRC 11
++#define CLK_MATRIX_300M_SRC 12
++#define CLK_MATRIX_339M_SRC 13
++#define CLK_MATRIX_400M_SRC 14
++#define CLK_MATRIX_500M_SRC 15
++#define CLK_MATRIX_600M_SRC 16
++#define CLK_UART0_SRC 17
++#define CLK_UART0_FRAC 18
++#define SCLK_UART0 19
++#define CLK_UART1_SRC 20
++#define CLK_UART1_FRAC 21
++#define SCLK_UART1 22
++#define CLK_UART2_SRC 23
++#define CLK_UART2_FRAC 24
++#define SCLK_UART2 25
++#define CLK_UART3_SRC 26
++#define CLK_UART3_FRAC 27
++#define SCLK_UART3 28
++#define CLK_UART4_SRC 29
++#define CLK_UART4_FRAC 30
++#define SCLK_UART4 31
++#define CLK_UART5_SRC 32
++#define CLK_UART5_FRAC 33
++#define SCLK_UART5 34
++#define CLK_UART6_SRC 35
++#define CLK_UART6_FRAC 36
++#define SCLK_UART6 37
++#define CLK_UART7_SRC 38
++#define CLK_UART7_FRAC 39
++#define SCLK_UART7 40
++#define CLK_I2S0_2CH_SRC 41
++#define CLK_I2S0_2CH_FRAC 42
++#define MCLK_I2S0_2CH_SAI_SRC 43
++#define CLK_I2S3_8CH_SRC 44
++#define CLK_I2S3_8CH_FRAC 45
++#define MCLK_I2S3_8CH_SAI_SRC 46
++#define CLK_I2S1_8CH_SRC 47
++#define CLK_I2S1_8CH_FRAC 48
++#define MCLK_I2S1_8CH_SAI_SRC 49
++#define CLK_I2S2_2CH_SRC 50
++#define CLK_I2S2_2CH_FRAC 51
++#define MCLK_I2S2_2CH_SAI_SRC 52
++#define CLK_SPDIF_SRC 53
++#define CLK_SPDIF_FRAC 54
++#define MCLK_SPDIF_SRC 55
++#define DCLK_VOP_SRC0 56
++#define DCLK_VOP_SRC1 57
++#define CLK_HSM 58
++#define CLK_CORE_SRC_ACS 59
++#define CLK_CORE_SRC_PVTMUX 60
++#define CLK_CORE_SRC 61
++#define CLK_CORE 62
++#define ACLK_M_CORE_BIU 63
++#define CLK_CORE_PVTPLL_SRC 64
++#define PCLK_DBG 65
++#define SWCLKTCK 66
++#define CLK_SCANHS_CORE 67
++#define CLK_SCANHS_ACLKM_CORE 68
++#define CLK_SCANHS_PCLK_DBG 69
++#define CLK_SCANHS_PCLK_CPU_BIU 70
++#define PCLK_CPU_ROOT 71
++#define PCLK_CORE_GRF 72
++#define PCLK_DAPLITE_BIU 73
++#define PCLK_CPU_BIU 74
++#define CLK_REF_PVTPLL_CORE 75
++#define ACLK_BUS_VOPGL_ROOT 76
++#define ACLK_BUS_VOPGL_BIU 77
++#define ACLK_BUS_H_ROOT 78
++#define ACLK_BUS_H_BIU 79
++#define ACLK_BUS_ROOT 80
++#define HCLK_BUS_ROOT 81
++#define PCLK_BUS_ROOT 82
++#define ACLK_BUS_M_ROOT 83
++#define ACLK_SYSMEM_BIU 84
++#define CLK_TIMER_ROOT 85
++#define ACLK_BUS_BIU 86
++#define HCLK_BUS_BIU 87
++#define PCLK_BUS_BIU 88
++#define PCLK_DFT2APB 89
++#define PCLK_BUS_GRF 90
++#define ACLK_BUS_M_BIU 91
++#define ACLK_GIC 92
++#define ACLK_SPINLOCK 93
++#define ACLK_DMAC 94
++#define PCLK_TIMER 95
++#define CLK_TIMER0 96
++#define CLK_TIMER1 97
++#define CLK_TIMER2 98
++#define CLK_TIMER3 99
++#define CLK_TIMER4 100
++#define CLK_TIMER5 101
++#define PCLK_JDBCK_DAP 102
++#define CLK_JDBCK_DAP 103
++#define PCLK_WDT_NS 104
++#define TCLK_WDT_NS 105
++#define HCLK_TRNG_NS 106
++#define PCLK_UART0 107
++#define PCLK_DMA2DDR 108
++#define ACLK_DMA2DDR 109
++#define PCLK_PWM0 110
++#define CLK_PWM0 111
++#define CLK_CAPTURE_PWM0 112
++#define PCLK_PWM1 113
++#define CLK_PWM1 114
++#define CLK_CAPTURE_PWM1 115
++#define PCLK_SCR 116
++#define ACLK_DCF 117
++#define PCLK_INTMUX 118
++#define CLK_PPLL_I 119
++#define CLK_PPLL_MUX 120
++#define CLK_PPLL_100M_MATRIX 121
++#define CLK_PPLL_50M_MATRIX 122
++#define CLK_REF_PCIE_INNER_PHY 123
++#define CLK_REF_PCIE_100M_PHY 124
++#define ACLK_VPU_L_ROOT 125
++#define CLK_GMAC1_VPU_25M 126
++#define CLK_PPLL_125M_MATRIX 127
++#define ACLK_VPU_ROOT 128
++#define HCLK_VPU_ROOT 129
++#define PCLK_VPU_ROOT 130
++#define ACLK_VPU_BIU 131
++#define HCLK_VPU_BIU 132
++#define PCLK_VPU_BIU 133
++#define ACLK_VPU 134
++#define HCLK_VPU 135
++#define PCLK_CRU_PCIE 136
++#define PCLK_VPU_GRF 137
++#define HCLK_SFC 138
++#define SCLK_SFC 139
++#define CCLK_SRC_EMMC 140
++#define HCLK_EMMC 141
++#define ACLK_EMMC 142
++#define BCLK_EMMC 143
++#define TCLK_EMMC 144
++#define PCLK_GPIO1 145
++#define DBCLK_GPIO1 146
++#define ACLK_VPU_L_BIU 147
++#define PCLK_VPU_IOC 148
++#define HCLK_SAI_I2S0 149
++#define MCLK_SAI_I2S0 150
++#define HCLK_SAI_I2S2 151
++#define MCLK_SAI_I2S2 152
++#define PCLK_ACODEC 153
++#define MCLK_ACODEC_TX 154
++#define PCLK_GPIO3 155
++#define DBCLK_GPIO3 156
++#define PCLK_SPI1 157
++#define CLK_SPI1 158
++#define SCLK_IN_SPI1 159
++#define PCLK_UART2 160
++#define PCLK_UART5 161
++#define PCLK_UART6 162
++#define PCLK_UART7 163
++#define PCLK_I2C3 164
++#define CLK_I2C3 165
++#define PCLK_I2C5 166
++#define CLK_I2C5 167
++#define PCLK_I2C6 168
++#define CLK_I2C6 169
++#define ACLK_MAC_VPU 170
++#define PCLK_MAC_VPU 171
++#define CLK_GMAC1_RMII_VPU 172
++#define CLK_GMAC1_SRC_VPU 173
++#define PCLK_PCIE 174
++#define CLK_PCIE_AUX 175
++#define ACLK_PCIE 176
++#define HCLK_PCIE_SLV 177
++#define HCLK_PCIE_DBI 178
++#define PCLK_PCIE_PHY 179
++#define PCLK_PIPE_GRF 180
++#define CLK_PIPE_USB3OTG_COMBO 181
++#define CLK_UTMI_USB3OTG 182
++#define CLK_PCIE_PIPE_PHY 183
++#define CCLK_SRC_SDIO0 184
++#define HCLK_SDIO0 185
++#define CCLK_SRC_SDIO1 186
++#define HCLK_SDIO1 187
++#define CLK_TS_0 188
++#define CLK_TS_1 189
++#define PCLK_CAN2 190
++#define CLK_CAN2 191
++#define PCLK_CAN3 192
++#define CLK_CAN3 193
++#define PCLK_SARADC 194
++#define CLK_SARADC 195
++#define PCLK_TSADC 196
++#define CLK_TSADC 197
++#define CLK_TSADC_TSEN 198
++#define ACLK_USB3OTG 199
++#define CLK_REF_USB3OTG 200
++#define CLK_SUSPEND_USB3OTG 201
++#define ACLK_GPU_ROOT 202
++#define PCLK_GPU_ROOT 203
++#define ACLK_GPU_BIU 204
++#define PCLK_GPU_BIU 205
++#define ACLK_GPU 206
++#define CLK_GPU_PVTPLL_SRC 207
++#define ACLK_GPU_MALI 208
++#define HCLK_RKVENC_ROOT 209
++#define ACLK_RKVENC_ROOT 210
++#define PCLK_RKVENC_ROOT 211
++#define HCLK_RKVENC_BIU 212
++#define ACLK_RKVENC_BIU 213
++#define PCLK_RKVENC_BIU 214
++#define HCLK_RKVENC 215
++#define ACLK_RKVENC 216
++#define CLK_CORE_RKVENC 217
++#define HCLK_SAI_I2S1 218
++#define MCLK_SAI_I2S1 219
++#define PCLK_I2C1 220
++#define CLK_I2C1 221
++#define PCLK_I2C0 222
++#define CLK_I2C0 223
++#define CLK_UART_JTAG 224
++#define PCLK_SPI0 225
++#define CLK_SPI0 226
++#define SCLK_IN_SPI0 227
++#define PCLK_GPIO4 228
++#define DBCLK_GPIO4 229
++#define PCLK_RKVENC_IOC 230
++#define HCLK_SPDIF 231
++#define MCLK_SPDIF 232
++#define HCLK_PDM 233
++#define MCLK_PDM 234
++#define PCLK_UART1 235
++#define PCLK_UART3 236
++#define PCLK_RKVENC_GRF 237
++#define PCLK_CAN0 238
++#define CLK_CAN0 239
++#define PCLK_CAN1 240
++#define CLK_CAN1 241
++#define ACLK_VO_ROOT 242
++#define HCLK_VO_ROOT 243
++#define PCLK_VO_ROOT 244
++#define ACLK_VO_BIU 245
++#define HCLK_VO_BIU 246
++#define PCLK_VO_BIU 247
++#define HCLK_RGA2E 248
++#define ACLK_RGA2E 249
++#define CLK_CORE_RGA2E 250
++#define HCLK_VDPP 251
++#define ACLK_VDPP 252
++#define CLK_CORE_VDPP 253
++#define PCLK_VO_GRF 254
++#define PCLK_CRU 255
++#define ACLK_VOP_ROOT 256
++#define ACLK_VOP_BIU 257
++#define HCLK_VOP 258
++#define DCLK_VOP0 259
++#define DCLK_VOP1 260
++#define ACLK_VOP 261
++#define PCLK_HDMI 262
++#define CLK_SFR_HDMI 263
++#define CLK_CEC_HDMI 264
++#define CLK_SPDIF_HDMI 265
++#define CLK_HDMIPHY_TMDSSRC 266
++#define CLK_HDMIPHY_PREP 267
++#define PCLK_HDMIPHY 268
++#define HCLK_HDCP_KEY 269
++#define ACLK_HDCP 270
++#define HCLK_HDCP 271
++#define PCLK_HDCP 272
++#define HCLK_CVBS 273
++#define DCLK_CVBS 274
++#define DCLK_4X_CVBS 275
++#define ACLK_JPEG_DECODER 276
++#define HCLK_JPEG_DECODER 277
++#define ACLK_VO_L_ROOT 278
++#define ACLK_VO_L_BIU 279
++#define ACLK_MAC_VO 280
++#define PCLK_MAC_VO 281
++#define CLK_GMAC0_SRC 282
++#define CLK_GMAC0_RMII_50M 283
++#define CLK_GMAC0_TX 284
++#define CLK_GMAC0_RX 285
++#define ACLK_JPEG_ROOT 286
++#define ACLK_JPEG_BIU 287
++#define HCLK_SAI_I2S3 288
++#define MCLK_SAI_I2S3 289
++#define CLK_MACPHY 290
++#define PCLK_VCDCPHY 291
++#define PCLK_GPIO2 292
++#define DBCLK_GPIO2 293
++#define PCLK_VO_IOC 294
++#define CCLK_SRC_SDMMC0 295
++#define HCLK_SDMMC0 296
++#define PCLK_OTPC_NS 297
++#define CLK_SBPI_OTPC_NS 298
++#define CLK_USER_OTPC_NS 299
++#define CLK_HDMIHDP0 300
++#define HCLK_USBHOST 301
++#define HCLK_USBHOST_ARB 302
++#define CLK_USBHOST_OHCI 303
++#define CLK_USBHOST_UTMI 304
++#define PCLK_UART4 305
++#define PCLK_I2C4 306
++#define CLK_I2C4 307
++#define PCLK_I2C7 308
++#define CLK_I2C7 309
++#define PCLK_USBPHY 310
++#define CLK_REF_USBPHY 311
++#define HCLK_RKVDEC_ROOT 312
++#define ACLK_RKVDEC_ROOT_NDFT 313
++#define PCLK_DDRPHY_CRU 314
++#define HCLK_RKVDEC_BIU 315
++#define ACLK_RKVDEC_BIU 316
++#define ACLK_RKVDEC 317
++#define HCLK_RKVDEC 318
++#define CLK_HEVC_CA_RKVDEC 319
++#define ACLK_RKVDEC_PVTMUX_ROOT 320
++#define CLK_RKVDEC_PVTPLL_SRC 321
++#define PCLK_DDR_ROOT 322
++#define PCLK_DDR_BIU 323
++#define PCLK_DDRC 324
++#define PCLK_DDRMON 325
++#define CLK_TIMER_DDRMON 326
++#define PCLK_MSCH_BIU 327
++#define PCLK_DDR_GRF 328
++#define PCLK_DDR_HWLP 329
++#define PCLK_DDRPHY 330
++#define CLK_MSCH_BIU 331
++#define ACLK_DDR_UPCTL 332
++#define CLK_DDR_UPCTL 333
++#define CLK_DDRMON 334
++#define ACLK_DDR_SCRAMBLE 335
++#define ACLK_SPLIT 336
++#define CLK_DDRC_SRC 337
++#define CLK_DDR_PHY 338
++#define PCLK_OTPC_S 339
++#define CLK_SBPI_OTPC_S 340
++#define CLK_USER_OTPC_S 341
++#define PCLK_KEYREADER 342
++#define PCLK_BUS_SGRF 343
++#define PCLK_STIMER 344
++#define CLK_STIMER0 345
++#define CLK_STIMER1 346
++#define PCLK_WDT_S 347
++#define TCLK_WDT_S 348
++#define HCLK_TRNG_S 349
++#define HCLK_BOOTROM 350
++#define PCLK_DCF 351
++#define ACLK_SYSMEM 352
++#define HCLK_TSP 353
++#define ACLK_TSP 354
++#define CLK_CORE_TSP 355
++#define CLK_OTPC_ARB 356
++#define PCLK_OTP_MASK 357
++#define CLK_PMC_OTP 358
++#define PCLK_PMU_ROOT 359
++#define HCLK_PMU_ROOT 360
++#define PCLK_I2C2 361
++#define CLK_I2C2 362
++#define HCLK_PMU_BIU 363
++#define PCLK_PMU_BIU 364
++#define FCLK_MCU 365
++#define RTC_CLK_MCU 366
++#define PCLK_OSCCHK 367
++#define CLK_PMU_MCU_JTAG 368
++#define PCLK_PMU 369
++#define PCLK_GPIO0 370
++#define DBCLK_GPIO0 371
++#define XIN_OSC0_DIV 372
++#define CLK_DEEPSLOW 373
++#define CLK_DDR_FAIL_SAFE 374
++#define PCLK_PMU_HP_TIMER 375
++#define CLK_PMU_HP_TIMER 376
++#define CLK_PMU_32K_HP_TIMER 377
++#define PCLK_PMU_IOC 378
++#define PCLK_PMU_CRU 379
++#define PCLK_PMU_GRF 380
++#define PCLK_PMU_WDT 381
++#define TCLK_PMU_WDT 382
++#define PCLK_PMU_MAILBOX 383
++#define PCLK_SCRKEYGEN 384
++#define CLK_SCRKEYGEN 385
++#define CLK_PVTM_OSCCHK 386
++#define CLK_REFOUT 387
++#define CLK_PVTM_PMU 388
++#define PCLK_PVTM_PMU 389
++#define PCLK_PMU_SGRF 390
++#define HCLK_PMU_SRAM 391
++#define CLK_UART0 392
++#define CLK_UART1 393
++#define CLK_UART2 394
++#define CLK_UART3 395
++#define CLK_UART4 396
++#define CLK_UART5 397
++#define CLK_UART6 398
++#define CLK_UART7 399
++#define MCLK_I2S0_2CH_SAI_SRC_PRE 400
++#define MCLK_I2S1_8CH_SAI_SRC_PRE 401
++#define MCLK_I2S2_2CH_SAI_SRC_PRE 402
++#define MCLK_I2S3_8CH_SAI_SRC_PRE 403
++#define MCLK_SDPDIF_SRC_PRE 404
++
++/* scmi-clocks indices */
++#define SCMI_PCLK_KEYREADER 0
++#define SCMI_HCLK_KLAD 1
++#define SCMI_PCLK_KLAD 2
++#define SCMI_HCLK_TRNG_S 3
++#define SCMI_HCLK_CRYPTO_S 4
++#define SCMI_PCLK_WDT_S 5
++#define SCMI_TCLK_WDT_S 6
++#define SCMI_PCLK_STIMER 7
++#define SCMI_CLK_STIMER0 8
++#define SCMI_CLK_STIMER1 9
++#define SCMI_PCLK_OTP_MASK 10
++#define SCMI_PCLK_OTPC_S 11
++#define SCMI_CLK_SBPI_OTPC_S 12
++#define SCMI_CLK_USER_OTPC_S 13
++#define SCMI_CLK_PMC_OTP 14
++#define SCMI_CLK_OTPC_ARB 15
++#define SCMI_CLK_CORE_TSP 16
++#define SCMI_ACLK_TSP 17
++#define SCMI_HCLK_TSP 18
++#define SCMI_PCLK_DCF 19
++#define SCMI_CLK_DDR 20
++#define SCMI_CLK_CPU 21
++#define SCMI_CLK_GPU 22
++#define SCMI_CORE_CRYPTO 23
++#define SCMI_ACLK_CRYPTO 24
++#define SCMI_PKA_CRYPTO 25
++#define SCMI_HCLK_CRYPTO 26
++#define SCMI_CORE_CRYPTO_S 27
++#define SCMI_ACLK_CRYPTO_S 28
++#define SCMI_PKA_CRYPTO_S 29
++#define SCMI_CORE_KLAD 30
++#define SCMI_ACLK_KLAD 31
++#define SCMI_HCLK_TRNG 32
++
++#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+--- /dev/null
++++ b/include/dt-bindings/reset/rockchip,rk3528-cru.h
+@@ -0,0 +1,241 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
++/*
++ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
++ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
++ * Author: Joseph Chen <chenjh@rock-chips.com>
++ */
++
++#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
++#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
++
++#define SRST_CORE0_PO 0
++#define SRST_CORE1_PO 1
++#define SRST_CORE2_PO 2
++#define SRST_CORE3_PO 3
++#define SRST_CORE0 4
++#define SRST_CORE1 5
++#define SRST_CORE2 6
++#define SRST_CORE3 7
++#define SRST_NL2 8
++#define SRST_CORE_BIU 9
++#define SRST_CORE_CRYPTO 10
++#define SRST_P_DBG 11
++#define SRST_POT_DBG 12
++#define SRST_NT_DBG 13
++#define SRST_P_CORE_GRF 14
++#define SRST_P_DAPLITE_BIU 15
++#define SRST_P_CPU_BIU 16
++#define SRST_REF_PVTPLL_CORE 17
++#define SRST_A_BUS_VOPGL_BIU 18
++#define SRST_A_BUS_H_BIU 19
++#define SRST_A_SYSMEM_BIU 20
++#define SRST_A_BUS_BIU 21
++#define SRST_H_BUS_BIU 22
++#define SRST_P_BUS_BIU 23
++#define SRST_P_DFT2APB 24
++#define SRST_P_BUS_GRF 25
++#define SRST_A_BUS_M_BIU 26
++#define SRST_A_GIC 27
++#define SRST_A_SPINLOCK 28
++#define SRST_A_DMAC 29
++#define SRST_P_TIMER 30
++#define SRST_TIMER0 31
++#define SRST_TIMER1 32
++#define SRST_TIMER2 33
++#define SRST_TIMER3 34
++#define SRST_TIMER4 35
++#define SRST_TIMER5 36
++#define SRST_P_JDBCK_DAP 37
++#define SRST_JDBCK_DAP 38
++#define SRST_P_WDT_NS 39
++#define SRST_T_WDT_NS 40
++#define SRST_H_TRNG_NS 41
++#define SRST_P_UART0 42
++#define SRST_S_UART0 43
++#define SRST_PKA_CRYPTO 44
++#define SRST_A_CRYPTO 45
++#define SRST_H_CRYPTO 46
++#define SRST_P_DMA2DDR 47
++#define SRST_A_DMA2DDR 48
++#define SRST_P_PWM0 49
++#define SRST_PWM0 50
++#define SRST_P_PWM1 51
++#define SRST_PWM1 52
++#define SRST_P_SCR 53
++#define SRST_A_DCF 54
++#define SRST_P_INTMUX 55
++#define SRST_A_VPU_BIU 56
++#define SRST_H_VPU_BIU 57
++#define SRST_P_VPU_BIU 58
++#define SRST_A_VPU 59
++#define SRST_H_VPU 60
++#define SRST_P_CRU_PCIE 61
++#define SRST_P_VPU_GRF 62
++#define SRST_H_SFC 63
++#define SRST_S_SFC 64
++#define SRST_C_EMMC 65
++#define SRST_H_EMMC 66
++#define SRST_A_EMMC 67
++#define SRST_B_EMMC 68
++#define SRST_T_EMMC 69
++#define SRST_P_GPIO1 70
++#define SRST_DB_GPIO1 71
++#define SRST_A_VPU_L_BIU 72
++#define SRST_P_VPU_IOC 73
++#define SRST_H_SAI_I2S0 74
++#define SRST_M_SAI_I2S0 75
++#define SRST_H_SAI_I2S2 76
++#define SRST_M_SAI_I2S2 77
++#define SRST_P_ACODEC 78
++#define SRST_P_GPIO3 79
++#define SRST_DB_GPIO3 80
++#define SRST_P_SPI1 81
++#define SRST_SPI1 82
++#define SRST_P_UART2 83
++#define SRST_S_UART2 84
++#define SRST_P_UART5 85
++#define SRST_S_UART5 86
++#define SRST_P_UART6 87
++#define SRST_S_UART6 88
++#define SRST_P_UART7 89
++#define SRST_S_UART7 90
++#define SRST_P_I2C3 91
++#define SRST_I2C3 92
++#define SRST_P_I2C5 93
++#define SRST_I2C5 94
++#define SRST_P_I2C6 95
++#define SRST_I2C6 96
++#define SRST_A_MAC 97
++#define SRST_P_PCIE 98
++#define SRST_PCIE_PIPE_PHY 99
++#define SRST_PCIE_POWER_UP 100
++#define SRST_P_PCIE_PHY 101
++#define SRST_P_PIPE_GRF 102
++#define SRST_H_SDIO0 103
++#define SRST_H_SDIO1 104
++#define SRST_TS_0 105
++#define SRST_TS_1 106
++#define SRST_P_CAN2 107
++#define SRST_CAN2 108
++#define SRST_P_CAN3 109
++#define SRST_CAN3 110
++#define SRST_P_SARADC 111
++#define SRST_SARADC 112
++#define SRST_SARADC_PHY 113
++#define SRST_P_TSADC 114
++#define SRST_TSADC 115
++#define SRST_A_USB3OTG 116
++#define SRST_A_GPU_BIU 117
++#define SRST_P_GPU_BIU 118
++#define SRST_A_GPU 119
++#define SRST_REF_PVTPLL_GPU 120
++#define SRST_H_RKVENC_BIU 121
++#define SRST_A_RKVENC_BIU 122
++#define SRST_P_RKVENC_BIU 123
++#define SRST_H_RKVENC 124
++#define SRST_A_RKVENC 125
++#define SRST_CORE_RKVENC 126
++#define SRST_H_SAI_I2S1 127
++#define SRST_M_SAI_I2S1 128
++#define SRST_P_I2C1 129
++#define SRST_I2C1 130
++#define SRST_P_I2C0 131
++#define SRST_I2C0 132
++#define SRST_P_SPI0 133
++#define SRST_SPI0 134
++#define SRST_P_GPIO4 135
++#define SRST_DB_GPIO4 136
++#define SRST_P_RKVENC_IOC 137
++#define SRST_H_SPDIF 138
++#define SRST_M_SPDIF 139
++#define SRST_H_PDM 140
++#define SRST_M_PDM 141
++#define SRST_P_UART1 142
++#define SRST_S_UART1 143
++#define SRST_P_UART3 144
++#define SRST_S_UART3 145
++#define SRST_P_RKVENC_GRF 146
++#define SRST_P_CAN0 147
++#define SRST_CAN0 148
++#define SRST_P_CAN1 149
++#define SRST_CAN1 150
++#define SRST_A_VO_BIU 151
++#define SRST_H_VO_BIU 152
++#define SRST_P_VO_BIU 153
++#define SRST_H_RGA2E 154
++#define SRST_A_RGA2E 155
++#define SRST_CORE_RGA2E 156
++#define SRST_H_VDPP 157
++#define SRST_A_VDPP 158
++#define SRST_CORE_VDPP 159
++#define SRST_P_VO_GRF 160
++#define SRST_P_CRU 161
++#define SRST_A_VOP_BIU 162
++#define SRST_H_VOP 163
++#define SRST_D_VOP0 164
++#define SRST_D_VOP1 165
++#define SRST_A_VOP 166
++#define SRST_P_HDMI 167
++#define SRST_HDMI 168
++#define SRST_P_HDMIPHY 169
++#define SRST_H_HDCP_KEY 170
++#define SRST_A_HDCP 171
++#define SRST_H_HDCP 172
++#define SRST_P_HDCP 173
++#define SRST_H_CVBS 174
++#define SRST_D_CVBS_VOP 175
++#define SRST_D_4X_CVBS_VOP 176
++#define SRST_A_JPEG_DECODER 177
++#define SRST_H_JPEG_DECODER 178
++#define SRST_A_VO_L_BIU 179
++#define SRST_A_MAC_VO 180
++#define SRST_A_JPEG_BIU 181
++#define SRST_H_SAI_I2S3 182
++#define SRST_M_SAI_I2S3 183
++#define SRST_MACPHY 184
++#define SRST_P_VCDCPHY 185
++#define SRST_P_GPIO2 186
++#define SRST_DB_GPIO2 187
++#define SRST_P_VO_IOC 188
++#define SRST_H_SDMMC0 189
++#define SRST_P_OTPC_NS 190
++#define SRST_SBPI_OTPC_NS 191
++#define SRST_USER_OTPC_NS 192
++#define SRST_HDMIHDP0 193
++#define SRST_H_USBHOST 194
++#define SRST_H_USBHOST_ARB 195
++#define SRST_HOST_UTMI 196
++#define SRST_P_UART4 197
++#define SRST_S_UART4 198
++#define SRST_P_I2C4 199
++#define SRST_I2C4 200
++#define SRST_P_I2C7 201
++#define SRST_I2C7 202
++#define SRST_P_USBPHY 203
++#define SRST_USBPHY_POR 204
++#define SRST_USBPHY_OTG 205
++#define SRST_USBPHY_HOST 206
++#define SRST_P_DDRPHY_CRU 207
++#define SRST_H_RKVDEC_BIU 208
++#define SRST_A_RKVDEC_BIU 209
++#define SRST_A_RKVDEC 210
++#define SRST_H_RKVDEC 211
++#define SRST_HEVC_CA_RKVDEC 212
++#define SRST_REF_PVTPLL_RKVDEC 213
++#define SRST_P_DDR_BIU 214
++#define SRST_P_DDRC 215
++#define SRST_P_DDRMON 216
++#define SRST_TIMER_DDRMON 217
++#define SRST_P_MSCH_BIU 218
++#define SRST_P_DDR_GRF 219
++#define SRST_P_DDR_HWLP 220
++#define SRST_P_DDRPHY 221
++#define SRST_MSCH_BIU 222
++#define SRST_A_DDR_UPCTL 223
++#define SRST_DDR_UPCTL 224
++#define SRST_DDRMON 225
++#define SRST_A_DDR_SCRAMBLE 226
++#define SRST_A_SPLIT 227
++#define SRST_DDR_PHY 228
++
++#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H
--- /dev/null
+From 651aabc9fb0f354ad2ba5fd06a6011e652447489 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Mon, 17 Feb 2025 06:11:43 +0000
+Subject: [PATCH] clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE
+
+RK3528 comes with a new PLL variant: its "PPLL", which mainly generates
+clocks for the PCIe controller, operates in normal mode only. Let's
+describe it with flag ROCKCHIP_PLL_FIXED_MODE and handle it in code.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20250217061142.38480-7-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-pll.c | 10 ++++++----
+ drivers/clk/rockchip/clk.h | 2 ++
+ 2 files changed, 8 insertions(+), 4 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-pll.c
++++ b/drivers/clk/rockchip/clk-pll.c
+@@ -204,10 +204,12 @@ static int rockchip_rk3036_pll_set_param
+ rockchip_rk3036_pll_get_params(pll, &cur);
+ cur.rate = 0;
+
+- cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
+- if (cur_parent == PLL_MODE_NORM) {
+- pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
+- rate_change_remuxed = 1;
++ if (!(pll->flags & ROCKCHIP_PLL_FIXED_MODE)) {
++ cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
++ if (cur_parent == PLL_MODE_NORM) {
++ pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
++ rate_change_remuxed = 1;
++ }
+ }
+
+ /* update pll values */
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -469,6 +469,7 @@ struct rockchip_pll_rate_table {
+ * Flags:
+ * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
+ * rate_table parameters and ajust them if necessary.
++ * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only
+ */
+ struct rockchip_pll_clock {
+ unsigned int id;
+@@ -486,6 +487,7 @@ struct rockchip_pll_clock {
+ };
+
+ #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
++#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
+
+ #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
+ _lshift, _pflags, _rtable) \
--- /dev/null
+From 5d0eb375e6857d270f6376d161ef02a1b7183fa2 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Mon, 17 Feb 2025 06:11:44 +0000
+Subject: [PATCH] clk: rockchip: Add clock controller driver for RK3528 SoC
+
+Add clock tree definition for RK3528. Similar to previous Rockchip
+SoCs, clock controller of RK3528 is combined with the reset controller.
+We omit the reset part for now since it's hard to test it without
+support for other basic peripherals.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20250217061142.38480-8-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/Kconfig | 7 +
+ drivers/clk/rockchip/Makefile | 1 +
+ drivers/clk/rockchip/clk-rk3528.c | 1114 +++++++++++++++++++++++++++++
+ drivers/clk/rockchip/clk.h | 20 +
+ 4 files changed, 1142 insertions(+)
+ create mode 100644 drivers/clk/rockchip/clk-rk3528.c
+
+--- a/drivers/clk/rockchip/Kconfig
++++ b/drivers/clk/rockchip/Kconfig
+@@ -93,6 +93,13 @@ config CLK_RK3399
+ help
+ Build the driver for RK3399 Clock Driver.
+
++config CLK_RK3528
++ bool "Rockchip RK3528 clock controller support"
++ depends on ARM64 || COMPILE_TEST
++ default y
++ help
++ Build the driver for RK3528 Clock Controller.
++
+ config CLK_RK3568
+ bool "Rockchip RK3568 clock controller support"
+ depends on ARM64 || COMPILE_TEST
+--- a/drivers/clk/rockchip/Makefile
++++ b/drivers/clk/rockchip/Makefile
+@@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_RK3308) += clk-r
+ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
+ obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
+ obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
++obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o
+ obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
+ obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o
+ obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o
+--- /dev/null
++++ b/drivers/clk/rockchip/clk-rk3528.c
+@@ -0,0 +1,1114 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
++ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
++ * Author: Joseph Chen <chenjh@rock-chips.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++
++#include <dt-bindings/clock/rockchip,rk3528-cru.h>
++
++#include "clk.h"
++
++#define RK3528_GRF_SOC_STATUS0 0x1a0
++
++enum rk3528_plls {
++ apll, cpll, gpll, ppll, dpll,
++};
++
++static struct rockchip_pll_rate_table rk3528_pll_rates[] = {
++ RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */
++ RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0),
++ RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
++ RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */
++ RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0),
++ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
++ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
++ RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
++ RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
++ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
++ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
++ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
++ RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0),
++ { /* sentinel */ },
++};
++
++#define RK3528_DIV_ACLK_M_CORE_MASK 0x1f
++#define RK3528_DIV_ACLK_M_CORE_SHIFT 11
++#define RK3528_DIV_PCLK_DBG_MASK 0x1f
++#define RK3528_DIV_PCLK_DBG_SHIFT 1
++
++#define RK3528_CLKSEL39(_aclk_m_core) \
++{ \
++ .reg = RK3528_CLKSEL_CON(39), \
++ .val = HIWORD_UPDATE(_aclk_m_core, RK3528_DIV_ACLK_M_CORE_MASK, \
++ RK3528_DIV_ACLK_M_CORE_SHIFT), \
++}
++
++#define RK3528_CLKSEL40(_pclk_dbg) \
++{ \
++ .reg = RK3528_CLKSEL_CON(40), \
++ .val = HIWORD_UPDATE(_pclk_dbg, RK3528_DIV_PCLK_DBG_MASK, \
++ RK3528_DIV_PCLK_DBG_SHIFT), \
++}
++
++#define RK3528_CPUCLK_RATE(_prate, _aclk_m_core, _pclk_dbg) \
++{ \
++ .prate = _prate, \
++ .divs = { \
++ RK3528_CLKSEL39(_aclk_m_core), \
++ RK3528_CLKSEL40(_pclk_dbg), \
++ }, \
++}
++
++static struct rockchip_cpuclk_rate_table rk3528_cpuclk_rates[] __initdata = {
++ RK3528_CPUCLK_RATE(1896000000, 1, 13),
++ RK3528_CPUCLK_RATE(1800000000, 1, 12),
++ RK3528_CPUCLK_RATE(1704000000, 1, 11),
++ RK3528_CPUCLK_RATE(1608000000, 1, 11),
++ RK3528_CPUCLK_RATE(1512000000, 1, 11),
++ RK3528_CPUCLK_RATE(1416000000, 1, 9),
++ RK3528_CPUCLK_RATE(1296000000, 1, 8),
++ RK3528_CPUCLK_RATE(1200000000, 1, 8),
++ RK3528_CPUCLK_RATE(1188000000, 1, 8),
++ RK3528_CPUCLK_RATE(1092000000, 1, 7),
++ RK3528_CPUCLK_RATE(1008000000, 1, 6),
++ RK3528_CPUCLK_RATE(1000000000, 1, 6),
++ RK3528_CPUCLK_RATE(996000000, 1, 6),
++ RK3528_CPUCLK_RATE(960000000, 1, 6),
++ RK3528_CPUCLK_RATE(912000000, 1, 6),
++ RK3528_CPUCLK_RATE(816000000, 1, 5),
++ RK3528_CPUCLK_RATE(600000000, 1, 3),
++ RK3528_CPUCLK_RATE(594000000, 1, 3),
++ RK3528_CPUCLK_RATE(408000000, 1, 2),
++ RK3528_CPUCLK_RATE(312000000, 1, 2),
++ RK3528_CPUCLK_RATE(216000000, 1, 1),
++ RK3528_CPUCLK_RATE(96000000, 1, 0),
++};
++
++static const struct rockchip_cpuclk_reg_data rk3528_cpuclk_data = {
++ .core_reg[0] = RK3528_CLKSEL_CON(39),
++ .div_core_shift[0] = 5,
++ .div_core_mask[0] = 0x1f,
++ .num_cores = 1,
++ .mux_core_alt = 1,
++ .mux_core_main = 0,
++ .mux_core_shift = 10,
++ .mux_core_mask = 0x1,
++};
++
++PNAME(mux_pll_p) = { "xin24m" };
++PNAME(mux_armclk) = { "apll", "gpll" };
++PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
++PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
++PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
++PNAME(mux_100m_50m_24m_p) = { "clk_100m_src", "clk_50m_src",
++ "xin24m" };
++PNAME(mux_150m_100m_24m_p) = { "clk_150m_src", "clk_100m_src",
++ "xin24m" };
++PNAME(mux_200m_100m_24m_p) = { "clk_200m_src", "clk_100m_src",
++ "xin24m" };
++PNAME(mux_200m_100m_50m_24m_p) = { "clk_200m_src", "clk_100m_src",
++ "clk_50m_src", "xin24m" };
++PNAME(mux_300m_200m_100m_24m_p) = { "clk_300m_src", "clk_200m_src",
++ "clk_100m_src", "xin24m" };
++PNAME(mux_339m_200m_100m_24m_p) = { "clk_339m_src", "clk_200m_src",
++ "clk_100m_src", "xin24m" };
++PNAME(mux_500m_200m_100m_24m_p) = { "clk_500m_src", "clk_200m_src",
++ "clk_100m_src", "xin24m" };
++PNAME(mux_500m_300m_100m_24m_p) = { "clk_500m_src", "clk_300m_src",
++ "clk_100m_src", "xin24m" };
++PNAME(mux_600m_300m_200m_24m_p) = { "clk_600m_src", "clk_300m_src",
++ "clk_200m_src", "xin24m" };
++PNAME(aclk_gpu_p) = { "aclk_gpu_root",
++ "clk_gpu_pvtpll_src" };
++PNAME(aclk_rkvdec_pvtmux_root_p) = { "aclk_rkvdec_root",
++ "clk_rkvdec_pvtpll_src" };
++PNAME(clk_i2c2_p) = { "clk_200m_src", "clk_100m_src",
++ "xin24m", "clk_32k" };
++PNAME(clk_ref_pcie_inner_phy_p) = { "clk_ppll_100m_src", "xin24m" };
++PNAME(dclk_vop0_p) = { "dclk_vop_src0",
++ "clk_hdmiphy_pixel_io" };
++PNAME(mclk_i2s0_2ch_sai_src_p) = { "clk_i2s0_2ch_src",
++ "clk_i2s0_2ch_frac", "xin12m" };
++PNAME(mclk_i2s1_8ch_sai_src_p) = { "clk_i2s1_8ch_src",
++ "clk_i2s1_8ch_frac", "xin12m" };
++PNAME(mclk_i2s2_2ch_sai_src_p) = { "clk_i2s2_2ch_src",
++ "clk_i2s2_2ch_frac", "xin12m" };
++PNAME(mclk_i2s3_8ch_sai_src_p) = { "clk_i2s3_8ch_src",
++ "clk_i2s3_8ch_frac", "xin12m" };
++PNAME(mclk_sai_i2s0_p) = { "mclk_i2s0_2ch_sai_src",
++ "i2s0_mclkin" };
++PNAME(mclk_sai_i2s1_p) = { "mclk_i2s1_8ch_sai_src",
++ "i2s1_mclkin" };
++PNAME(mclk_spdif_src_p) = { "clk_spdif_src", "clk_spdif_frac",
++ "xin12m" };
++PNAME(sclk_uart0_src_p) = { "clk_uart0_src", "clk_uart0_frac",
++ "xin24m" };
++PNAME(sclk_uart1_src_p) = { "clk_uart1_src", "clk_uart1_frac",
++ "xin24m" };
++PNAME(sclk_uart2_src_p) = { "clk_uart2_src", "clk_uart2_frac",
++ "xin24m" };
++PNAME(sclk_uart3_src_p) = { "clk_uart3_src", "clk_uart3_frac",
++ "xin24m" };
++PNAME(sclk_uart4_src_p) = { "clk_uart4_src", "clk_uart4_frac",
++ "xin24m" };
++PNAME(sclk_uart5_src_p) = { "clk_uart5_src", "clk_uart5_frac",
++ "xin24m" };
++PNAME(sclk_uart6_src_p) = { "clk_uart6_src", "clk_uart6_frac",
++ "xin24m" };
++PNAME(sclk_uart7_src_p) = { "clk_uart7_src", "clk_uart7_frac",
++ "xin24m" };
++PNAME(clk_32k_p) = { "xin_osc0_div", "clk_pvtm_32k" };
++
++static struct rockchip_pll_clock rk3528_pll_clks[] __initdata = {
++ [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
++ CLK_IS_CRITICAL, RK3528_PLL_CON(0),
++ RK3528_MODE_CON, 0, 0, 0, rk3528_pll_rates),
++
++ [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
++ CLK_IS_CRITICAL, RK3528_PLL_CON(8),
++ RK3528_MODE_CON, 2, 0, 0, rk3528_pll_rates),
++
++ [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
++ CLK_IS_CRITICAL, RK3528_PLL_CON(24),
++ RK3528_MODE_CON, 4, 0, 0, rk3528_pll_rates),
++
++ [ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll", mux_pll_p,
++ CLK_IS_CRITICAL, RK3528_PCIE_PLL_CON(32),
++ RK3528_MODE_CON, 6, 0, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates),
++
++ [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
++ CLK_IGNORE_UNUSED, RK3528_DDRPHY_PLL_CON(16),
++ RK3528_DDRPHY_MODE_CON, 0, 0, 0, rk3528_pll_rates),
++};
++
++#define MFLAGS CLK_MUX_HIWORD_MASK
++#define DFLAGS CLK_DIVIDER_HIWORD_MASK
++#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
++
++static struct rockchip_clk_branch rk3528_uart0_fracmux __initdata =
++ MUX(CLK_UART0, "clk_uart0", sclk_uart0_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(6), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3528_uart1_fracmux __initdata =
++ MUX(CLK_UART1, "clk_uart1", sclk_uart1_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(8), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3528_uart2_fracmux __initdata =
++ MUX(CLK_UART2, "clk_uart2", sclk_uart2_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(10), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3528_uart3_fracmux __initdata =
++ MUX(CLK_UART3, "clk_uart3", sclk_uart3_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(12), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3528_uart4_fracmux __initdata =
++ MUX(CLK_UART4, "clk_uart4", sclk_uart4_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(14), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3528_uart5_fracmux __initdata =
++ MUX(CLK_UART5, "clk_uart5", sclk_uart5_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(16), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3528_uart6_fracmux __initdata =
++ MUX(CLK_UART6, "clk_uart6", sclk_uart6_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(18), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3528_uart7_fracmux __initdata =
++ MUX(CLK_UART7, "clk_uart7", sclk_uart7_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(20), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch mclk_i2s0_2ch_sai_src_fracmux __initdata =
++ MUX(MCLK_I2S0_2CH_SAI_SRC_PRE, "mclk_i2s0_2ch_sai_src_pre", mclk_i2s0_2ch_sai_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(22), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch mclk_i2s1_8ch_sai_src_fracmux __initdata =
++ MUX(MCLK_I2S1_8CH_SAI_SRC_PRE, "mclk_i2s1_8ch_sai_src_pre", mclk_i2s1_8ch_sai_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(26), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch mclk_i2s2_2ch_sai_src_fracmux __initdata =
++ MUX(MCLK_I2S2_2CH_SAI_SRC_PRE, "mclk_i2s2_2ch_sai_src_pre", mclk_i2s2_2ch_sai_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(28), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch mclk_i2s3_8ch_sai_src_fracmux __initdata =
++ MUX(MCLK_I2S3_8CH_SAI_SRC_PRE, "mclk_i2s3_8ch_sai_src_pre", mclk_i2s3_8ch_sai_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(24), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch mclk_spdif_src_fracmux __initdata =
++ MUX(MCLK_SDPDIF_SRC_PRE, "mclk_spdif_src_pre", mclk_spdif_src_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(32), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3528_clk_branches[] __initdata = {
++ /* top */
++ FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
++
++ COMPOSITE(CLK_MATRIX_250M_SRC, "clk_250m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(1), 15, 1, MFLAGS, 10, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 5, GFLAGS),
++ COMPOSITE(CLK_MATRIX_500M_SRC, "clk_500m_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 10, GFLAGS),
++ COMPOSITE_NOMUX(CLK_MATRIX_50M_SRC, "clk_50m_src", "cpll", CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(0), 2, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 1, GFLAGS),
++ COMPOSITE_NOMUX(CLK_MATRIX_100M_SRC, "clk_100m_src", "cpll", CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(0), 7, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 2, GFLAGS),
++ COMPOSITE_NOMUX(CLK_MATRIX_150M_SRC, "clk_150m_src", "gpll", CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(1), 0, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 3, GFLAGS),
++ COMPOSITE_NOMUX(CLK_MATRIX_200M_SRC, "clk_200m_src", "gpll", CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(1), 5, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 4, GFLAGS),
++ COMPOSITE_NOMUX(CLK_MATRIX_300M_SRC, "clk_300m_src", "gpll", CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(2), 0, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 6, GFLAGS),
++ COMPOSITE_NOMUX_HALFDIV(CLK_MATRIX_339M_SRC, "clk_339m_src", "gpll", CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(2), 5, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 7, GFLAGS),
++ COMPOSITE_NOMUX(CLK_MATRIX_400M_SRC, "clk_400m_src", "gpll", CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(2), 10, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 8, GFLAGS),
++ COMPOSITE_NOMUX(CLK_MATRIX_600M_SRC, "clk_600m_src", "gpll", CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(4), 0, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 11, GFLAGS),
++ COMPOSITE(DCLK_VOP_SRC0, "dclk_vop_src0", mux_gpll_cpll_p, 0,
++ RK3528_CLKSEL_CON(32), 10, 1, MFLAGS, 2, 8, DFLAGS,
++ RK3528_CLKGATE_CON(3), 7, GFLAGS),
++ COMPOSITE(DCLK_VOP_SRC1, "dclk_vop_src1", mux_gpll_cpll_p, 0,
++ RK3528_CLKSEL_CON(33), 8, 1, MFLAGS, 0, 8, DFLAGS,
++ RK3528_CLKGATE_CON(3), 8, GFLAGS),
++ COMPOSITE_NOMUX(CLK_HSM, "clk_hsm", "xin24m", 0,
++ RK3528_CLKSEL_CON(36), 5, 5, DFLAGS,
++ RK3528_CLKGATE_CON(3), 13, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "gpll", 0,
++ RK3528_CLKSEL_CON(4), 5, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 12, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(5), 0,
++ RK3528_CLKGATE_CON(0), 13, GFLAGS,
++ &rk3528_uart0_fracmux),
++ GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
++ RK3528_CLKGATE_CON(0), 14, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_UART1_SRC, "clk_uart1_src", "gpll", 0,
++ RK3528_CLKSEL_CON(6), 2, 5, DFLAGS,
++ RK3528_CLKGATE_CON(0), 15, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(7), 0,
++ RK3528_CLKGATE_CON(1), 0, GFLAGS,
++ &rk3528_uart1_fracmux),
++ GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
++ RK3528_CLKGATE_CON(1), 1, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_UART2_SRC, "clk_uart2_src", "gpll", 0,
++ RK3528_CLKSEL_CON(8), 2, 5, DFLAGS,
++ RK3528_CLKGATE_CON(1), 2, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(9), 0,
++ RK3528_CLKGATE_CON(1), 3, GFLAGS,
++ &rk3528_uart2_fracmux),
++ GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
++ RK3528_CLKGATE_CON(1), 4, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_UART3_SRC, "clk_uart3_src", "gpll", 0,
++ RK3528_CLKSEL_CON(10), 2, 5, DFLAGS,
++ RK3528_CLKGATE_CON(1), 5, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(11), 0,
++ RK3528_CLKGATE_CON(1), 6, GFLAGS,
++ &rk3528_uart3_fracmux),
++ GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
++ RK3528_CLKGATE_CON(1), 7, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_UART4_SRC, "clk_uart4_src", "gpll", 0,
++ RK3528_CLKSEL_CON(12), 2, 5, DFLAGS,
++ RK3528_CLKGATE_CON(1), 8, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(13), 0,
++ RK3528_CLKGATE_CON(1), 9, GFLAGS,
++ &rk3528_uart4_fracmux),
++ GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
++ RK3528_CLKGATE_CON(1), 10, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_UART5_SRC, "clk_uart5_src", "gpll", 0,
++ RK3528_CLKSEL_CON(14), 2, 5, DFLAGS,
++ RK3528_CLKGATE_CON(1), 11, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(15), 0,
++ RK3528_CLKGATE_CON(1), 12, GFLAGS,
++ &rk3528_uart5_fracmux),
++ GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
++ RK3528_CLKGATE_CON(1), 13, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_UART6_SRC, "clk_uart6_src", "gpll", 0,
++ RK3528_CLKSEL_CON(16), 2, 5, DFLAGS,
++ RK3528_CLKGATE_CON(1), 14, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(17), 0,
++ RK3528_CLKGATE_CON(1), 15, GFLAGS,
++ &rk3528_uart6_fracmux),
++ GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
++ RK3528_CLKGATE_CON(2), 0, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_UART7_SRC, "clk_uart7_src", "gpll", 0,
++ RK3528_CLKSEL_CON(18), 2, 5, DFLAGS,
++ RK3528_CLKGATE_CON(2), 1, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(19), 0,
++ RK3528_CLKGATE_CON(2), 2, GFLAGS,
++ &rk3528_uart7_fracmux),
++ GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
++ RK3528_CLKGATE_CON(2), 3, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_I2S0_2CH_SRC, "clk_i2s0_2ch_src", "gpll", 0,
++ RK3528_CLKSEL_CON(20), 8, 5, DFLAGS,
++ RK3528_CLKGATE_CON(2), 5, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_I2S0_2CH_FRAC, "clk_i2s0_2ch_frac", "clk_i2s0_2ch_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(21), 0,
++ RK3528_CLKGATE_CON(2), 6, GFLAGS,
++ &mclk_i2s0_2ch_sai_src_fracmux),
++ GATE(MCLK_I2S0_2CH_SAI_SRC, "mclk_i2s0_2ch_sai_src", "mclk_i2s0_2ch_sai_src_pre", 0,
++ RK3528_CLKGATE_CON(2), 7, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_I2S1_8CH_SRC, "clk_i2s1_8ch_src", "gpll", 0,
++ RK3528_CLKSEL_CON(24), 3, 5, DFLAGS,
++ RK3528_CLKGATE_CON(2), 11, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_I2S1_8CH_FRAC, "clk_i2s1_8ch_frac", "clk_i2s1_8ch_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(25), 0,
++ RK3528_CLKGATE_CON(2), 12, GFLAGS,
++ &mclk_i2s1_8ch_sai_src_fracmux),
++ GATE(MCLK_I2S1_8CH_SAI_SRC, "mclk_i2s1_8ch_sai_src", "mclk_i2s1_8ch_sai_src_pre", 0,
++ RK3528_CLKGATE_CON(2), 13, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", "gpll", 0,
++ RK3528_CLKSEL_CON(26), 3, 5, DFLAGS,
++ RK3528_CLKGATE_CON(2), 14, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(27), 0,
++ RK3528_CLKGATE_CON(2), 15, GFLAGS,
++ &mclk_i2s2_2ch_sai_src_fracmux),
++ GATE(MCLK_I2S2_2CH_SAI_SRC, "mclk_i2s2_2ch_sai_src", "mclk_i2s2_2ch_sai_src_pre", 0,
++ RK3528_CLKGATE_CON(3), 0, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_I2S3_8CH_SRC, "clk_i2s3_8ch_src", "gpll", 0,
++ RK3528_CLKSEL_CON(22), 3, 5, DFLAGS,
++ RK3528_CLKGATE_CON(2), 8, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_I2S3_8CH_FRAC, "clk_i2s3_8ch_frac", "clk_i2s3_8ch_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(23), 0,
++ RK3528_CLKGATE_CON(2), 9, GFLAGS,
++ &mclk_i2s3_8ch_sai_src_fracmux),
++ GATE(MCLK_I2S3_8CH_SAI_SRC, "mclk_i2s3_8ch_sai_src", "mclk_i2s3_8ch_sai_src_pre", 0,
++ RK3528_CLKGATE_CON(2), 10, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_SPDIF_SRC, "clk_spdif_src", "gpll", 0,
++ RK3528_CLKSEL_CON(30), 2, 5, DFLAGS,
++ RK3528_CLKGATE_CON(3), 4, GFLAGS),
++ COMPOSITE_FRACMUX(CLK_SPDIF_FRAC, "clk_spdif_frac", "clk_spdif_src", CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(31), 0,
++ RK3528_CLKGATE_CON(3), 5, GFLAGS,
++ &mclk_spdif_src_fracmux),
++ GATE(MCLK_SPDIF_SRC, "mclk_spdif_src", "mclk_spdif_src_pre", 0,
++ RK3528_CLKGATE_CON(3), 6, GFLAGS),
++
++ /* bus */
++ COMPOSITE_NODIV(ACLK_BUS_M_ROOT, "aclk_bus_m_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(43), 12, 2, MFLAGS,
++ RK3528_CLKGATE_CON(8), 7, GFLAGS),
++ GATE(ACLK_GIC, "aclk_gic", "aclk_bus_m_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(9), 1, GFLAGS),
++
++ COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(43), 6, 2, MFLAGS,
++ RK3528_CLKGATE_CON(8), 4, GFLAGS),
++ GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0,
++ RK3528_CLKGATE_CON(9), 2, GFLAGS),
++ GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_root", 0,
++ RK3528_CLKGATE_CON(9), 4, GFLAGS),
++ GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0,
++ RK3528_CLKGATE_CON(11), 11, GFLAGS),
++ COMPOSITE(ACLK_BUS_VOPGL_ROOT, "aclk_bus_vopgl_root", mux_gpll_cpll_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(43), 3, 1, MFLAGS, 0, 3, DFLAGS,
++ RK3528_CLKGATE_CON(8), 0, GFLAGS),
++ COMPOSITE_NODIV(ACLK_BUS_H_ROOT, "aclk_bus_h_root", mux_500m_200m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(43), 4, 2, MFLAGS,
++ RK3528_CLKGATE_CON(8), 2, GFLAGS),
++ GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_h_root", 0,
++ RK3528_CLKGATE_CON(10), 14, GFLAGS),
++
++ COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(43), 8, 2, MFLAGS,
++ RK3528_CLKGATE_CON(8), 5, GFLAGS),
++
++ COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(43), 10, 2, MFLAGS,
++ RK3528_CLKGATE_CON(8), 6, GFLAGS),
++ GATE(PCLK_DFT2APB, "pclk_dft2apb", "pclk_bus_root", 0,
++ RK3528_CLKGATE_CON(8), 13, GFLAGS),
++ GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(8), 15, GFLAGS),
++ GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0,
++ RK3528_CLKGATE_CON(9), 5, GFLAGS),
++ GATE(PCLK_JDBCK_DAP, "pclk_jdbck_dap", "pclk_bus_root", 0,
++ RK3528_CLKGATE_CON(9), 12, GFLAGS),
++ GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0,
++ RK3528_CLKGATE_CON(9), 15, GFLAGS),
++ GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0,
++ RK3528_CLKGATE_CON(10), 7, GFLAGS),
++ GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0,
++ RK3528_CLKGATE_CON(11), 4, GFLAGS),
++ GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0,
++ RK3528_CLKGATE_CON(11), 7, GFLAGS),
++ GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", 0,
++ RK3528_CLKGATE_CON(10), 13, GFLAGS),
++ GATE(PCLK_SCR, "pclk_scr", "pclk_bus_root", 0,
++ RK3528_CLKGATE_CON(11), 10, GFLAGS),
++ GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", CLK_IGNORE_UNUSED,
++ RK3528_CLKGATE_CON(11), 12, GFLAGS),
++
++ COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(44), 6, 2, MFLAGS,
++ RK3528_CLKGATE_CON(11), 5, GFLAGS),
++ COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(44), 8, 2, MFLAGS,
++ RK3528_CLKGATE_CON(11), 8, GFLAGS),
++
++ GATE(CLK_CAPTURE_PWM1, "clk_capture_pwm1", "xin24m", 0,
++ RK3528_CLKGATE_CON(11), 9, GFLAGS),
++ GATE(CLK_CAPTURE_PWM0, "clk_capture_pwm0", "xin24m", 0,
++ RK3528_CLKGATE_CON(11), 6, GFLAGS),
++ GATE(CLK_JDBCK_DAP, "clk_jdbck_dap", "xin24m", 0,
++ RK3528_CLKGATE_CON(9), 13, GFLAGS),
++ GATE(TCLK_WDT_NS, "tclk_wdt_ns", "xin24m", 0,
++ RK3528_CLKGATE_CON(10), 0, GFLAGS),
++
++ GATE(CLK_TIMER_ROOT, "clk_timer_root", "xin24m", 0,
++ RK3528_CLKGATE_CON(8), 9, GFLAGS),
++ GATE(CLK_TIMER0, "clk_timer0", "clk_timer_root", 0,
++ RK3528_CLKGATE_CON(9), 6, GFLAGS),
++ GATE(CLK_TIMER1, "clk_timer1", "clk_timer_root", 0,
++ RK3528_CLKGATE_CON(9), 7, GFLAGS),
++ GATE(CLK_TIMER2, "clk_timer2", "clk_timer_root", 0,
++ RK3528_CLKGATE_CON(9), 8, GFLAGS),
++ GATE(CLK_TIMER3, "clk_timer3", "clk_timer_root", 0,
++ RK3528_CLKGATE_CON(9), 9, GFLAGS),
++ GATE(CLK_TIMER4, "clk_timer4", "clk_timer_root", 0,
++ RK3528_CLKGATE_CON(9), 10, GFLAGS),
++ GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", 0,
++ RK3528_CLKGATE_CON(9), 11, GFLAGS),
++
++ /* pmu */
++ GATE(HCLK_PMU_ROOT, "hclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED,
++ RK3528_PMU_CLKGATE_CON(0), 1, GFLAGS),
++ GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "clk_100m_src", CLK_IGNORE_UNUSED,
++ RK3528_PMU_CLKGATE_CON(0), 0, GFLAGS),
++
++ GATE(FCLK_MCU, "fclk_mcu", "hclk_pmu_root", 0,
++ RK3528_PMU_CLKGATE_CON(0), 7, GFLAGS),
++ GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "hclk_pmu_root", CLK_IS_CRITICAL,
++ RK3528_PMU_CLKGATE_CON(5), 4, GFLAGS),
++
++ GATE(PCLK_I2C2, "pclk_i2c2", "pclk_pmu_root", 0,
++ RK3528_PMU_CLKGATE_CON(0), 2, GFLAGS),
++ GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", 0,
++ RK3528_PMU_CLKGATE_CON(1), 2, GFLAGS),
++ GATE(PCLK_PMU_IOC, "pclk_pmu_ioc", "pclk_pmu_root", CLK_IS_CRITICAL,
++ RK3528_PMU_CLKGATE_CON(1), 5, GFLAGS),
++ GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IS_CRITICAL,
++ RK3528_PMU_CLKGATE_CON(1), 6, GFLAGS),
++ GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IS_CRITICAL,
++ RK3528_PMU_CLKGATE_CON(1), 7, GFLAGS),
++ GATE(PCLK_PMU_WDT, "pclk_pmu_wdt", "pclk_pmu_root", 0,
++ RK3528_PMU_CLKGATE_CON(1), 10, GFLAGS),
++ GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IS_CRITICAL,
++ RK3528_PMU_CLKGATE_CON(0), 13, GFLAGS),
++ GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0,
++ RK3528_PMU_CLKGATE_CON(0), 14, GFLAGS),
++ GATE(PCLK_OSCCHK, "pclk_oscchk", "pclk_pmu_root", 0,
++ RK3528_PMU_CLKGATE_CON(0), 9, GFLAGS),
++ GATE(PCLK_PMU_MAILBOX, "pclk_pmu_mailbox", "pclk_pmu_root", 0,
++ RK3528_PMU_CLKGATE_CON(1), 12, GFLAGS),
++ GATE(PCLK_SCRKEYGEN, "pclk_scrkeygen", "pclk_pmu_root", 0,
++ RK3528_PMU_CLKGATE_CON(1), 15, GFLAGS),
++ GATE(PCLK_PVTM_PMU, "pclk_pvtm_pmu", "pclk_pmu_root", 0,
++ RK3528_PMU_CLKGATE_CON(5), 1, GFLAGS),
++
++ COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", clk_i2c2_p, 0,
++ RK3528_PMU_CLKSEL_CON(0), 0, 2, MFLAGS,
++ RK3528_PMU_CLKGATE_CON(0), 3, GFLAGS),
++
++ GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
++ RK3528_PMU_CLKGATE_CON(2), 4, GFLAGS),
++ COMPOSITE_NOMUX(CLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0,
++ RK3528_PMU_CLKSEL_CON(5), 0, 5, DFLAGS,
++ RK3528_PMU_CLKGATE_CON(5), 0, GFLAGS),
++
++ COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", 0,
++ RK3528_PMU_CLKSEL_CON(1), 0,
++ RK3528_PMU_CLKGATE_CON(1), 0, GFLAGS),
++ /* clk_32k: internal! No path from external osc 32k */
++ MUX(CLK_DEEPSLOW, "clk_32k", clk_32k_p, CLK_IS_CRITICAL,
++ RK3528_PMU_CLKSEL_CON(2), 0, 1, MFLAGS),
++ GATE(RTC_CLK_MCU, "rtc_clk_mcu", "clk_32k", 0,
++ RK3528_PMU_CLKGATE_CON(0), 8, GFLAGS),
++ GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "xin24m", CLK_IGNORE_UNUSED,
++ RK3528_PMU_CLKGATE_CON(1), 1, GFLAGS),
++
++ COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0,
++ RK3528_PMU_CLKSEL_CON(0), 2, 1, MFLAGS,
++ RK3528_PMU_CLKGATE_CON(0), 15, GFLAGS),
++ COMPOSITE_NODIV(TCLK_PMU_WDT, "tclk_pmu_wdt", mux_24m_32k_p, 0,
++ RK3528_PMU_CLKSEL_CON(2), 1, 1, MFLAGS,
++ RK3528_PMU_CLKGATE_CON(1), 11, GFLAGS),
++
++ /* core */
++ COMPOSITE_NOMUX(ACLK_M_CORE_BIU, "aclk_m_core", "armclk", CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(39), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
++ RK3528_CLKGATE_CON(5), 12, GFLAGS),
++ COMPOSITE_NOMUX(PCLK_DBG, "pclk_dbg", "armclk", CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(40), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
++ RK3528_CLKGATE_CON(5), 13, GFLAGS),
++ GATE(PCLK_CPU_ROOT, "pclk_cpu_root", "pclk_dbg", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(6), 1, GFLAGS),
++ GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_cpu_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(6), 2, GFLAGS),
++
++ /* ddr */
++ GATE(CLK_DDRC_SRC, "clk_ddrc_src", "dpll", CLK_IS_CRITICAL,
++ RK3528_DDRPHY_CLKGATE_CON(0), 0, GFLAGS),
++ GATE(CLK_DDR_PHY, "clk_ddr_phy", "dpll", CLK_IS_CRITICAL,
++ RK3528_DDRPHY_CLKGATE_CON(0), 1, GFLAGS),
++
++ COMPOSITE_NODIV(PCLK_DDR_ROOT, "pclk_ddr_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(90), 0, 2, MFLAGS,
++ RK3528_CLKGATE_CON(45), 0, GFLAGS),
++ GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IGNORE_UNUSED,
++ RK3528_CLKGATE_CON(45), 3, GFLAGS),
++ GATE(PCLK_DDR_HWLP, "pclk_ddr_hwlp", "pclk_ddr_root", CLK_IGNORE_UNUSED,
++ RK3528_CLKGATE_CON(45), 8, GFLAGS),
++ GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
++ RK3528_CLKGATE_CON(45), 4, GFLAGS),
++
++ GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(45), 2, GFLAGS),
++ GATE(PCLK_DDR_GRF, "pclk_ddr_grf", "pclk_ddr_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(45), 6, GFLAGS),
++ GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(45), 9, GFLAGS),
++
++ GATE(ACLK_DDR_UPCTL, "aclk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(45), 11, GFLAGS),
++ GATE(CLK_DDR_UPCTL, "clk_ddr_upctl", "clk_ddrc_src", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(45), 12, GFLAGS),
++ GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(45), 13, GFLAGS),
++ GATE(ACLK_DDR_SCRAMBLE, "aclk_ddr_scramble", "clk_ddrc_src", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(45), 14, GFLAGS),
++ GATE(ACLK_SPLIT, "aclk_split", "clk_ddrc_src", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(45), 15, GFLAGS),
++
++ /* gpu */
++ COMPOSITE_NODIV(ACLK_GPU_ROOT, "aclk_gpu_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(76), 0, 2, MFLAGS,
++ RK3528_CLKGATE_CON(34), 0, GFLAGS),
++ COMPOSITE_NODIV(ACLK_GPU, "aclk_gpu", aclk_gpu_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(76), 6, 1, MFLAGS,
++ RK3528_CLKGATE_CON(34), 7, GFLAGS),
++ GATE(ACLK_GPU_MALI, "aclk_gpu_mali", "aclk_gpu", 0,
++ RK3528_CLKGATE_CON(34), 8, GFLAGS),
++ COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(76), 4, 2, MFLAGS,
++ RK3528_CLKGATE_CON(34), 2, GFLAGS),
++
++ /* rkvdec */
++ COMPOSITE_NODIV(ACLK_RKVDEC_ROOT_NDFT, "aclk_rkvdec_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(88), 6, 2, MFLAGS,
++ RK3528_CLKGATE_CON(44), 3, GFLAGS),
++ COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(88), 4, 2, MFLAGS,
++ RK3528_CLKGATE_CON(44), 2, GFLAGS),
++ GATE(PCLK_DDRPHY_CRU, "pclk_ddrphy_cru", "hclk_rkvdec_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(44), 4, GFLAGS),
++ GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0,
++ RK3528_CLKGATE_CON(44), 9, GFLAGS),
++ COMPOSITE_NODIV(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", mux_600m_300m_200m_24m_p, 0,
++ RK3528_CLKSEL_CON(88), 11, 2, MFLAGS,
++ RK3528_CLKGATE_CON(44), 11, GFLAGS),
++ MUX(ACLK_RKVDEC_PVTMUX_ROOT, "aclk_rkvdec_pvtmux_root", aclk_rkvdec_pvtmux_root_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(88), 13, 1, MFLAGS),
++ GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pvtmux_root", 0,
++ RK3528_CLKGATE_CON(44), 8, GFLAGS),
++
++ /* rkvenc */
++ COMPOSITE_NODIV(ACLK_RKVENC_ROOT, "aclk_rkvenc_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(79), 2, 2, MFLAGS,
++ RK3528_CLKGATE_CON(36), 1, GFLAGS),
++ GATE(ACLK_RKVENC, "aclk_rkvenc", "aclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(36), 7, GFLAGS),
++
++ COMPOSITE_NODIV(PCLK_RKVENC_ROOT, "pclk_rkvenc_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(79), 4, 2, MFLAGS,
++ RK3528_CLKGATE_CON(36), 2, GFLAGS),
++ GATE(PCLK_RKVENC_IOC, "pclk_rkvenc_ioc", "pclk_rkvenc_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(37), 10, GFLAGS),
++ GATE(PCLK_RKVENC_GRF, "pclk_rkvenc_grf", "pclk_rkvenc_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(38), 6, GFLAGS),
++ GATE(PCLK_I2C1, "pclk_i2c1", "pclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(36), 11, GFLAGS),
++ GATE(PCLK_I2C0, "pclk_i2c0", "pclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(36), 13, GFLAGS),
++ GATE(PCLK_SPI0, "pclk_spi0", "pclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(37), 2, GFLAGS),
++ GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(37), 8, GFLAGS),
++ GATE(PCLK_UART1, "pclk_uart1", "pclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(38), 2, GFLAGS),
++ GATE(PCLK_UART3, "pclk_uart3", "pclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(38), 4, GFLAGS),
++ GATE(PCLK_CAN0, "pclk_can0", "pclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(38), 7, GFLAGS),
++ GATE(PCLK_CAN1, "pclk_can1", "pclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(38), 9, GFLAGS),
++
++ COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mux_150m_100m_24m_p, 0,
++ RK3528_CLKSEL_CON(80), 12, 2, MFLAGS,
++ RK3528_CLKGATE_CON(38), 1, GFLAGS),
++ COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_p, 0,
++ RK3528_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS,
++ RK3528_CLKGATE_CON(38), 8, GFLAGS),
++ COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_p, 0,
++ RK3528_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS,
++ RK3528_CLKGATE_CON(38), 10, GFLAGS),
++
++ COMPOSITE_NODIV(HCLK_RKVENC_ROOT, "hclk_rkvenc_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(79), 0, 2, MFLAGS,
++ RK3528_CLKGATE_CON(36), 0, GFLAGS),
++ GATE(HCLK_SAI_I2S1, "hclk_sai_i2s1", "hclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(36), 9, GFLAGS),
++ GATE(HCLK_SPDIF, "hclk_spdif", "hclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(37), 14, GFLAGS),
++ GATE(HCLK_PDM, "hclk_pdm", "hclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(38), 0, GFLAGS),
++ GATE(HCLK_RKVENC, "hclk_rkvenc", "hclk_rkvenc_root", 0,
++ RK3528_CLKGATE_CON(36), 6, GFLAGS),
++
++ COMPOSITE_NODIV(CLK_CORE_RKVENC, "clk_core_rkvenc", mux_300m_200m_100m_24m_p, 0,
++ RK3528_CLKSEL_CON(79), 6, 2, MFLAGS,
++ RK3528_CLKGATE_CON(36), 8, GFLAGS),
++ COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_200m_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(79), 11, 2, MFLAGS,
++ RK3528_CLKGATE_CON(36), 14, GFLAGS),
++ COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(79), 9, 2, MFLAGS,
++ RK3528_CLKGATE_CON(36), 12, GFLAGS),
++
++ COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(79), 13, 2, MFLAGS,
++ RK3528_CLKGATE_CON(37), 3, GFLAGS),
++ COMPOSITE_NODIV(MCLK_SAI_I2S1, "mclk_sai_i2s1", mclk_sai_i2s1_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(79), 8, 1, MFLAGS,
++ RK3528_CLKGATE_CON(36), 10, GFLAGS),
++ GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
++ RK3528_CLKGATE_CON(37), 9, GFLAGS),
++
++ /* vo */
++ COMPOSITE_NODIV(HCLK_VO_ROOT, "hclk_vo_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(83), 2, 2, MFLAGS,
++ RK3528_CLKGATE_CON(39), 1, GFLAGS),
++ GATE(HCLK_VOP, "hclk_vop", "hclk_vo_root", 0,
++ RK3528_CLKGATE_CON(40), 2, GFLAGS),
++ GATE(HCLK_USBHOST, "hclk_usbhost", "hclk_vo_root", 0,
++ RK3528_CLKGATE_CON(43), 3, GFLAGS),
++ GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vo_root", 0,
++ RK3528_CLKGATE_CON(41), 7, GFLAGS),
++ GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vo_root", 0,
++ RK3528_CLKGATE_CON(39), 10, GFLAGS),
++ GATE(HCLK_CVBS, "hclk_cvbs", "hclk_vo_root", 0,
++ RK3528_CLKGATE_CON(41), 3, GFLAGS),
++ GATE(HCLK_USBHOST_ARB, "hclk_usbhost_arb", "hclk_vo_root", 0,
++ RK3528_CLKGATE_CON(43), 4, GFLAGS),
++ GATE(HCLK_SAI_I2S3, "hclk_sai_i2s3", "hclk_vo_root", 0,
++ RK3528_CLKGATE_CON(42), 1, GFLAGS),
++ GATE(HCLK_HDCP, "hclk_hdcp", "hclk_vo_root", 0,
++ RK3528_CLKGATE_CON(41), 1, GFLAGS),
++ GATE(HCLK_RGA2E, "hclk_rga2e", "hclk_vo_root", 0,
++ RK3528_CLKGATE_CON(39), 7, GFLAGS),
++ GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vo_root", 0,
++ RK3528_CLKGATE_CON(42), 9, GFLAGS),
++ GATE(HCLK_HDCP_KEY, "hclk_hdcp_key", "hclk_vo_root", 0,
++ RK3528_CLKGATE_CON(40), 15, GFLAGS),
++
++ COMPOSITE_NODIV(ACLK_VO_L_ROOT, "aclk_vo_l_root", mux_150m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(84), 1, 2, MFLAGS,
++ RK3528_CLKGATE_CON(41), 8, GFLAGS),
++ GATE(ACLK_MAC_VO, "aclk_gmac0", "aclk_vo_l_root", 0,
++ RK3528_CLKGATE_CON(41), 10, GFLAGS),
++
++ COMPOSITE_NODIV(PCLK_VO_ROOT, "pclk_vo_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(83), 4, 2, MFLAGS,
++ RK3528_CLKGATE_CON(39), 2, GFLAGS),
++ GATE(PCLK_MAC_VO, "pclk_gmac0", "pclk_vo_root", 0,
++ RK3528_CLKGATE_CON(41), 11, GFLAGS),
++ GATE(PCLK_VCDCPHY, "pclk_vcdcphy", "pclk_vo_root", 0,
++ RK3528_CLKGATE_CON(42), 4, GFLAGS),
++ GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vo_root", 0,
++ RK3528_CLKGATE_CON(42), 5, GFLAGS),
++ GATE(PCLK_VO_IOC, "pclk_vo_ioc", "pclk_vo_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(42), 7, GFLAGS),
++ GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_vo_root", 0,
++ RK3528_CLKGATE_CON(42), 11, GFLAGS),
++ GATE(PCLK_UART4, "pclk_uart4", "pclk_vo_root", 0,
++ RK3528_CLKGATE_CON(43), 7, GFLAGS),
++ GATE(PCLK_I2C4, "pclk_i2c4", "pclk_vo_root", 0,
++ RK3528_CLKGATE_CON(43), 9, GFLAGS),
++ GATE(PCLK_I2C7, "pclk_i2c7", "pclk_vo_root", 0,
++ RK3528_CLKGATE_CON(43), 11, GFLAGS),
++
++ GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_vo_root", 0,
++ RK3528_CLKGATE_CON(43), 13, GFLAGS),
++
++ GATE(PCLK_VO_GRF, "pclk_vo_grf", "pclk_vo_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(39), 13, GFLAGS),
++ GATE(PCLK_CRU, "pclk_cru", "pclk_vo_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(39), 15, GFLAGS),
++ GATE(PCLK_HDMI, "pclk_hdmi", "pclk_vo_root", 0,
++ RK3528_CLKGATE_CON(40), 6, GFLAGS),
++ GATE(PCLK_HDMIPHY, "pclk_hdmiphy", "pclk_vo_root", 0,
++ RK3528_CLKGATE_CON(40), 14, GFLAGS),
++ GATE(PCLK_HDCP, "pclk_hdcp", "pclk_vo_root", 0,
++ RK3528_CLKGATE_CON(41), 2, GFLAGS),
++
++ COMPOSITE_NODIV(CLK_CORE_VDPP, "clk_core_vdpp", mux_339m_200m_100m_24m_p, 0,
++ RK3528_CLKSEL_CON(83), 10, 2, MFLAGS,
++ RK3528_CLKGATE_CON(39), 12, GFLAGS),
++ COMPOSITE_NODIV(CLK_CORE_RGA2E, "clk_core_rga2e", mux_339m_200m_100m_24m_p, 0,
++ RK3528_CLKSEL_CON(83), 8, 2, MFLAGS,
++ RK3528_CLKGATE_CON(39), 9, GFLAGS),
++ COMPOSITE_NODIV(ACLK_JPEG_ROOT, "aclk_jpeg_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(84), 9, 2, MFLAGS,
++ RK3528_CLKGATE_CON(41), 15, GFLAGS),
++ GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_root", 0,
++ RK3528_CLKGATE_CON(41), 6, GFLAGS),
++
++ COMPOSITE_NODIV(ACLK_VO_ROOT, "aclk_vo_root", mux_339m_200m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(83), 0, 2, MFLAGS,
++ RK3528_CLKGATE_CON(39), 0, GFLAGS),
++ GATE(ACLK_RGA2E, "aclk_rga2e", "aclk_vo_root", 0,
++ RK3528_CLKGATE_CON(39), 8, GFLAGS),
++ GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vo_root", 0,
++ RK3528_CLKGATE_CON(39), 11, GFLAGS),
++ GATE(ACLK_HDCP, "aclk_hdcp", "aclk_vo_root", 0,
++ RK3528_CLKGATE_CON(41), 0, GFLAGS),
++
++ COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", mux_gpll_cpll_xin24m_p, 0,
++ RK3528_CLKSEL_CON(85), 6, 2, MFLAGS, 0, 6, DFLAGS,
++ RK3528_CLKGATE_CON(42), 8, GFLAGS),
++
++ COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", mux_gpll_cpll_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(83), 15, 1, MFLAGS, 12, 3, DFLAGS,
++ RK3528_CLKGATE_CON(40), 0, GFLAGS),
++ GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0,
++ RK3528_CLKGATE_CON(40), 5, GFLAGS),
++
++ COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(85), 13, 2, MFLAGS,
++ RK3528_CLKGATE_CON(43), 10, GFLAGS),
++ COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(86), 0, 2, MFLAGS,
++ RK3528_CLKGATE_CON(43), 12, GFLAGS),
++ GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
++ RK3528_CLKGATE_CON(42), 6, GFLAGS),
++
++ GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
++ RK3528_CLKGATE_CON(43), 2, GFLAGS),
++ GATE(CLK_MACPHY, "clk_macphy", "xin24m", 0,
++ RK3528_CLKGATE_CON(42), 3, GFLAGS),
++ GATE(CLK_REF_USBPHY, "clk_ref_usbphy", "xin24m", 0,
++ RK3528_CLKGATE_CON(43), 14, GFLAGS),
++ GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
++ RK3528_CLKGATE_CON(42), 12, GFLAGS),
++ FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns",
++ 0, 1, 2),
++
++ GATE(MCLK_SAI_I2S3, "mclk_sai_i2s3", "mclk_i2s3_8ch_sai_src", 0,
++ RK3528_CLKGATE_CON(42), 2, GFLAGS),
++ COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++ RK3528_CLKSEL_CON(84), 0, 1, MFLAGS,
++ RK3528_CLKGATE_CON(40), 3, GFLAGS),
++ GATE(DCLK_VOP1, "dclk_vop1", "dclk_vop_src1", CLK_SET_RATE_PARENT,
++ RK3528_CLKGATE_CON(40), 4, GFLAGS),
++ FACTOR_GATE(DCLK_CVBS, "dclk_cvbs", "dclk_vop1", 0, 1, 4,
++ RK3528_CLKGATE_CON(41), 4, GFLAGS),
++ GATE(DCLK_4X_CVBS, "dclk_4x_cvbs", "dclk_vop1", 0,
++ RK3528_CLKGATE_CON(41), 5, GFLAGS),
++
++ FACTOR_GATE(CLK_SFR_HDMI, "clk_sfr_hdmi", "dclk_vop_src1", 0, 1, 4,
++ RK3528_CLKGATE_CON(40), 7, GFLAGS),
++
++ GATE(CLK_SPDIF_HDMI, "clk_spdif_hdmi", "mclk_spdif_src", 0,
++ RK3528_CLKGATE_CON(40), 10, GFLAGS),
++ GATE(MCLK_SPDIF, "mclk_spdif", "mclk_spdif_src", 0,
++ RK3528_CLKGATE_CON(37), 15, GFLAGS),
++ GATE(CLK_CEC_HDMI, "clk_cec_hdmi", "clk_32k", 0,
++ RK3528_CLKGATE_CON(40), 8, GFLAGS),
++
++ /* vpu */
++ GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
++ RK3528_CLKGATE_CON(26), 5, GFLAGS),
++ GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
++ RK3528_CLKGATE_CON(27), 1, GFLAGS),
++ GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0,
++ RK3528_CLKGATE_CON(33), 4, GFLAGS),
++ GATE(CLK_PCIE_AUX, "clk_pcie_aux", "xin24m", 0,
++ RK3528_CLKGATE_CON(30), 2, GFLAGS),
++ GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0,
++ RK3528_CLKGATE_CON(26), 3, GFLAGS),
++ GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0,
++ RK3528_CLKGATE_CON(33), 2, GFLAGS),
++ COMPOSITE(CCLK_SRC_SDIO0, "cclk_src_sdio0", mux_gpll_cpll_xin24m_p, 0,
++ RK3528_CLKSEL_CON(72), 6, 2, MFLAGS, 0, 6, DFLAGS,
++ RK3528_CLKGATE_CON(32), 1, GFLAGS),
++
++ COMPOSITE_NODIV(PCLK_VPU_ROOT, "pclk_vpu_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(61), 4, 2, MFLAGS,
++ RK3528_CLKGATE_CON(25), 5, GFLAGS),
++ GATE(PCLK_VPU_GRF, "pclk_vpu_grf", "pclk_vpu_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(25), 12, GFLAGS),
++ GATE(PCLK_CRU_PCIE, "pclk_cru_pcie", "pclk_vpu_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(25), 11, GFLAGS),
++ GATE(PCLK_UART6, "pclk_uart6", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(27), 11, GFLAGS),
++ GATE(PCLK_CAN2, "pclk_can2", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(32), 7, GFLAGS),
++ GATE(PCLK_SPI1, "pclk_spi1", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(27), 4, GFLAGS),
++ GATE(PCLK_CAN3, "pclk_can3", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(32), 9, GFLAGS),
++ GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(27), 0, GFLAGS),
++ GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(26), 4, GFLAGS),
++ GATE(PCLK_SARADC, "pclk_saradc", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(32), 11, GFLAGS),
++ GATE(PCLK_ACODEC, "pclk_acodec", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(26), 13, GFLAGS),
++ GATE(PCLK_UART7, "pclk_uart7", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(27), 13, GFLAGS),
++ GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(27), 9, GFLAGS),
++ GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(32), 14, GFLAGS),
++ GATE(PCLK_PCIE, "pclk_pcie", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(30), 1, GFLAGS),
++ GATE(PCLK_UART2, "pclk_uart2", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(27), 7, GFLAGS),
++ GATE(PCLK_VPU_IOC, "pclk_vpu_ioc", "pclk_vpu_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(26), 8, GFLAGS),
++ GATE(PCLK_PIPE_GRF, "pclk_pipe_grf", "pclk_vpu_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(30), 7, GFLAGS),
++ GATE(PCLK_I2C5, "pclk_i2c5", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(28), 1, GFLAGS),
++ GATE(PCLK_PCIE_PHY, "pclk_pcie_phy", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(30), 6, GFLAGS),
++ GATE(PCLK_I2C3, "pclk_i2c3", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(27), 15, GFLAGS),
++ GATE(PCLK_MAC_VPU, "pclk_gmac1", "pclk_vpu_root", CLK_IS_CRITICAL,
++ RK3528_CLKGATE_CON(28), 6, GFLAGS),
++ GATE(PCLK_I2C6, "pclk_i2c6", "pclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(28), 3, GFLAGS),
++
++ COMPOSITE_NODIV(ACLK_VPU_L_ROOT, "aclk_vpu_l_root", mux_200m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(60), 0, 2, MFLAGS,
++ RK3528_CLKGATE_CON(25), 0, GFLAGS),
++ GATE(ACLK_EMMC, "aclk_emmc", "aclk_vpu_l_root", 0,
++ RK3528_CLKGATE_CON(26), 1, GFLAGS),
++ GATE(ACLK_MAC_VPU, "aclk_gmac1", "aclk_vpu_l_root", 0,
++ RK3528_CLKGATE_CON(28), 5, GFLAGS),
++ GATE(ACLK_PCIE, "aclk_pcie", "aclk_vpu_l_root", 0,
++ RK3528_CLKGATE_CON(30), 3, GFLAGS),
++
++ GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_vpu_l_root", 0,
++ RK3528_CLKGATE_CON(33), 1, GFLAGS),
++
++ COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(61), 2, 2, MFLAGS,
++ RK3528_CLKGATE_CON(25), 4, GFLAGS),
++ GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(25), 10, GFLAGS),
++ GATE(HCLK_SFC, "hclk_sfc", "hclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(25), 13, GFLAGS),
++ GATE(HCLK_EMMC, "hclk_emmc", "hclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(26), 0, GFLAGS),
++ GATE(HCLK_SAI_I2S0, "hclk_sai_i2s0", "hclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(26), 9, GFLAGS),
++ GATE(HCLK_SAI_I2S2, "hclk_sai_i2s2", "hclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(26), 11, GFLAGS),
++
++ GATE(HCLK_PCIE_SLV, "hclk_pcie_slv", "hclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(30), 4, GFLAGS),
++ GATE(HCLK_PCIE_DBI, "hclk_pcie_dbi", "hclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(30), 5, GFLAGS),
++ GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(32), 2, GFLAGS),
++ GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(32), 4, GFLAGS),
++
++ COMPOSITE_NOMUX(CLK_GMAC1_VPU_25M, "clk_gmac1_25m", "ppll", 0,
++ RK3528_CLKSEL_CON(60), 2, 8, DFLAGS,
++ RK3528_CLKGATE_CON(25), 1, GFLAGS),
++ COMPOSITE_NOMUX(CLK_PPLL_125M_MATRIX, "clk_ppll_125m_src", "ppll", 0,
++ RK3528_CLKSEL_CON(60), 10, 5, DFLAGS,
++ RK3528_CLKGATE_CON(25), 2, GFLAGS),
++
++ COMPOSITE(CLK_CAN3, "clk_can3", mux_gpll_cpll_p, 0,
++ RK3528_CLKSEL_CON(73), 13, 1, MFLAGS, 7, 6, DFLAGS,
++ RK3528_CLKGATE_CON(32), 10, GFLAGS),
++ COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(64), 0, 2, MFLAGS,
++ RK3528_CLKGATE_CON(28), 4, GFLAGS),
++
++ COMPOSITE(SCLK_SFC, "sclk_sfc", mux_gpll_cpll_xin24m_p, 0,
++ RK3528_CLKSEL_CON(61), 12, 2, MFLAGS, 6, 6, DFLAGS,
++ RK3528_CLKGATE_CON(25), 14, GFLAGS),
++ COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", mux_gpll_cpll_xin24m_p, 0,
++ RK3528_CLKSEL_CON(62), 6, 2, MFLAGS, 0, 6, DFLAGS,
++ RK3528_CLKGATE_CON(25), 15, GFLAGS),
++
++ COMPOSITE_NODIV(ACLK_VPU_ROOT, "aclk_vpu_root",
++ mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
++ RK3528_CLKSEL_CON(61), 0, 2, MFLAGS,
++ RK3528_CLKGATE_CON(25), 3, GFLAGS),
++ GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_root", 0,
++ RK3528_CLKGATE_CON(25), 9, GFLAGS),
++
++ COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(63), 10, 2, MFLAGS,
++ RK3528_CLKGATE_CON(27), 5, GFLAGS),
++ COMPOSITE(CCLK_SRC_SDIO1, "cclk_src_sdio1", mux_gpll_cpll_xin24m_p, 0,
++ RK3528_CLKSEL_CON(72), 14, 2, MFLAGS, 8, 6, DFLAGS,
++ RK3528_CLKGATE_CON(32), 3, GFLAGS),
++ COMPOSITE(CLK_CAN2, "clk_can2", mux_gpll_cpll_p, 0,
++ RK3528_CLKSEL_CON(73), 6, 1, MFLAGS, 0, 6, DFLAGS,
++ RK3528_CLKGATE_CON(32), 8, GFLAGS),
++ COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0,
++ RK3528_CLKSEL_CON(74), 3, 5, DFLAGS,
++ RK3528_CLKGATE_CON(32), 15, GFLAGS),
++ COMPOSITE_NOMUX(CLK_SARADC, "clk_saradc", "xin24m", 0,
++ RK3528_CLKSEL_CON(74), 0, 3, DFLAGS,
++ RK3528_CLKGATE_CON(32), 12, GFLAGS),
++ COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m", 0,
++ RK3528_CLKSEL_CON(74), 8, 5, DFLAGS,
++ RK3528_CLKGATE_CON(33), 0, GFLAGS),
++ COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(62), 8, 2, MFLAGS,
++ RK3528_CLKGATE_CON(26), 2, GFLAGS),
++ COMPOSITE_NOMUX(MCLK_ACODEC_TX, "mclk_acodec_tx", "mclk_i2s2_2ch_sai_src", 0,
++ RK3528_CLKSEL_CON(63), 0, 8, DFLAGS,
++ RK3528_CLKGATE_CON(26), 14, GFLAGS),
++ COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(63), 12, 2, MFLAGS,
++ RK3528_CLKGATE_CON(28), 0, GFLAGS),
++ COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0,
++ RK3528_CLKSEL_CON(63), 14, 2, MFLAGS,
++ RK3528_CLKGATE_CON(28), 2, GFLAGS),
++ COMPOSITE_NODIV(MCLK_SAI_I2S0, "mclk_sai_i2s0", mclk_sai_i2s0_p, CLK_SET_RATE_PARENT,
++ RK3528_CLKSEL_CON(62), 10, 1, MFLAGS,
++ RK3528_CLKGATE_CON(26), 10, GFLAGS),
++ GATE(MCLK_SAI_I2S2, "mclk_sai_i2s2", "mclk_i2s2_2ch_sai_src", 0,
++ RK3528_CLKGATE_CON(26), 12, GFLAGS),
++
++ /* pcie */
++ COMPOSITE_NOMUX(CLK_PPLL_100M_MATRIX, "clk_ppll_100m_src", "ppll", CLK_IS_CRITICAL,
++ RK3528_PCIE_CLKSEL_CON(1), 2, 5, DFLAGS,
++ RK3528_PCIE_CLKGATE_CON(0), 1, GFLAGS),
++ COMPOSITE_NOMUX(CLK_PPLL_50M_MATRIX, "clk_ppll_50m_src", "ppll", CLK_IS_CRITICAL,
++ RK3528_PCIE_CLKSEL_CON(1), 7, 5, DFLAGS,
++ RK3528_PCIE_CLKGATE_CON(0), 2, GFLAGS),
++ MUX(CLK_REF_PCIE_INNER_PHY, "clk_ref_pcie_inner_phy", clk_ref_pcie_inner_phy_p, 0,
++ RK3528_PCIE_CLKSEL_CON(1), 13, 1, MFLAGS),
++ FACTOR(CLK_REF_PCIE_100M_PHY, "clk_ref_pcie_100m_phy", "clk_ppll_100m_src",
++ 0, 1, 1),
++
++ /* gmac */
++ DIV(CLK_GMAC0_SRC, "clk_gmac0_src", "gmac0", 0,
++ RK3528_CLKSEL_CON(84), 3, 6, DFLAGS),
++ GATE(CLK_GMAC0_TX, "clk_gmac0_tx", "clk_gmac0_src", 0,
++ RK3528_CLKGATE_CON(41), 13, GFLAGS),
++ GATE(CLK_GMAC0_RX, "clk_gmac0_rx", "clk_gmac0_src", 0,
++ RK3528_CLKGATE_CON(41), 14, GFLAGS),
++ GATE(CLK_GMAC0_RMII_50M, "clk_gmac0_rmii_50m", "gmac0", 0,
++ RK3528_CLKGATE_CON(41), 12, GFLAGS),
++
++ FACTOR(CLK_GMAC1_RMII_VPU, "clk_gmac1_50m", "clk_ppll_50m_src",
++ 0, 1, 1),
++ FACTOR(CLK_GMAC1_SRC_VPU, "clk_gmac1_125m", "clk_ppll_125m_src",
++ 0, 1, 1),
++};
++
++static int __init clk_rk3528_probe(struct platform_device *pdev)
++{
++ struct rockchip_clk_provider *ctx;
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++ unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches);
++ unsigned long nr_clks;
++ void __iomem *reg_base;
++
++ nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches,
++ nr_branches) + 1;
++
++ reg_base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(reg_base))
++ return dev_err_probe(dev, PTR_ERR(reg_base),
++ "could not map cru region");
++
++ ctx = rockchip_clk_init(np, reg_base, nr_clks);
++ if (IS_ERR(ctx))
++ return dev_err_probe(dev, PTR_ERR(ctx),
++ "rockchip clk init failed");
++
++ rockchip_clk_register_plls(ctx, rk3528_pll_clks,
++ ARRAY_SIZE(rk3528_pll_clks),
++ RK3528_GRF_SOC_STATUS0);
++ rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
++ mux_armclk, ARRAY_SIZE(mux_armclk),
++ &rk3528_cpuclk_data, rk3528_cpuclk_rates,
++ ARRAY_SIZE(rk3528_cpuclk_rates));
++ rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches);
++
++ rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL);
++
++ rockchip_clk_of_add_provider(np, ctx);
++
++ return 0;
++}
++
++static const struct of_device_id clk_rk3528_match_table[] = {
++ { .compatible = "rockchip,rk3528-cru" },
++ { /* end */ }
++};
++
++static struct platform_driver clk_rk3528_driver = {
++ .driver = {
++ .name = "clk-rk3528",
++ .of_match_table = clk_rk3528_match_table,
++ .suppress_bind_attrs = true,
++ },
++};
++builtin_platform_driver_probe(clk_rk3528_driver, clk_rk3528_probe);
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -208,6 +208,26 @@ struct clk;
+ #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
+ #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
+
++#define RK3528_PMU_CRU_BASE 0x10000
++#define RK3528_PCIE_CRU_BASE 0x20000
++#define RK3528_DDRPHY_CRU_BASE 0x28000
++#define RK3528_PLL_CON(x) RK2928_PLL_CON(x)
++#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
++#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
++#define RK3528_MODE_CON 0x280
++#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
++#define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
++#define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
++#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
++#define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
++#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
++#define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
++#define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
++#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
++#define RK3528_GLB_CNT_TH 0xc00
++#define RK3528_GLB_SRST_FST 0xc08
++#define RK3528_GLB_SRST_SND 0xc0c
++
+ #define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
+ #define RK3568_MODE_CON0 0xc0
+ #define RK3568_MISC_CON0 0xc4
--- /dev/null
+From 5738362a5ee7e3417312e7fc03bcb0ffb12ba4f3 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Thu, 27 Feb 2025 17:52:57 +0000
+Subject: [PATCH] clk: rockchip: rk3528: Add reset lookup table
+
+In the commit 5d0eb375e685 ("clk: rockchip: Add clock controller driver
+for RK3528 SoC") only the dt-binding header was added for the reset
+controller for the RK3528 SoC.
+
+Add a reset lookup table generated from the SRST symbols used by vendor
+linux-6.1-stan-rkr5 kernel to complete support for the reset controller.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250227175302.2950788-1-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/Makefile | 2 +-
+ drivers/clk/rockchip/clk-rk3528.c | 2 +
+ drivers/clk/rockchip/clk.h | 1 +
+ drivers/clk/rockchip/rst-rk3528.c | 306 ++++++++++++++++++++++++++++++
+ 4 files changed, 310 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/clk/rockchip/rst-rk3528.c
+
+--- a/drivers/clk/rockchip/Makefile
++++ b/drivers/clk/rockchip/Makefile
+@@ -29,7 +29,7 @@ obj-$(CONFIG_CLK_RK3308) += clk-r
+ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
+ obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
+ obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
+-obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o
++obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o rst-rk3528.o
+ obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
+ obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o
+ obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o
+--- a/drivers/clk/rockchip/clk-rk3528.c
++++ b/drivers/clk/rockchip/clk-rk3528.c
+@@ -1092,6 +1092,8 @@ static int __init clk_rk3528_probe(struc
+ ARRAY_SIZE(rk3528_cpuclk_rates));
+ rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches);
+
++ rk3528_rst_init(np, reg_base);
++
+ rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL);
+
+ rockchip_clk_of_add_provider(np, ctx);
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -1187,6 +1187,7 @@ static inline void rockchip_register_sof
+ return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
+ }
+
++void rk3528_rst_init(struct device_node *np, void __iomem *reg_base);
+ void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
+ void rk3588_rst_init(struct device_node *np, void __iomem *reg_base);
+
+--- /dev/null
++++ b/drivers/clk/rockchip/rst-rk3528.c
+@@ -0,0 +1,306 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
++ * Based on Sebastian Reichel's implementation for RK3588
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <dt-bindings/reset/rockchip,rk3528-cru.h>
++#include "clk.h"
++
++/* 0xFF4A0000 + 0x0A00 */
++#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
++
++/* mapping table for reset ID to register offset */
++static const int rk3528_register_offset[] = {
++ /* CRU_SOFTRST_CON03 */
++ RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10),
++
++ /* CRU_SOFTRST_CON05 */
++ RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13),
++ RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14),
++ RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15),
++
++ /* CRU_SOFTRST_CON06 */
++ RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7),
++
++ /* CRU_SOFTRST_CON08 */
++ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13),
++ RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15),
++
++ /* CRU_SOFTRST_CON09 */
++ RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0),
++ RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13),
++ RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15),
++
++ /* CRU_SOFTRST_CON10 */
++ RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0),
++ RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13),
++ RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14),
++
++ /* CRU_SOFTRST_CON11 */
++ RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12),
++
++ /* CRU_SOFTRST_CON25 */
++ RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13),
++ RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14),
++ RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15),
++
++ /* CRU_SOFTRST_CON26 */
++ RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0),
++ RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13),
++
++ /* CRU_SOFTRST_CON27 */
++ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0),
++ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13),
++ RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14),
++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15),
++
++ /* CRU_SOFTRST_CON28 */
++ RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0),
++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5),
++
++ /* CRU_SOFTRST_CON30 */
++ RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7),
++
++ /* CRU_SOFTRST_CON32 */
++ RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13),
++ RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14),
++ RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15),
++
++ /* CRU_SOFTRST_CON33 */
++ RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1),
++
++ /* CRU_SOFTRST_CON34 */
++ RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9),
++
++ /* CRU_SOFTRST_CON36 */
++ RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13),
++ RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14),
++
++ /* CRU_SOFTRST_CON37 */
++ RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14),
++ RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15),
++
++ /* CRU_SOFTRST_CON38 */
++ RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0),
++ RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10),
++
++ /* CRU_SOFTRST_CON39 */
++ RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13),
++ RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15),
++
++ /* CRU_SOFTRST_CON40 */
++ RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14),
++ RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15),
++
++ /* CRU_SOFTRST_CON41 */
++ RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0),
++ RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10),
++
++ /* CRU_SOFTRST_CON42 */
++ RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0),
++ RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13),
++
++ /* CRU_SOFTRST_CON43 */
++ RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13),
++ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14),
++ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15),
++
++ /* CRU_SOFTRST_CON44 */
++ RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0),
++ RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7),
++ RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12),
++
++ /* CRU_SOFTRST_CON45 */
++ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1),
++ RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2),
++ RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3),
++ RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4),
++ RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5),
++ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6),
++ RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8),
++ RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9),
++ RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10),
++ RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11),
++ RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12),
++ RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13),
++ RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14),
++ RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15),
++
++ /* CRU_SOFTRST_CON46 */
++ RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0),
++};
++
++void rk3528_rst_init(struct device_node *np, void __iomem *reg_base)
++{
++ rockchip_register_softrst_lut(np,
++ rk3528_register_offset,
++ ARRAY_SIZE(rk3528_register_offset),
++ reg_base + RK3528_SOFTRST_CON(0),
++ ROCKCHIP_SOFTRST_HIWORD_MASK);
++}
--- /dev/null
+From a5e4cde647851ed67f19a5cb54a99282f32aae99 Mon Sep 17 00:00:00 2001
+From: Steven Liu <steven.liu@rock-chips.com>
+Date: Fri, 28 Feb 2025 06:40:09 +0000
+Subject: [PATCH] pinctrl: rockchip: Add support for RK3528
+
+Add gpio and pinctrl support for the 5 GPIO banks on RK3528.
+
+Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/20250228064024.3200000-4-jonas@kwiboo.se
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-rockchip.c | 160 ++++++++++++++++++++++++++++-
+ drivers/pinctrl/pinctrl-rockchip.h | 1 +
+ 2 files changed, 160 insertions(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/pinctrl-rockchip.c
++++ b/drivers/pinctrl/pinctrl-rockchip.c
+@@ -2003,6 +2003,115 @@ static int rk3399_calc_drv_reg_and_bit(s
+ return 0;
+ }
+
++#define RK3528_DRV_BITS_PER_PIN 8
++#define RK3528_DRV_PINS_PER_REG 2
++#define RK3528_DRV_GPIO0_OFFSET 0x100
++#define RK3528_DRV_GPIO1_OFFSET 0x20120
++#define RK3528_DRV_GPIO2_OFFSET 0x30160
++#define RK3528_DRV_GPIO3_OFFSET 0x20190
++#define RK3528_DRV_GPIO4_OFFSET 0x101C0
++
++static int rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
++ int pin_num, struct regmap **regmap,
++ int *reg, u8 *bit)
++{
++ struct rockchip_pinctrl *info = bank->drvdata;
++
++ *regmap = info->regmap_base;
++
++ if (bank->bank_num == 0)
++ *reg = RK3528_DRV_GPIO0_OFFSET;
++ else if (bank->bank_num == 1)
++ *reg = RK3528_DRV_GPIO1_OFFSET;
++ else if (bank->bank_num == 2)
++ *reg = RK3528_DRV_GPIO2_OFFSET;
++ else if (bank->bank_num == 3)
++ *reg = RK3528_DRV_GPIO3_OFFSET;
++ else if (bank->bank_num == 4)
++ *reg = RK3528_DRV_GPIO4_OFFSET;
++ else
++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
++
++ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
++ *bit = pin_num % RK3528_DRV_PINS_PER_REG;
++ *bit *= RK3528_DRV_BITS_PER_PIN;
++
++ return 0;
++}
++
++#define RK3528_PULL_BITS_PER_PIN 2
++#define RK3528_PULL_PINS_PER_REG 8
++#define RK3528_PULL_GPIO0_OFFSET 0x200
++#define RK3528_PULL_GPIO1_OFFSET 0x20210
++#define RK3528_PULL_GPIO2_OFFSET 0x30220
++#define RK3528_PULL_GPIO3_OFFSET 0x20230
++#define RK3528_PULL_GPIO4_OFFSET 0x10240
++
++static int rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
++ int pin_num, struct regmap **regmap,
++ int *reg, u8 *bit)
++{
++ struct rockchip_pinctrl *info = bank->drvdata;
++
++ *regmap = info->regmap_base;
++
++ if (bank->bank_num == 0)
++ *reg = RK3528_PULL_GPIO0_OFFSET;
++ else if (bank->bank_num == 1)
++ *reg = RK3528_PULL_GPIO1_OFFSET;
++ else if (bank->bank_num == 2)
++ *reg = RK3528_PULL_GPIO2_OFFSET;
++ else if (bank->bank_num == 3)
++ *reg = RK3528_PULL_GPIO3_OFFSET;
++ else if (bank->bank_num == 4)
++ *reg = RK3528_PULL_GPIO4_OFFSET;
++ else
++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
++
++ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
++ *bit = pin_num % RK3528_PULL_PINS_PER_REG;
++ *bit *= RK3528_PULL_BITS_PER_PIN;
++
++ return 0;
++}
++
++#define RK3528_SMT_BITS_PER_PIN 1
++#define RK3528_SMT_PINS_PER_REG 8
++#define RK3528_SMT_GPIO0_OFFSET 0x400
++#define RK3528_SMT_GPIO1_OFFSET 0x20410
++#define RK3528_SMT_GPIO2_OFFSET 0x30420
++#define RK3528_SMT_GPIO3_OFFSET 0x20430
++#define RK3528_SMT_GPIO4_OFFSET 0x10440
++
++static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
++ int pin_num,
++ struct regmap **regmap,
++ int *reg, u8 *bit)
++{
++ struct rockchip_pinctrl *info = bank->drvdata;
++
++ *regmap = info->regmap_base;
++
++ if (bank->bank_num == 0)
++ *reg = RK3528_SMT_GPIO0_OFFSET;
++ else if (bank->bank_num == 1)
++ *reg = RK3528_SMT_GPIO1_OFFSET;
++ else if (bank->bank_num == 2)
++ *reg = RK3528_SMT_GPIO2_OFFSET;
++ else if (bank->bank_num == 3)
++ *reg = RK3528_SMT_GPIO3_OFFSET;
++ else if (bank->bank_num == 4)
++ *reg = RK3528_SMT_GPIO4_OFFSET;
++ else
++ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
++
++ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
++ *bit = pin_num % RK3528_SMT_PINS_PER_REG;
++ *bit *= RK3528_SMT_BITS_PER_PIN;
++
++ return 0;
++}
++
+ #define RK3568_PULL_PMU_OFFSET 0x20
+ #define RK3568_PULL_GRF_OFFSET 0x80
+ #define RK3568_PULL_BITS_PER_PIN 2
+@@ -2495,7 +2604,8 @@ static int rockchip_set_drive_perpin(str
+ rmask_bits = RK3588_DRV_BITS_PER_PIN;
+ ret = strength;
+ goto config;
+- } else if (ctrl->type == RK3568) {
++ } else if (ctrl->type == RK3528 ||
++ ctrl->type == RK3568) {
+ rmask_bits = RK3568_DRV_BITS_PER_PIN;
+ ret = (1 << (strength + 1)) - 1;
+ goto config;
+@@ -2639,6 +2749,7 @@ static int rockchip_get_pull(struct rock
+ case RK3328:
+ case RK3368:
+ case RK3399:
++ case RK3528:
+ case RK3568:
+ case RK3576:
+ case RK3588:
+@@ -2699,6 +2810,7 @@ static int rockchip_set_pull(struct rock
+ case RK3328:
+ case RK3368:
+ case RK3399:
++ case RK3528:
+ case RK3568:
+ case RK3576:
+ case RK3588:
+@@ -2964,6 +3076,7 @@ static bool rockchip_pinconf_pull_valid(
+ case RK3328:
+ case RK3368:
+ case RK3399:
++ case RK3528:
+ case RK3568:
+ case RK3576:
+ case RK3588:
+@@ -4083,6 +4196,49 @@ static struct rockchip_pin_ctrl rk3399_p
+ .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
+ };
+
++static struct rockchip_pin_bank rk3528_pin_banks[] = {
++ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ 0, 0, 0, 0),
++ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ 0x20020, 0x20028, 0x20030, 0x20038),
++ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ 0x30040, 0, 0, 0),
++ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ 0x20060, 0x20068, 0x20070, 0),
++ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ IOMUX_WIDTH_4BIT,
++ 0x10080, 0x10088, 0x10090, 0x10098),
++};
++
++static struct rockchip_pin_ctrl rk3528_pin_ctrl = {
++ .pin_banks = rk3528_pin_banks,
++ .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
++ .label = "RK3528-GPIO",
++ .type = RK3528,
++ .pull_calc_reg = rk3528_calc_pull_reg_and_bit,
++ .drv_calc_reg = rk3528_calc_drv_reg_and_bit,
++ .schmitt_calc_reg = rk3528_calc_schmitt_reg_and_bit,
++};
++
+ static struct rockchip_pin_bank rk3568_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+@@ -4207,6 +4363,8 @@ static const struct of_device_id rockchi
+ .data = &rk3368_pin_ctrl },
+ { .compatible = "rockchip,rk3399-pinctrl",
+ .data = &rk3399_pin_ctrl },
++ { .compatible = "rockchip,rk3528-pinctrl",
++ .data = &rk3528_pin_ctrl },
+ { .compatible = "rockchip,rk3568-pinctrl",
+ .data = &rk3568_pin_ctrl },
+ { .compatible = "rockchip,rk3576-pinctrl",
+--- a/drivers/pinctrl/pinctrl-rockchip.h
++++ b/drivers/pinctrl/pinctrl-rockchip.h
+@@ -196,6 +196,7 @@ enum rockchip_pinctrl_type {
+ RK3328,
+ RK3368,
+ RK3399,
++ RK3528,
+ RK3568,
+ RK3576,
+ RK3588,
--- /dev/null
+From 8a023e86f3d999007f2687952afe78ef34a6aa91 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Tue, 6 May 2025 09:22:02 +0000
+Subject: [PATCH] dt-bindings: clock: Add GRF clock definition for RK3528
+
+These clocks are for SD/SDIO tuning purpose and come with registers
+in GRF syscon.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20250506092206.46143-2-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ include/dt-bindings/clock/rockchip,rk3528-cru.h | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/include/dt-bindings/clock/rockchip,rk3528-cru.h
++++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h
+@@ -414,6 +414,12 @@
+ #define MCLK_I2S2_2CH_SAI_SRC_PRE 402
+ #define MCLK_I2S3_8CH_SAI_SRC_PRE 403
+ #define MCLK_SDPDIF_SRC_PRE 404
++#define SCLK_SDMMC_DRV 405
++#define SCLK_SDMMC_SAMPLE 406
++#define SCLK_SDIO0_DRV 407
++#define SCLK_SDIO0_SAMPLE 408
++#define SCLK_SDIO1_DRV 409
++#define SCLK_SDIO1_SAMPLE 410
+
+ /* scmi-clocks indices */
+ #define SCMI_PCLK_KEYREADER 0
--- /dev/null
+From 621ba4d9f6db560a7406fd732af1b495ff5aa103 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Tue, 6 May 2025 09:22:03 +0000
+Subject: [PATCH] clk: rockchip: Support MMC clocks in GRF region
+
+Registers of MMC drive/sample clocks in Rockchip RV1106 and RK3528
+locate in GRF regions. Adjust MMC clock code to support register
+operations through regmap.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20250506092206.46143-3-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-mmc-phase.c | 24 ++++++++++++++++++++----
+ drivers/clk/rockchip/clk.c | 16 ++++++++++++++--
+ drivers/clk/rockchip/clk.h | 17 ++++++++++++++++-
+ 3 files changed, 50 insertions(+), 7 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-mmc-phase.c
++++ b/drivers/clk/rockchip/clk-mmc-phase.c
+@@ -9,11 +9,14 @@
+ #include <linux/clk-provider.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
++#include <linux/regmap.h>
+ #include "clk.h"
+
+ struct rockchip_mmc_clock {
+ struct clk_hw hw;
+ void __iomem *reg;
++ struct regmap *grf;
++ int grf_reg;
+ int shift;
+ int cached_phase;
+ struct notifier_block clk_rate_change_nb;
+@@ -54,7 +57,12 @@ static int rockchip_mmc_get_phase(struct
+ if (!rate)
+ return 0;
+
+- raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
++ if (mmc_clock->grf)
++ regmap_read(mmc_clock->grf, mmc_clock->grf_reg, &raw_value);
++ else
++ raw_value = readl(mmc_clock->reg);
++
++ raw_value >>= mmc_clock->shift;
+
+ degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
+
+@@ -134,8 +142,12 @@ static int rockchip_mmc_set_phase(struct
+ raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
+ raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
+ raw_value |= nineties;
+- writel(HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift),
+- mmc_clock->reg);
++ raw_value = HIWORD_UPDATE(raw_value, 0x07ff, mmc_clock->shift);
++
++ if (mmc_clock->grf)
++ regmap_write(mmc_clock->grf, mmc_clock->grf_reg, raw_value);
++ else
++ writel(raw_value, mmc_clock->reg);
+
+ pr_debug("%s->set_phase(%d) delay_nums=%u reg[0x%p]=0x%03x actual_degrees=%d\n",
+ clk_hw_get_name(hw), degrees, delay_num,
+@@ -189,7 +201,9 @@ static int rockchip_mmc_clk_rate_notify(
+
+ struct clk *rockchip_clk_register_mmc(const char *name,
+ const char *const *parent_names, u8 num_parents,
+- void __iomem *reg, int shift)
++ void __iomem *reg,
++ struct regmap *grf, int grf_reg,
++ int shift)
+ {
+ struct clk_init_data init;
+ struct rockchip_mmc_clock *mmc_clock;
+@@ -208,6 +222,8 @@ struct clk *rockchip_clk_register_mmc(co
+
+ mmc_clock->hw.init = &init;
+ mmc_clock->reg = reg;
++ mmc_clock->grf = grf;
++ mmc_clock->grf_reg = grf_reg;
+ mmc_clock->shift = shift;
+
+ clk = clk_register(NULL, &mmc_clock->hw);
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -509,8 +509,10 @@ void rockchip_clk_register_branches(stru
+ clk = NULL;
+
+ /* for GRF-dependent branches, choose the right grf first */
+- if ((list->branch_type == branch_muxgrf || list->branch_type == branch_grf_gate) &&
+- list->grf_type != grf_type_sys) {
++ if ((list->branch_type == branch_muxgrf ||
++ list->branch_type == branch_grf_gate ||
++ list->branch_type == branch_grf_mmc) &&
++ list->grf_type != grf_type_sys) {
+ hash_for_each_possible(ctx->aux_grf_table, agrf, node, list->grf_type) {
+ if (agrf->type == list->grf_type) {
+ grf = agrf->grf;
+@@ -612,6 +614,16 @@ void rockchip_clk_register_branches(stru
+ list->name,
+ list->parent_names, list->num_parents,
+ ctx->reg_base + list->muxdiv_offset,
++ NULL, 0,
++ list->div_shift
++ );
++ break;
++ case branch_grf_mmc:
++ clk = rockchip_clk_register_mmc(
++ list->name,
++ list->parent_names, list->num_parents,
++ 0,
++ grf, list->muxdiv_offset,
+ list->div_shift
+ );
+ break;
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -580,7 +580,9 @@ struct clk *rockchip_clk_register_cpuclk
+
+ struct clk *rockchip_clk_register_mmc(const char *name,
+ const char *const *parent_names, u8 num_parents,
+- void __iomem *reg, int shift);
++ void __iomem *reg,
++ struct regmap *grf, int grf_reg,
++ int shift);
+
+ /*
+ * DDRCLK flags, including method of setting the rate
+@@ -625,6 +627,7 @@ enum rockchip_clk_branch_type {
+ branch_grf_gate,
+ branch_linked_gate,
+ branch_mmc,
++ branch_grf_mmc,
+ branch_inverter,
+ branch_factor,
+ branch_ddrclk,
+@@ -991,6 +994,18 @@ struct rockchip_clk_branch {
+ .div_shift = shift, \
+ }
+
++#define MMC_GRF(_id, cname, pname, offset, shift, grftype) \
++ { \
++ .id = _id, \
++ .branch_type = branch_grf_mmc, \
++ .name = cname, \
++ .parent_names = (const char *[]){ pname }, \
++ .num_parents = 1, \
++ .muxdiv_offset = offset, \
++ .div_shift = shift, \
++ .grf_type = grftype, \
++ }
++
+ #define INVERTER(_id, cname, pname, io, is, if) \
+ { \
+ .id = _id, \
--- /dev/null
+From 61bf658a4d95e8f982b6e66dea763bff57996349 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Sat, 10 May 2025 07:52:49 +0000
+Subject: [PATCH] clk: rockchip: Pass NULL as reg pointer when registering GRF
+ MMC clocks
+
+This corrects the type and suppresses sparse warnings about passing
+plain integers as NULL pointer.
+
+Fixes: 621ba4d9f6db ("clk: rockchip: Support MMC clocks in GRF region")
+Reported-by: kernel test robot <lkp@intel.com>
+Closes: https://lore.kernel.org/oe-kbuild-all/202505100302.YVtB1zhF-lkp@intel.com/
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20250510075248.34006-2-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -622,7 +622,7 @@ void rockchip_clk_register_branches(stru
+ clk = rockchip_clk_register_mmc(
+ list->name,
+ list->parent_names, list->num_parents,
+- 0,
++ NULL,
+ grf, list->muxdiv_offset,
+ list->div_shift
+ );
--- /dev/null
+From 306d2f5ddaa765f04ffb54fc9437a6318f904b53 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Tue, 6 May 2025 09:22:04 +0000
+Subject: [PATCH] clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF
+ region
+
+These clocks locate in VO and VPU GRF, serving for SD/SDIO controller
+tuning purpose. Add their definitions and register them in driver if
+corresponding GRF is available.
+
+GRFs are looked up by compatible to simplify devicetree binding.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20250506092206.46143-4-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/clk/rockchip/clk-rk3528.c | 82 ++++++++++++++++++++++++++++---
+ drivers/clk/rockchip/clk.h | 5 ++
+ 2 files changed, 81 insertions(+), 6 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-rk3528.c
++++ b/drivers/clk/rockchip/clk-rk3528.c
+@@ -10,6 +10,8 @@
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/platform_device.h>
++#include <linux/mfd/syscon.h>
++#include <linux/minmax.h>
+
+ #include <dt-bindings/clock/rockchip,rk3528-cru.h>
+
+@@ -1061,23 +1063,65 @@ static struct rockchip_clk_branch rk3528
+ 0, 1, 1),
+ };
+
++static struct rockchip_clk_branch rk3528_vo_clk_branches[] __initdata = {
++ MMC_GRF(SCLK_SDMMC_DRV, "sdmmc_drv", "cclk_src_sdmmc0",
++ RK3528_SDMMC_CON(0), 1, grf_type_vo),
++ MMC_GRF(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "cclk_src_sdmmc0",
++ RK3528_SDMMC_CON(1), 1, grf_type_vo),
++};
++
++static struct rockchip_clk_branch rk3528_vpu_clk_branches[] __initdata = {
++ MMC_GRF(SCLK_SDIO0_DRV, "sdio0_drv", "cclk_src_sdio0",
++ RK3528_SDIO0_CON(0), 1, grf_type_vpu),
++ MMC_GRF(SCLK_SDIO0_SAMPLE, "sdio0_sample", "cclk_src_sdio0",
++ RK3528_SDIO0_CON(1), 1, grf_type_vpu),
++ MMC_GRF(SCLK_SDIO1_DRV, "sdio1_drv", "cclk_src_sdio1",
++ RK3528_SDIO1_CON(0), 1, grf_type_vpu),
++ MMC_GRF(SCLK_SDIO1_SAMPLE, "sdio1_sample", "cclk_src_sdio1",
++ RK3528_SDIO1_CON(1), 1, grf_type_vpu),
++};
++
+ static int __init clk_rk3528_probe(struct platform_device *pdev)
+ {
+- struct rockchip_clk_provider *ctx;
++ unsigned long nr_vpu_branches = ARRAY_SIZE(rk3528_vpu_clk_branches);
++ unsigned long nr_vo_branches = ARRAY_SIZE(rk3528_vo_clk_branches);
++ unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches);
++ unsigned long nr_clks, nr_vo_clks, nr_vpu_clks;
++ struct rockchip_aux_grf *vo_grf_e, *vpu_grf_e;
++ struct regmap *vo_grf, *vpu_grf;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+- unsigned long nr_branches = ARRAY_SIZE(rk3528_clk_branches);
+- unsigned long nr_clks;
++ struct rockchip_clk_provider *ctx;
+ void __iomem *reg_base;
+
+- nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches,
+- nr_branches) + 1;
+-
+ reg_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(reg_base))
+ return dev_err_probe(dev, PTR_ERR(reg_base),
+ "could not map cru region");
+
++ nr_clks = rockchip_clk_find_max_clk_id(rk3528_clk_branches,
++ nr_branches) + 1;
++
++ vo_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vo-grf");
++ if (!IS_ERR(vo_grf)) {
++ nr_vo_clks = rockchip_clk_find_max_clk_id(rk3528_vo_clk_branches,
++ nr_vo_branches) + 1;
++ nr_clks = max(nr_clks, nr_vo_clks);
++ } else if (PTR_ERR(vo_grf) != -ENODEV) {
++ return dev_err_probe(dev, PTR_ERR(vo_grf),
++ "failed to look up VO GRF\n");
++ }
++
++ vpu_grf = syscon_regmap_lookup_by_compatible("rockchip,rk3528-vpu-grf");
++ if (!IS_ERR(vpu_grf)) {
++ nr_vpu_clks = rockchip_clk_find_max_clk_id(rk3528_vpu_clk_branches,
++ nr_vpu_branches) + 1;
++ nr_clks = max(nr_clks, nr_vpu_clks);
++ } else if (PTR_ERR(vpu_grf) != -ENODEV) {
++ return dev_err_probe(dev, PTR_ERR(vpu_grf),
++ "failed to look up VPU GRF\n");
++ }
++
+ ctx = rockchip_clk_init(np, reg_base, nr_clks);
+ if (IS_ERR(ctx))
+ return dev_err_probe(dev, PTR_ERR(ctx),
+@@ -1092,6 +1136,32 @@ static int __init clk_rk3528_probe(struc
+ ARRAY_SIZE(rk3528_cpuclk_rates));
+ rockchip_clk_register_branches(ctx, rk3528_clk_branches, nr_branches);
+
++ if (!IS_ERR(vo_grf)) {
++ vo_grf_e = devm_kzalloc(dev, sizeof(*vo_grf_e), GFP_KERNEL);
++ if (!vo_grf_e)
++ return -ENOMEM;
++
++ vo_grf_e->grf = vo_grf;
++ vo_grf_e->type = grf_type_vo;
++ hash_add(ctx->aux_grf_table, &vo_grf_e->node, grf_type_vo);
++
++ rockchip_clk_register_branches(ctx, rk3528_vo_clk_branches,
++ nr_vo_branches);
++ }
++
++ if (!IS_ERR(vpu_grf)) {
++ vpu_grf_e = devm_kzalloc(dev, sizeof(*vpu_grf_e), GFP_KERNEL);
++ if (!vpu_grf_e)
++ return -ENOMEM;
++
++ vpu_grf_e->grf = vpu_grf;
++ vpu_grf_e->type = grf_type_vpu;
++ hash_add(ctx->aux_grf_table, &vpu_grf_e->node, grf_type_vpu);
++
++ rockchip_clk_register_branches(ctx, rk3528_vpu_clk_branches,
++ nr_vpu_branches);
++ }
++
+ rk3528_rst_init(np, reg_base);
+
+ rockchip_register_restart_notifier(ctx, RK3528_GLB_SRST_FST, NULL);
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -218,6 +218,9 @@ struct clk;
+ #define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+ #define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
+ #define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
++#define RK3528_SDMMC_CON(x) ((x) * 0x4 + 0x24)
++#define RK3528_SDIO0_CON(x) ((x) * 0x4 + 0x4)
++#define RK3528_SDIO1_CON(x) ((x) * 0x4 + 0xc)
+ #define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
+ #define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
+ #define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
+@@ -407,6 +410,8 @@ enum rockchip_grf_type {
+ grf_type_pmu0,
+ grf_type_pmu1,
+ grf_type_ioc,
++ grf_type_vo,
++ grf_type_vpu,
+ };
+
+ /* ceil(sqrt(enums in rockchip_grf_type - 1)) */
--- /dev/null
+From 276036283716b9135525b195675ea42801bde204 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Thu, 15 May 2025 10:26:52 +0200
+Subject: [PATCH] clk: rockchip: rk3528: add slab.h header include
+
+The newly added GRF types introduced kzalloc usage into the rk3528.
+At least for the similar rk3576 driver, the kernel-test-robot reported the
+missing prototype, which warranted adding a slab.h include.
+
+While it did not complain about the rk3528, so the header might be included
+"accidentially" right now, add a real include to make sure we keep it
+included in the future.
+
+Fixes: 306d2f5ddaa7 ("clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region")
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250515082652.2503063-2-heiko@sntech.de
+---
+ drivers/clk/rockchip/clk-rk3528.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/clk/rockchip/clk-rk3528.c
++++ b/drivers/clk/rockchip/clk-rk3528.c
+@@ -12,6 +12,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/mfd/syscon.h>
+ #include <linux/minmax.h>
++#include <linux/slab.h>
+
+ #include <dt-bindings/clock/rockchip,rk3528-cru.h>
+
--- /dev/null
+From 8358102806c619d8d6c814010173617fb374b77e Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 18 May 2025 22:06:48 +0000
+Subject: [PATCH] dt-bindings: power: rockchip: Add support for RK3528
+
+Add the compatible string and power domains for RK3528 SoC.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20250518220707.669515-2-jonas@kwiboo.se
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ .../power/rockchip,power-controller.yaml | 1 +
+ .../dt-bindings/power/rockchip,rk3528-power.h | 19 +++++++++++++++++++
+ 2 files changed, 20 insertions(+)
+ create mode 100644 include/dt-bindings/power/rockchip,rk3528-power.h
+
+--- a/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
++++ b/Documentation/devicetree/bindings/power/rockchip,power-controller.yaml
+@@ -40,6 +40,7 @@ properties:
+ - rockchip,rk3366-power-controller
+ - rockchip,rk3368-power-controller
+ - rockchip,rk3399-power-controller
++ - rockchip,rk3528-power-controller
+ - rockchip,rk3568-power-controller
+ - rockchip,rk3576-power-controller
+ - rockchip,rk3588-power-controller
+--- /dev/null
++++ b/include/dt-bindings/power/rockchip,rk3528-power.h
+@@ -0,0 +1,19 @@
++/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
++#ifndef __DT_BINDINGS_POWER_RK3528_POWER_H__
++#define __DT_BINDINGS_POWER_RK3528_POWER_H__
++
++#define RK3528_PD_PMU 0
++#define RK3528_PD_BUS 1
++#define RK3528_PD_DDR 2
++#define RK3528_PD_MSCH 3
++
++/* VD_GPU */
++#define RK3528_PD_GPU 4
++
++/* VD_LOGIC */
++#define RK3528_PD_RKVDEC 5
++#define RK3528_PD_RKVENC 6
++#define RK3528_PD_VO 7
++#define RK3528_PD_VPU 8
++
++#endif
--- /dev/null
+From 58ebba35ddab4868c921f970b60a77032362ef4c Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Wed, 5 Feb 2025 14:15:53 +0800
+Subject: [PATCH] pmdomain: rockchip: Add smc call to inform firmware
+
+Inform firmware to keep the power domain on or off.
+
+Suggested-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Acked-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/1738736156-119203-5-git-send-email-shawn.lin@rock-chips.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/pmdomain/rockchip/pm-domains.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/pmdomain/rockchip/pm-domains.c
++++ b/drivers/pmdomain/rockchip/pm-domains.c
+@@ -5,6 +5,7 @@
+ * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
+ */
+
++#include <linux/arm-smccc.h>
+ #include <linux/io.h>
+ #include <linux/iopoll.h>
+ #include <linux/err.h>
+@@ -20,6 +21,7 @@
+ #include <linux/regmap.h>
+ #include <linux/mfd/syscon.h>
+ #include <soc/rockchip/pm_domains.h>
++#include <soc/rockchip/rockchip_sip.h>
+ #include <dt-bindings/power/px30-power.h>
+ #include <dt-bindings/power/rockchip,rv1126-power.h>
+ #include <dt-bindings/power/rk3036-power.h>
+@@ -540,6 +542,7 @@ static void rockchip_do_pmu_set_power_do
+ struct generic_pm_domain *genpd = &pd->genpd;
+ u32 pd_pwr_offset = pd->info->pwr_offset;
+ bool is_on, is_mem_on = false;
++ struct arm_smccc_res res;
+
+ if (pd->info->pwr_mask == 0)
+ return;
+@@ -567,6 +570,11 @@ static void rockchip_do_pmu_set_power_do
+ genpd->name, is_on);
+ return;
+ }
++
++ /* Inform firmware to keep this pd on or off */
++ arm_smccc_smc(ROCKCHIP_SIP_SUSPEND_MODE, ROCKCHIP_SLEEP_PD_CONFIG,
++ pmu->info->pwr_offset + pd_pwr_offset,
++ pd->info->pwr_mask, on, 0, 0, 0, &res);
+ }
+
+ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
--- /dev/null
+From 61eeb9678789644f118eff608d9031b5de4f719d Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Wed, 19 Feb 2025 08:58:09 +0800
+Subject: [PATCH] pmdomain: rockchip: Check if SMC could be handled by TA
+
+Non-existent trusted-firmware could lead to SMC calls into some unset
+location, that breaks the system. Let's check that it's supported before
+executing the SMC.
+
+Reported-by: Steven Price <steven.price@arm.com>
+Suggested-by: Heiko Stuebner <heiko@sntech.de>
+Fixes: 58ebba35ddab ("pmdomain: rockchip: Add smc call to inform firmware")
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Steven Price <steven.price@arm.com>
+Link: https://lore.kernel.org/r/1739926689-151827-1-git-send-email-shawn.lin@rock-chips.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/pmdomain/rockchip/pm-domains.c | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/pmdomain/rockchip/pm-domains.c
++++ b/drivers/pmdomain/rockchip/pm-domains.c
+@@ -572,9 +572,10 @@ static void rockchip_do_pmu_set_power_do
+ }
+
+ /* Inform firmware to keep this pd on or off */
+- arm_smccc_smc(ROCKCHIP_SIP_SUSPEND_MODE, ROCKCHIP_SLEEP_PD_CONFIG,
+- pmu->info->pwr_offset + pd_pwr_offset,
+- pd->info->pwr_mask, on, 0, 0, 0, &res);
++ if (arm_smccc_1_1_get_conduit() != SMCCC_CONDUIT_NONE)
++ arm_smccc_smc(ROCKCHIP_SIP_SUSPEND_MODE, ROCKCHIP_SLEEP_PD_CONFIG,
++ pmu->info->pwr_offset + pd_pwr_offset,
++ pd->info->pwr_mask, on, 0, 0, 0, &res);
+ }
+
+ static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
--- /dev/null
+From bc4bc2a1609712e6c5de01be8a20341b710dc99b Mon Sep 17 00:00:00 2001
+From: Ulf Hansson <ulf.hansson@linaro.org>
+Date: Mon, 24 Feb 2025 13:05:29 +0100
+Subject: [PATCH] pmdomain: rockchip: Fix build error
+
+To resolve the build error with undefined reference to
+`arm_smccc_1_1_get_conduit', let's add a build dependency to
+HAVE_ARM_SMCCC_DISCOVERY.
+
+Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
+Fixes: 61eeb9678789 ("pmdomain: rockchip: Check if SMC could be handled by TA")
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/pmdomain/rockchip/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/pmdomain/rockchip/Kconfig
++++ b/drivers/pmdomain/rockchip/Kconfig
+@@ -4,6 +4,7 @@ if ARCH_ROCKCHIP || COMPILE_TEST
+ config ROCKCHIP_PM_DOMAINS
+ bool "Rockchip generic power domain"
+ depends on PM
++ depends on HAVE_ARM_SMCCC_DISCOVERY
+ select PM_GENERIC_DOMAINS
+ help
+ Say y here to enable power domain support.
--- /dev/null
+From 3068b386232f0a7d84da6d1366dbd0b7926c5652 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 18 May 2025 22:06:49 +0000
+Subject: [PATCH] pmdomain: rockchip: Add support for RK3528
+
+Add configuration and power domains for RK3528 SoC.
+
+Only PD_GPU can fully be powered down. PD_RKVDEC, PD_RKVENC, PD_VO and
+PD_VPU are used by miscellaneous devices in RK3528.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250518220707.669515-3-jonas@kwiboo.se
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/pmdomain/rockchip/pm-domains.c | 27 ++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/drivers/pmdomain/rockchip/pm-domains.c
++++ b/drivers/pmdomain/rockchip/pm-domains.c
+@@ -34,6 +34,7 @@
+ #include <dt-bindings/power/rk3366-power.h>
+ #include <dt-bindings/power/rk3368-power.h>
+ #include <dt-bindings/power/rk3399-power.h>
++#include <dt-bindings/power/rockchip,rk3528-power.h>
+ #include <dt-bindings/power/rk3568-power.h>
+ #include <dt-bindings/power/rockchip,rk3576-power.h>
+ #include <dt-bindings/power/rk3588-power.h>
+@@ -196,6 +197,9 @@ struct rockchip_pmu {
+ #define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
+ DOMAIN(name, pwr, status, req, req, req, wakeup)
+
++#define DOMAIN_RK3528(name, pwr, req) \
++ DOMAIN_M(name, pwr, pwr, req, req, req, false)
++
+ #define DOMAIN_RK3568(name, pwr, req, wakeup) \
+ DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
+
+@@ -1139,6 +1143,14 @@ static const struct rockchip_domain_info
+ [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399("sdioaudio", BIT(31), BIT(31), BIT(29), true),
+ };
+
++static const struct rockchip_domain_info rk3528_pm_domains[] = {
++ [RK3528_PD_GPU] = DOMAIN_RK3528("gpu", BIT(0), BIT(4)),
++ [RK3528_PD_RKVDEC] = DOMAIN_RK3528("vdec", 0, BIT(5)),
++ [RK3528_PD_RKVENC] = DOMAIN_RK3528("venc", 0, BIT(6)),
++ [RK3528_PD_VO] = DOMAIN_RK3528("vo", 0, BIT(7)),
++ [RK3528_PD_VPU] = DOMAIN_RK3528("vpu", 0, BIT(8)),
++};
++
+ static const struct rockchip_domain_info rk3568_pm_domains[] = {
+ [RK3568_PD_NPU] = DOMAIN_RK3568("npu", BIT(1), BIT(2), false),
+ [RK3568_PD_GPU] = DOMAIN_RK3568("gpu", BIT(0), BIT(1), false),
+@@ -1340,6 +1352,17 @@ static const struct rockchip_pmu_info rk
+ .domain_info = rk3399_pm_domains,
+ };
+
++static const struct rockchip_pmu_info rk3528_pmu = {
++ .pwr_offset = 0x1210,
++ .status_offset = 0x1230,
++ .req_offset = 0x1110,
++ .idle_offset = 0x1128,
++ .ack_offset = 0x1120,
++
++ .num_domains = ARRAY_SIZE(rk3528_pm_domains),
++ .domain_info = rk3528_pm_domains,
++};
++
+ static const struct rockchip_pmu_info rk3568_pmu = {
+ .pwr_offset = 0xa0,
+ .status_offset = 0x98,
+@@ -1439,6 +1462,10 @@ static const struct of_device_id rockchi
+ .data = (void *)&rk3399_pmu,
+ },
+ {
++ .compatible = "rockchip,rk3528-power-controller",
++ .data = (void *)&rk3528_pmu,
++ },
++ {
+ .compatible = "rockchip,rk3568-power-controller",
+ .data = (void *)&rk3568_pmu,
+ },
--- /dev/null
+From 9a9f71b2a3a7491c10ceea699e1999298db5c596 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 10 Jun 2025 14:32:37 +0200
+Subject: [PATCH] thermal/drivers/rockchip: Rename rk_tsadcv3_tshut_mode
+
+The "v" version specifier here refers to the hardware IP revision.
+Mainline deviated from downstream here by calling the v4 revision v3 as
+it didn't support the v3 hardware revision at all.
+
+This creates needless confusion, so rename it to rk_tsadcv4_tshut_mode
+to be consistent with what the hardware wants to be called.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-1-b6e9efbf1015@collabora.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/rockchip_thermal.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -1045,7 +1045,7 @@ static void rk_tsadcv2_tshut_mode(int ch
+ writel_relaxed(val, regs + TSADCV2_INT_EN);
+ }
+
+-static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs,
++static void rk_tsadcv4_tshut_mode(int chn, void __iomem *regs,
+ enum tshut_mode mode)
+ {
+ u32 val_gpio, val_cru;
+@@ -1297,7 +1297,7 @@ static const struct rockchip_tsadc_chip
+ .get_temp = rk_tsadcv4_get_temp,
+ .set_alarm_temp = rk_tsadcv3_alarm_temp,
+ .set_tshut_temp = rk_tsadcv3_tshut_temp,
+- .set_tshut_mode = rk_tsadcv3_tshut_mode,
++ .set_tshut_mode = rk_tsadcv4_tshut_mode,
+ .table = {
+ .id = rk3588_code_table,
+ .length = ARRAY_SIZE(rk3588_code_table),
--- /dev/null
+From feb69bccf5d3eb31918df86638abc82594390ba5 Mon Sep 17 00:00:00 2001
+From: Ye Zhang <ye.zhang@rock-chips.com>
+Date: Tue, 10 Jun 2025 14:32:39 +0200
+Subject: [PATCH] thermal/drivers/rockchip: Support RK3576 SoC in the thermal
+ driver
+
+The RK3576 SoC has six TS-ADC channels: TOP, BIG_CORE, LITTLE_CORE,
+DDR, NPU and GPU.
+
+Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
+[ported to mainline, reworded commit message]
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-3-b6e9efbf1015@collabora.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/rockchip_thermal.c | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -1284,6 +1284,28 @@ static const struct rockchip_tsadc_chip
+ },
+ };
+
++static const struct rockchip_tsadc_chip rk3576_tsadc_data = {
++ /* top, big_core, little_core, ddr, npu, gpu */
++ .chn_offset = 0,
++ .chn_num = 6, /* six channels for tsadc */
++ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
++ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
++ .tshut_temp = 95000,
++ .initialize = rk_tsadcv8_initialize,
++ .irq_ack = rk_tsadcv4_irq_ack,
++ .control = rk_tsadcv4_control,
++ .get_temp = rk_tsadcv4_get_temp,
++ .set_alarm_temp = rk_tsadcv3_alarm_temp,
++ .set_tshut_temp = rk_tsadcv3_tshut_temp,
++ .set_tshut_mode = rk_tsadcv4_tshut_mode,
++ .table = {
++ .id = rk3588_code_table,
++ .length = ARRAY_SIZE(rk3588_code_table),
++ .data_mask = TSADCV4_DATA_MASK,
++ .mode = ADC_INCREMENT,
++ },
++};
++
+ static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
+ /* top, big_core0, big_core1, little_core, center, gpu, npu */
+ .chn_offset = 0,
+@@ -1343,6 +1365,10 @@ static const struct of_device_id of_rock
+ .data = (void *)&rk3568_tsadc_data,
+ },
+ {
++ .compatible = "rockchip,rk3576-tsadc",
++ .data = (void *)&rk3576_tsadc_data,
++ },
++ {
+ .compatible = "rockchip,rk3588-tsadc",
+ .data = (void *)&rk3588_tsadc_data,
+ },
--- /dev/null
+From ae332ec0009d762982540635411caefeafa92a5b Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 10 Jun 2025 14:32:41 +0200
+Subject: [PATCH] thermal/drivers/rockchip: Support reading trim values from
+ OTP
+
+Many of the Rockchip SoCs support storing trim values for the sensors in
+factory programmable memory. These values specify a fixed offset from
+the sensor's returned temperature to get a more accurate picture of what
+temperature the silicon is actually at.
+
+The way this is implemented is with various OTP cells, which may be
+absent. There may both be whole-TSADC trim values, as well as per-sensor
+trim values.
+
+In the downstream driver, whole-chip trim values override the per-sensor
+trim values. This rewrite of the functionality changes the semantics to
+something I see as slightly more useful: allow the whole-chip trim
+values to serve as a fallback for lacking per-sensor trim values,
+instead of overriding already present sensor trim values.
+
+Additionally, the chip may specify an offset (trim_base, trim_base_frac)
+in degrees celsius and degrees decicelsius respectively which defines
+what the basis is from which the trim, if any, should be calculated
+from. By default, this is 30 degrees Celsius, but the chip can once
+again specify a different value through OTP cells.
+
+The implementation of these trim calculations have been tested
+extensively on an RK3576, where it was confirmed to get rid of pesky 1.8
+degree Celsius offsets between certain sensors.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-5-b6e9efbf1015@collabora.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/thermal/rockchip_thermal.c | 221 ++++++++++++++++++++++++++---
+ 1 file changed, 202 insertions(+), 19 deletions(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -9,6 +9,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
++#include <linux/nvmem-consumer.h>
+ #include <linux/of.h>
+ #include <linux/of_address.h>
+ #include <linux/of_irq.h>
+@@ -69,16 +70,18 @@ struct chip_tsadc_table {
+ * struct rockchip_tsadc_chip - hold the private data of tsadc chip
+ * @chn_offset: the channel offset of the first channel
+ * @chn_num: the channel number of tsadc chip
+- * @tshut_temp: the hardware-controlled shutdown temperature value
++ * @trim_slope: used to convert the trim code to a temperature in millicelsius
++ * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim
+ * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
+ * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
+ * @initialize: SoC special initialize tsadc controller method
+ * @irq_ack: clear the interrupt
+ * @control: enable/disable method for the tsadc controller
+- * @get_temp: get the temperature
++ * @get_temp: get the raw temperature, unadjusted by trim
+ * @set_alarm_temp: set the high temperature interrupt
+ * @set_tshut_temp: set the hardware-controlled shutdown temperature
+ * @set_tshut_mode: set the hardware-controlled shutdown mode
++ * @get_trim_code: convert a hardware temperature code to one adjusted for by trim
+ * @table: the chip-specific conversion table
+ */
+ struct rockchip_tsadc_chip {
+@@ -86,6 +89,9 @@ struct rockchip_tsadc_chip {
+ int chn_offset;
+ int chn_num;
+
++ /* Used to convert trim code to trim temp */
++ int trim_slope;
++
+ /* The hardware-controlled tshut property */
+ int tshut_temp;
+ enum tshut_mode tshut_mode;
+@@ -105,6 +111,8 @@ struct rockchip_tsadc_chip {
+ int (*set_tshut_temp)(const struct chip_tsadc_table *table,
+ int chn, void __iomem *reg, int temp);
+ void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
++ int (*get_trim_code)(const struct chip_tsadc_table *table,
++ int code, int trim_base, int trim_base_frac);
+
+ /* Per-table methods */
+ struct chip_tsadc_table table;
+@@ -114,12 +122,16 @@ struct rockchip_tsadc_chip {
+ * struct rockchip_thermal_sensor - hold the information of thermal sensor
+ * @thermal: pointer to the platform/configuration data
+ * @tzd: pointer to a thermal zone
++ * @of_node: pointer to the device_node representing this sensor, if any
+ * @id: identifier of the thermal sensor
++ * @trim_temp: per-sensor trim temperature value
+ */
+ struct rockchip_thermal_sensor {
+ struct rockchip_thermal_data *thermal;
+ struct thermal_zone_device *tzd;
++ struct device_node *of_node;
+ int id;
++ int trim_temp;
+ };
+
+ /**
+@@ -132,7 +144,11 @@ struct rockchip_thermal_sensor {
+ * @pclk: the advanced peripherals bus clock
+ * @grf: the general register file will be used to do static set by software
+ * @regs: the base address of tsadc controller
+- * @tshut_temp: the hardware-controlled shutdown temperature value
++ * @trim_base: major component of sensor trim value, in Celsius
++ * @trim_base_frac: minor component of sensor trim value, in Decicelsius
++ * @trim: fallback thermal trim value for each channel
++ * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim
++ * @trim_temp: the fallback trim temperature for the whole sensor
+ * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
+ * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
+ */
+@@ -149,7 +165,12 @@ struct rockchip_thermal_data {
+ struct regmap *grf;
+ void __iomem *regs;
+
++ int trim_base;
++ int trim_base_frac;
++ int trim;
++
+ int tshut_temp;
++ int trim_temp;
+ enum tshut_mode tshut_mode;
+ enum tshut_polarity tshut_polarity;
+ };
+@@ -249,6 +270,9 @@ struct rockchip_thermal_data {
+
+ #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
+
++
++#define RK_MAX_TEMP (180000)
++
+ /**
+ * struct tsadc_table - code to temperature conversion table
+ * @code: the value of adc channel
+@@ -1061,6 +1085,15 @@ static void rk_tsadcv4_tshut_mode(int ch
+ writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
+ }
+
++static int rk_tsadcv2_get_trim_code(const struct chip_tsadc_table *table,
++ int code, int trim_base, int trim_base_frac)
++{
++ int temp = trim_base * 1000 + trim_base_frac * 100;
++ u32 base_code = rk_tsadcv2_temp_to_code(table, temp);
++
++ return code - base_code;
++}
++
+ static const struct rockchip_tsadc_chip px30_tsadc_data = {
+ /* cpu, gpu */
+ .chn_offset = 0,
+@@ -1298,6 +1331,8 @@ static const struct rockchip_tsadc_chip
+ .set_alarm_temp = rk_tsadcv3_alarm_temp,
+ .set_tshut_temp = rk_tsadcv3_tshut_temp,
+ .set_tshut_mode = rk_tsadcv4_tshut_mode,
++ .get_trim_code = rk_tsadcv2_get_trim_code,
++ .trim_slope = 923,
+ .table = {
+ .id = rk3588_code_table,
+ .length = ARRAY_SIZE(rk3588_code_table),
+@@ -1413,7 +1448,7 @@ static int rockchip_thermal_set_trips(st
+ __func__, sensor->id, low, high);
+
+ return tsadc->set_alarm_temp(&tsadc->table,
+- sensor->id, thermal->regs, high);
++ sensor->id, thermal->regs, high + sensor->trim_temp);
+ }
+
+ static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_temp)
+@@ -1425,6 +1460,8 @@ static int rockchip_thermal_get_temp(str
+
+ retval = tsadc->get_temp(&tsadc->table,
+ sensor->id, thermal->regs, out_temp);
++ *out_temp -= sensor->trim_temp;
++
+ return retval;
+ }
+
+@@ -1433,6 +1470,104 @@ static const struct thermal_zone_device_
+ .set_trips = rockchip_thermal_set_trips,
+ };
+
++/**
++ * rockchip_get_efuse_value - read an OTP cell from a device node
++ * @np: pointer to the device node with the nvmem-cells property
++ * @cell_name: name of cell that should be read
++ * @value: pointer to where the read value will be placed
++ *
++ * Return: Negative errno on failure, during which *value will not be touched,
++ * or 0 on success.
++ */
++static int rockchip_get_efuse_value(struct device_node *np, const char *cell_name,
++ int *value)
++{
++ struct nvmem_cell *cell;
++ int ret = 0;
++ size_t len;
++ u8 *buf;
++ int i;
++
++ cell = of_nvmem_cell_get(np, cell_name);
++ if (IS_ERR(cell))
++ return PTR_ERR(cell);
++
++ buf = nvmem_cell_read(cell, &len);
++
++ nvmem_cell_put(cell);
++
++ if (IS_ERR(buf))
++ return PTR_ERR(buf);
++
++ if (len > sizeof(*value)) {
++ ret = -ERANGE;
++ goto exit;
++ }
++
++ /* Copy with implicit endian conversion */
++ *value = 0;
++ for (i = 0; i < len; i++)
++ *value |= (int) buf[i] << (8 * i);
++
++exit:
++ kfree(buf);
++ return ret;
++}
++
++static int rockchip_get_trim_configuration(struct device *dev, struct device_node *np,
++ struct rockchip_thermal_data *thermal)
++{
++ const struct rockchip_tsadc_chip *tsadc = thermal->chip;
++ int trim_base = 0, trim_base_frac = 0, trim = 0;
++ int trim_code;
++ int ret;
++
++ thermal->trim_base = 0;
++ thermal->trim_base_frac = 0;
++ thermal->trim = 0;
++
++ if (!tsadc->get_trim_code)
++ return 0;
++
++ ret = rockchip_get_efuse_value(np, "trim_base", &trim_base);
++ if (ret < 0) {
++ if (ret == -ENOENT) {
++ trim_base = 30;
++ dev_dbg(dev, "trim_base is absent, defaulting to 30\n");
++ } else {
++ dev_err(dev, "failed reading nvmem value of trim_base: %pe\n",
++ ERR_PTR(ret));
++ return ret;
++ }
++ }
++ ret = rockchip_get_efuse_value(np, "trim_base_frac", &trim_base_frac);
++ if (ret < 0) {
++ if (ret == -ENOENT) {
++ dev_dbg(dev, "trim_base_frac is absent, defaulting to 0\n");
++ } else {
++ dev_err(dev, "failed reading nvmem value of trim_base_frac: %pe\n",
++ ERR_PTR(ret));
++ return ret;
++ }
++ }
++ thermal->trim_base = trim_base;
++ thermal->trim_base_frac = trim_base_frac;
++
++ /*
++ * If the tsadc node contains the trim property, then it is used in the
++ * absence of per-channel trim values
++ */
++ if (!rockchip_get_efuse_value(np, "trim", &trim))
++ thermal->trim = trim;
++ if (trim) {
++ trim_code = tsadc->get_trim_code(&tsadc->table, trim,
++ trim_base, trim_base_frac);
++ thermal->trim_temp = thermal->chip->trim_slope * trim_code;
++ }
++
++ return 0;
++}
++
+ static int rockchip_configure_from_dt(struct device *dev,
+ struct device_node *np,
+ struct rockchip_thermal_data *thermal)
+@@ -1493,6 +1628,8 @@ static int rockchip_configure_from_dt(st
+ if (IS_ERR(thermal->grf))
+ dev_warn(dev, "Missing rockchip,grf property\n");
+
++ rockchip_get_trim_configuration(dev, np, thermal);
++
+ return 0;
+ }
+
+@@ -1503,23 +1640,50 @@ rockchip_thermal_register_sensor(struct
+ int id)
+ {
+ const struct rockchip_tsadc_chip *tsadc = thermal->chip;
++ struct device *dev = &pdev->dev;
++ int trim = thermal->trim;
++ int trim_code, tshut_temp;
++ int trim_temp = 0;
+ int error;
+
++ if (thermal->trim_temp)
++ trim_temp = thermal->trim_temp;
++
++ if (tsadc->get_trim_code && sensor->of_node) {
++ error = rockchip_get_efuse_value(sensor->of_node, "trim", &trim);
++ if (error < 0 && error != -ENOENT) {
++ dev_err(dev, "failed reading trim of sensor %d: %pe\n",
++ id, ERR_PTR(error));
++ return error;
++ }
++ if (trim) {
++ trim_code = tsadc->get_trim_code(&tsadc->table, trim,
++ thermal->trim_base,
++ thermal->trim_base_frac);
++ trim_temp = thermal->chip->trim_slope * trim_code;
++ }
++ }
++
++ sensor->trim_temp = trim_temp;
++
++ dev_dbg(dev, "trim of sensor %d is %d\n", id, sensor->trim_temp);
++
++ tshut_temp = min(thermal->tshut_temp + sensor->trim_temp, RK_MAX_TEMP);
++
+ tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
+
+- error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
+- thermal->tshut_temp);
++ error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, tshut_temp);
+ if (error)
+- dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
+- __func__, thermal->tshut_temp, error);
++ dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
++ __func__, tshut_temp, error);
+
+ sensor->thermal = thermal;
+ sensor->id = id;
+- sensor->tzd = devm_thermal_of_zone_register(&pdev->dev, id, sensor,
++ sensor->tzd = devm_thermal_of_zone_register(dev, id, sensor,
+ &rockchip_of_thermal_ops);
+ if (IS_ERR(sensor->tzd)) {
+ error = PTR_ERR(sensor->tzd);
+- dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
++ dev_err(dev, "failed to register sensor %d: %d\n",
+ id, error);
+ return error;
+ }
+@@ -1542,9 +1706,11 @@ static int rockchip_thermal_probe(struct
+ {
+ struct device_node *np = pdev->dev.of_node;
+ struct rockchip_thermal_data *thermal;
++ struct device_node *child;
+ int irq;
+ int i;
+ int error;
++ u32 chn;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+@@ -1595,6 +1761,18 @@ static int rockchip_thermal_probe(struct
+ thermal->chip->initialize(thermal->grf, thermal->regs,
+ thermal->tshut_polarity);
+
++ for_each_available_child_of_node(np, child) {
++ if (!of_property_read_u32(child, "reg", &chn)) {
++ if (chn < thermal->chip->chn_num)
++ thermal->sensors[chn].of_node = child;
++ else
++ dev_warn(&pdev->dev,
++ "sensor address (%d) too large, ignoring its trim\n",
++ chn);
++ }
++
++ }
++
+ for (i = 0; i < thermal->chip->chn_num; i++) {
+ error = rockchip_thermal_register_sensor(pdev, thermal,
+ &thermal->sensors[i],
+@@ -1664,8 +1842,11 @@ static int __maybe_unused rockchip_therm
+ static int __maybe_unused rockchip_thermal_resume(struct device *dev)
+ {
+ struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
+- int i;
++ const struct rockchip_tsadc_chip *tsadc = thermal->chip;
++ struct rockchip_thermal_sensor *sensor;
++ int tshut_temp;
+ int error;
++ int i;
+
+ error = clk_enable(thermal->clk);
+ if (error)
+@@ -1679,21 +1860,23 @@ static int __maybe_unused rockchip_therm
+
+ rockchip_thermal_reset_controller(thermal->reset);
+
+- thermal->chip->initialize(thermal->grf, thermal->regs,
+- thermal->tshut_polarity);
++ tsadc->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity);
+
+ for (i = 0; i < thermal->chip->chn_num; i++) {
+- int id = thermal->sensors[i].id;
++ sensor = &thermal->sensors[i];
++
++ tshut_temp = min(thermal->tshut_temp + sensor->trim_temp,
++ RK_MAX_TEMP);
+
+- thermal->chip->set_tshut_mode(id, thermal->regs,
++ tsadc->set_tshut_mode(sensor->id, thermal->regs,
+ thermal->tshut_mode);
+
+- error = thermal->chip->set_tshut_temp(&thermal->chip->table,
+- id, thermal->regs,
+- thermal->tshut_temp);
++ error = tsadc->set_tshut_temp(&thermal->chip->table,
++ sensor->id, thermal->regs,
++ tshut_temp);
+ if (error)
+ dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
+- __func__, thermal->tshut_temp, error);
++ __func__, tshut_temp, error);
+ }
+
+ thermal->chip->control(thermal->regs, true);
--- /dev/null
+From 591ae6bed250e4067db926313ff7279d23a1c7d1 Mon Sep 17 00:00:00 2001
+From: Ye Zhang <ye.zhang@rock-chips.com>
+Date: Tue, 12 Nov 2024 09:54:05 +0800
+Subject: [PATCH] gpio: rockchip: explan the format of the GPIO version ID
+
+Remove redundant comments and provide a detailed explanation of the
+GPIO version ID.
+
+Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20241112015408.3139996-2-ye.zhang@rock-chips.com
+Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
+---
+ drivers/gpio/gpio-rockchip.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpio/gpio-rockchip.c
++++ b/drivers/gpio/gpio-rockchip.c
+@@ -25,9 +25,15 @@
+ #include "../pinctrl/core.h"
+ #include "../pinctrl/pinctrl-rockchip.h"
+
++/*
++ * Version ID Register
++ * Bits [31:24] - Major Version
++ * Bits [23:16] - Minor Version
++ * Bits [15:0] - Revision Number
++ */
+ #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
+-#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
+-#define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
++#define GPIO_TYPE_V2 (0x01000C2B)
++#define GPIO_TYPE_V2_1 (0x0101157C)
+
+ static const struct rockchip_gpio_regs gpio_regs_v1 = {
+ .port_dr = 0x00,
--- /dev/null
+From 41209307cad7f14c387c68375a93b50e54261a53 Mon Sep 17 00:00:00 2001
+From: Ye Zhang <ye.zhang@rock-chips.com>
+Date: Tue, 12 Nov 2024 09:54:06 +0800
+Subject: [PATCH] gpio: rockchip: change the GPIO version judgment logic
+
+Have a list of valid IDs and default to -ENODEV.
+
+Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Link: https://lore.kernel.org/r/20241112015408.3139996-3-ye.zhang@rock-chips.com
+Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
+---
+ drivers/gpio/gpio-rockchip.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpio/gpio-rockchip.c
++++ b/drivers/gpio/gpio-rockchip.c
+@@ -660,8 +660,9 @@ static int rockchip_get_bank_data(struct
+ clk_prepare_enable(bank->clk);
+ id = readl(bank->reg_base + gpio_regs_v2.version_id);
+
+- /* If not gpio v2, that is default to v1. */
+- if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) {
++ switch (id) {
++ case GPIO_TYPE_V2:
++ case GPIO_TYPE_V2_1:
+ bank->gpio_regs = &gpio_regs_v2;
+ bank->gpio_type = GPIO_TYPE_V2;
+ bank->db_clk = of_clk_get(bank->of_node, 1);
+@@ -670,9 +671,14 @@ static int rockchip_get_bank_data(struct
+ clk_disable_unprepare(bank->clk);
+ return -EINVAL;
+ }
+- } else {
++ break;
++ case GPIO_TYPE_V1:
+ bank->gpio_regs = &gpio_regs_v1;
+ bank->gpio_type = GPIO_TYPE_V1;
++ break;
++ default:
++ dev_err(bank->dev, "unsupported version ID: 0x%08x\n", id);
++ return -ENODEV;
+ }
+
+ return 0;
--- /dev/null
+From 8bcbd0379c05c66ce2e842c7e8901aa317cdf04e Mon Sep 17 00:00:00 2001
+From: Ye Zhang <ye.zhang@rock-chips.com>
+Date: Tue, 12 Nov 2024 09:54:07 +0800
+Subject: [PATCH] gpio: rockchip: support new version GPIO
+
+Support the next version GPIO controller on SoCs like rk3576.
+
+Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
+Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20241112015408.3139996-4-ye.zhang@rock-chips.com
+Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
+---
+ drivers/gpio/gpio-rockchip.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/gpio/gpio-rockchip.c
++++ b/drivers/gpio/gpio-rockchip.c
+@@ -34,6 +34,7 @@
+ #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
+ #define GPIO_TYPE_V2 (0x01000C2B)
+ #define GPIO_TYPE_V2_1 (0x0101157C)
++#define GPIO_TYPE_V2_2 (0x010219C8)
+
+ static const struct rockchip_gpio_regs gpio_regs_v1 = {
+ .port_dr = 0x00,
+@@ -663,6 +664,7 @@ static int rockchip_get_bank_data(struct
+ switch (id) {
+ case GPIO_TYPE_V2:
+ case GPIO_TYPE_V2_1:
++ case GPIO_TYPE_V2_2:
+ bank->gpio_regs = &gpio_regs_v2;
+ bank->gpio_type = GPIO_TYPE_V2;
+ bank->db_clk = of_clk_get(bank->of_node, 1);
--- /dev/null
+From 595ad7a336bf21f9d111a033820cd95d70343bd1 Mon Sep 17 00:00:00 2001
+From: Dragan Simic <dsimic@manjaro.org>
+Date: Thu, 5 Sep 2024 10:28:23 +0200
+Subject: [PATCH] phy: phy-rockchip-inno-usb2: Handle failed extcon allocation
+ better
+
+Return the actual error code upon failure to allocate extcon device, instead
+of hardcoding -ENOMEM. Use dev_err_probe() to also log appropriate messages,
+which is fine because the containing function is used in the probe path.
+
+Helped-by: Heiko Stubner <heiko@sntech.de>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Dragan Simic <dsimic@manjaro.org>
+Link: https://lore.kernel.org/r/cc4995aa3e569be6bc23ca126b41fba82d50eeee.1725524802.git.dsimic@manjaro.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -433,7 +433,8 @@ static int rockchip_usb2phy_extcon_regis
+ rockchip_usb2phy_extcon_cable);
+
+ if (IS_ERR(edev))
+- return -ENOMEM;
++ return dev_err_probe(rphy->dev, PTR_ERR(edev),
++ "failed to allocate extcon device\n");
+
+ ret = devm_extcon_dev_register(rphy->dev, edev);
+ if (ret)
--- /dev/null
+From 86e2ed4e9a9680013ec9ab7c0428c9b8c5108efe Mon Sep 17 00:00:00 2001
+From: Frank Wang <frank.wang@rock-chips.com>
+Date: Wed, 16 Oct 2024 15:37:10 +0800
+Subject: [PATCH] phy: rockchip: inno-usb2: convert clock management to bulk
+
+Since some Rockchip SoCs (e.g RK3576) have more than one clock,
+this converts the clock management from single to bulk method to
+make the driver more flexible.
+
+Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20241016073713.14133-1-frawang.cn@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 45 +++++++++++++++----
+ 1 file changed, 37 insertions(+), 8 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -229,9 +229,10 @@ struct rockchip_usb2phy_port {
+ * @dev: pointer to device.
+ * @grf: General Register Files regmap.
+ * @usbgrf: USB General Register Files regmap.
+- * @clk: clock struct of phy input clk.
++ * @clks: array of phy input clocks.
+ * @clk480m: clock struct of phy output clk.
+ * @clk480m_hw: clock struct of phy output clk management.
++ * @num_clks: number of phy input clocks.
+ * @phy_reset: phy reset control.
+ * @chg_state: states involved in USB charger detection.
+ * @chg_type: USB charger types.
+@@ -246,9 +247,10 @@ struct rockchip_usb2phy {
+ struct device *dev;
+ struct regmap *grf;
+ struct regmap *usbgrf;
+- struct clk *clk;
++ struct clk_bulk_data *clks;
+ struct clk *clk480m;
+ struct clk_hw clk480m_hw;
++ int num_clks;
+ struct reset_control *phy_reset;
+ enum usb_chg_state chg_state;
+ enum power_supply_type chg_type;
+@@ -310,6 +312,13 @@ static int rockchip_usb2phy_reset(struct
+ return 0;
+ }
+
++static void rockchip_usb2phy_clk_bulk_disable(void *data)
++{
++ struct rockchip_usb2phy *rphy = data;
++
++ clk_bulk_disable_unprepare(rphy->num_clks, rphy->clks);
++}
++
+ static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
+ {
+ struct rockchip_usb2phy *rphy =
+@@ -376,7 +385,9 @@ rockchip_usb2phy_clk480m_register(struct
+ {
+ struct device_node *node = rphy->dev->of_node;
+ struct clk_init_data init;
++ struct clk *refclk = NULL;
+ const char *clk_name;
++ int i;
+ int ret = 0;
+
+ init.flags = 0;
+@@ -386,8 +397,15 @@ rockchip_usb2phy_clk480m_register(struct
+ /* optional override of the clockname */
+ of_property_read_string(node, "clock-output-names", &init.name);
+
+- if (rphy->clk) {
+- clk_name = __clk_get_name(rphy->clk);
++ for (i = 0; i < rphy->num_clks; i++) {
++ if (!strncmp(rphy->clks[i].id, "phyclk", 6)) {
++ refclk = rphy->clks[i].clk;
++ break;
++ }
++ }
++
++ if (!IS_ERR(refclk)) {
++ clk_name = __clk_get_name(refclk);
+ init.parent_names = &clk_name;
+ init.num_parents = 1;
+ } else {
+@@ -1408,16 +1426,26 @@ static int rockchip_usb2phy_probe(struct
+ if (IS_ERR(rphy->phy_reset))
+ return PTR_ERR(rphy->phy_reset);
+
+- rphy->clk = devm_clk_get_optional_enabled(dev, "phyclk");
+- if (IS_ERR(rphy->clk)) {
+- return dev_err_probe(&pdev->dev, PTR_ERR(rphy->clk),
+- "failed to get phyclk\n");
+- }
++ ret = devm_clk_bulk_get_all(dev, &rphy->clks);
++ if (ret == -EPROBE_DEFER)
++ return dev_err_probe(&pdev->dev, -EPROBE_DEFER,
++ "failed to get phy clock\n");
++
++ /* Clocks are optional */
++ rphy->num_clks = ret < 0 ? 0 : ret;
+
+ ret = rockchip_usb2phy_clk480m_register(rphy);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register 480m output clock\n");
+
++ ret = clk_bulk_prepare_enable(rphy->num_clks, rphy->clks);
++ if (ret)
++ return dev_err_probe(dev, ret, "failed to enable phy clock\n");
++
++ ret = devm_add_action_or_reset(dev, rockchip_usb2phy_clk_bulk_disable, rphy);
++ if (ret)
++ return ret;
++
+ if (rphy->phy_cfg->phy_tuning) {
+ ret = rphy->phy_cfg->phy_tuning(rphy);
+ if (ret)
--- /dev/null
+From 3d7de6e870ece5a32153382df9df6fb87613335e Mon Sep 17 00:00:00 2001
+From: William Wu <william.wu@rock-chips.com>
+Date: Wed, 16 Oct 2024 15:37:13 +0800
+Subject: [PATCH] phy: rockchip: inno-usb2: Add usb2 phys support for rk3576
+
+The RK3576 SoC has two independent USB2.0 PHYs, and each PHY has
+one port. This adds device specific data for it.
+
+Signed-off-by: William Wu <william.wu@rock-chips.com>
+Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20241016073713.14133-4-frawang.cn@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 103 ++++++++++++++++++
+ 1 file changed, 103 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -1521,6 +1521,30 @@ static int rk3128_usb2phy_tuning(struct
+ BIT(2) << BIT_WRITEABLE_SHIFT | 0);
+ }
+
++static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy)
++{
++ int ret;
++ u32 reg = rphy->phy_cfg->reg;
++
++ /* Deassert SIDDQ to power on analog block */
++ ret = regmap_write(rphy->grf, reg + 0x0010, GENMASK(29, 29) | 0x0000);
++ if (ret)
++ return ret;
++
++ /* Do reset after exit IDDQ mode */
++ ret = rockchip_usb2phy_reset(rphy);
++ if (ret)
++ return ret;
++
++ /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
++ ret |= regmap_write(rphy->grf, reg + 0x000c, GENMASK(27, 24) | 0x0900);
++
++ /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
++ ret |= regmap_write(rphy->grf, reg + 0x0010, GENMASK(20, 19) | 0x0010);
++
++ return ret;
++}
++
+ static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+ {
+ int ret;
+@@ -1949,6 +1973,84 @@ static const struct rockchip_usb2phy_cfg
+ { /* sentinel */ }
+ };
+
++static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
++ {
++ .reg = 0x0,
++ .num_ports = 1,
++ .phy_tuning = rk3576_usb2phy_tuning,
++ .clkout_ctl = { 0x0008, 0, 0, 1, 0 },
++ .port_cfgs = {
++ [USB2PHY_PORT_OTG] = {
++ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
++ .bvalid_det_en = { 0x00c0, 1, 1, 0, 1 },
++ .bvalid_det_st = { 0x00c4, 1, 1, 0, 1 },
++ .bvalid_det_clr = { 0x00c8, 1, 1, 0, 1 },
++ .ls_det_en = { 0x00c0, 0, 0, 0, 1 },
++ .ls_det_st = { 0x00c4, 0, 0, 0, 1 },
++ .ls_det_clr = { 0x00c8, 0, 0, 0, 1 },
++ .disfall_en = { 0x00c0, 6, 6, 0, 1 },
++ .disfall_st = { 0x00c4, 6, 6, 0, 1 },
++ .disfall_clr = { 0x00c8, 6, 6, 0, 1 },
++ .disrise_en = { 0x00c0, 5, 5, 0, 1 },
++ .disrise_st = { 0x00c4, 5, 5, 0, 1 },
++ .disrise_clr = { 0x00c8, 5, 5, 0, 1 },
++ .utmi_avalid = { 0x0080, 1, 1, 0, 1 },
++ .utmi_bvalid = { 0x0080, 0, 0, 0, 1 },
++ .utmi_ls = { 0x0080, 5, 4, 0, 1 },
++ }
++ },
++ .chg_det = {
++ .cp_det = { 0x0080, 8, 8, 0, 1 },
++ .dcp_det = { 0x0080, 8, 8, 0, 1 },
++ .dp_det = { 0x0080, 9, 9, 1, 0 },
++ .idm_sink_en = { 0x0010, 5, 5, 1, 0 },
++ .idp_sink_en = { 0x0010, 5, 5, 0, 1 },
++ .idp_src_en = { 0x0010, 14, 14, 0, 1 },
++ .rdm_pdwn_en = { 0x0010, 14, 14, 0, 1 },
++ .vdm_src_en = { 0x0010, 7, 6, 0, 3 },
++ .vdp_src_en = { 0x0010, 7, 6, 0, 3 },
++ },
++ },
++ {
++ .reg = 0x2000,
++ .num_ports = 1,
++ .phy_tuning = rk3576_usb2phy_tuning,
++ .clkout_ctl = { 0x2008, 0, 0, 1, 0 },
++ .port_cfgs = {
++ [USB2PHY_PORT_OTG] = {
++ .phy_sus = { 0x2000, 8, 0, 0, 0x1d1 },
++ .bvalid_det_en = { 0x20c0, 1, 1, 0, 1 },
++ .bvalid_det_st = { 0x20c4, 1, 1, 0, 1 },
++ .bvalid_det_clr = { 0x20c8, 1, 1, 0, 1 },
++ .ls_det_en = { 0x20c0, 0, 0, 0, 1 },
++ .ls_det_st = { 0x20c4, 0, 0, 0, 1 },
++ .ls_det_clr = { 0x20c8, 0, 0, 0, 1 },
++ .disfall_en = { 0x20c0, 6, 6, 0, 1 },
++ .disfall_st = { 0x20c4, 6, 6, 0, 1 },
++ .disfall_clr = { 0x20c8, 6, 6, 0, 1 },
++ .disrise_en = { 0x20c0, 5, 5, 0, 1 },
++ .disrise_st = { 0x20c4, 5, 5, 0, 1 },
++ .disrise_clr = { 0x20c8, 5, 5, 0, 1 },
++ .utmi_avalid = { 0x2080, 1, 1, 0, 1 },
++ .utmi_bvalid = { 0x2080, 0, 0, 0, 1 },
++ .utmi_ls = { 0x2080, 5, 4, 0, 1 },
++ }
++ },
++ .chg_det = {
++ .cp_det = { 0x2080, 8, 8, 0, 1 },
++ .dcp_det = { 0x2080, 8, 8, 0, 1 },
++ .dp_det = { 0x2080, 9, 9, 1, 0 },
++ .idm_sink_en = { 0x2010, 5, 5, 1, 0 },
++ .idp_sink_en = { 0x2010, 5, 5, 0, 1 },
++ .idp_src_en = { 0x2010, 14, 14, 0, 1 },
++ .rdm_pdwn_en = { 0x2010, 14, 14, 0, 1 },
++ .vdm_src_en = { 0x2010, 7, 6, 0, 3 },
++ .vdp_src_en = { 0x2010, 7, 6, 0, 3 },
++ },
++ },
++ { /* sentinel */ }
++};
++
+ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
+ {
+ .reg = 0x0000,
+@@ -2120,6 +2222,7 @@ static const struct of_device_id rockchi
+ { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
+ { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
+ { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
++ { .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs },
+ { .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
+ { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
+ {}
--- /dev/null
+From a76de028c619dd18f89786805bcc7bb4d379ea9f Mon Sep 17 00:00:00 2001
+From: Frank Wang <frank.wang@rock-chips.com>
+Date: Mon, 14 Oct 2024 10:03:42 +0800
+Subject: [PATCH] phy: rockchip: usbdp: add rk3576 device match data
+
+This adds RK3576 device match data support.
+
+Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
+Acked-by: Dragan Simic <dsimic@manjaro.org>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20241014020342.15974-2-frawang.cn@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-usbdp.c | 41 +++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
++++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
+@@ -1556,6 +1556,43 @@ static const char * const rk_udphy_rst_l
+ "init", "cmn", "lane", "pcs_apb", "pma_apb"
+ };
+
++static const struct rk_udphy_cfg rk3576_udphy_cfgs = {
++ .num_phys = 1,
++ .phy_ids = { 0x2b010000 },
++ .num_rsts = ARRAY_SIZE(rk_udphy_rst_list),
++ .rst_list = rk_udphy_rst_list,
++ .grfcfg = {
++ /* u2phy-grf */
++ .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0010, 1, 0, 0x2, 0x3),
++ .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0000, 15, 14, 0x1, 0x3),
++
++ /* usb-grf */
++ .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x0030, 15, 0, 0x1100, 0x0188),
++
++ /* usbdpphy-grf */
++ .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1),
++ .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1),
++ },
++ .vogrfcfg = {
++ {
++ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
++ .dp_lane_reg = 0x0000,
++ },
++ },
++ .dp_tx_ctrl_cfg = {
++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
++ rk3588_dp_tx_drv_ctrl_hbr2,
++ rk3588_dp_tx_drv_ctrl_hbr3,
++ },
++ .dp_tx_ctrl_cfg_typec = {
++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
++ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
++ rk3588_dp_tx_drv_ctrl_hbr2,
++ rk3588_dp_tx_drv_ctrl_hbr3,
++ },
++};
++
+ static const struct rk_udphy_cfg rk3588_udphy_cfgs = {
+ .num_phys = 2,
+ .phy_ids = {
+@@ -1603,6 +1640,10 @@ static const struct rk_udphy_cfg rk3588_
+
+ static const struct of_device_id rk_udphy_dt_match[] = {
+ {
++ .compatible = "rockchip,rk3576-usbdp-phy",
++ .data = &rk3576_udphy_cfgs
++ },
++ {
+ .compatible = "rockchip,rk3588-usbdp-phy",
+ .data = &rk3588_udphy_cfgs
+ },
--- /dev/null
+From ba8ad7eece66ac5c579dd8de39efc72770e7cf64 Mon Sep 17 00:00:00 2001
+From: Kever Yang <kever.yang@rock-chips.com>
+Date: Wed, 6 Nov 2024 10:13:57 +0800
+Subject: [PATCH] phy: rockchip-naneng-combo: add rk3576 support
+
+Rockchip RK3576 integrates two naneng-combo PHY, PHY0 is used for
+PCIE and SATA, PHY1 is used for PCIE, SATA and USB3.
+
+This adds device specific data support.
+
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+Signed-off-by: William Wu <william.wu@rock-chips.com>
+Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Test-by: Kever Yang <kever.yang@rock-chips.com>
+Link: https://lore.kernel.org/r/20241106021357.19782-2-frawang.cn@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ .../rockchip/phy-rockchip-naneng-combphy.c | 279 ++++++++++++++++++
+ 1 file changed, 279 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+@@ -37,6 +37,10 @@
+ #define PHYREG8 0x1C
+ #define PHYREG8_SSC_EN BIT(4)
+
++#define PHYREG10 0x24
++#define PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
++#define PHYREG10_SSC_PCM_3500PPM 7
++
+ #define PHYREG11 0x28
+ #define PHYREG11_SU_TRIM_0_7 0xF0
+
+@@ -61,17 +65,26 @@
+ #define PHYREG16 0x3C
+ #define PHYREG16_SSC_CNT_VALUE 0x5f
+
++#define PHYREG17 0x40
++
+ #define PHYREG18 0x44
+ #define PHYREG18_PLL_LOOP 0x32
+
++#define PHYREG21 0x50
++#define PHYREG21_RX_SQUELCH_VAL 0x0D
++
+ #define PHYREG27 0x6C
+ #define PHYREG27_RX_TRIM_RK3588 0x4C
+
++#define PHYREG30 0x74
++
+ #define PHYREG32 0x7C
+ #define PHYREG32_SSC_MASK GENMASK(7, 4)
++#define PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
+ #define PHYREG32_SSC_DIR_SHIFT 4
+ #define PHYREG32_SSC_UPWARD 0
+ #define PHYREG32_SSC_DOWNWARD 1
++#define PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6)
+ #define PHYREG32_SSC_OFFSET_SHIFT 6
+ #define PHYREG32_SSC_OFFSET_500PPM 1
+
+@@ -79,6 +92,7 @@
+ #define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
+ #define PHYREG33_PLL_KVCO_SHIFT 2
+ #define PHYREG33_PLL_KVCO_VALUE 2
++#define PHYREG33_PLL_KVCO_VALUE_RK3576 4
+
+ struct rockchip_combphy_priv;
+
+@@ -98,6 +112,7 @@ struct rockchip_combphy_grfcfg {
+ struct combphy_reg pipe_rxterm_set;
+ struct combphy_reg pipe_txelec_set;
+ struct combphy_reg pipe_txcomp_set;
++ struct combphy_reg pipe_clk_24m;
+ struct combphy_reg pipe_clk_25m;
+ struct combphy_reg pipe_clk_100m;
+ struct combphy_reg pipe_phymode_sel;
+@@ -599,6 +614,266 @@ static const struct rockchip_combphy_cfg
+ .combphy_cfg = rk3568_combphy_cfg,
+ };
+
++static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
++{
++ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
++ unsigned long rate;
++ u32 val;
++
++ switch (priv->type) {
++ case PHY_TYPE_PCIE:
++ /* Set SSC downward spread spectrum */
++ val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD);
++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
++
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
++ break;
++
++ case PHY_TYPE_USB3:
++ /* Set SSC downward spread spectrum */
++ val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD);
++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
++
++ /* Enable adaptive CTLE for USB3.0 Rx */
++ val = readl(priv->mmio + PHYREG15);
++ val |= PHYREG15_CTLE_EN;
++ writel(val, priv->mmio + PHYREG15);
++
++ /* Set PLL KVCO fine tuning signals */
++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33);
++
++ /* Set PLL LPF R1 to su_trim[10:7]=1001 */
++ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
++
++ /* Set PLL input clock divider 1/2 */
++ val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2);
++ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6);
++
++ /* Set PLL loop divider */
++ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
++
++ /* Set PLL KVCO to min and set PLL charge pump current to max */
++ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
++
++ /* Set Rx squelch input filler bandwidth */
++ writel(PHYREG21_RX_SQUELCH_VAL, priv->mmio + PHYREG21);
++
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
++ break;
++
++ case PHY_TYPE_SATA:
++ /* Enable adaptive CTLE for SATA Rx */
++ val = readl(priv->mmio + PHYREG15);
++ val |= PHYREG15_CTLE_EN;
++ writel(val, priv->mmio + PHYREG15);
++
++ /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
++ val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
++ val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
++ writel(val, priv->mmio + PHYREG7);
++
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
++ break;
++
++ default:
++ dev_err(priv->dev, "incompatible PHY type\n");
++ return -EINVAL;
++ }
++
++ rate = clk_get_rate(priv->refclk);
++
++ switch (rate) {
++ case REF_CLOCK_24MHz:
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
++ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
++ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
++ val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE);
++ rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
++ val, PHYREG15);
++
++ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
++ } else if (priv->type == PHY_TYPE_PCIE) {
++ /* PLL KVCO tuning fine */
++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
++ val, PHYREG33);
++
++ /* Set up rx_pck invert and rx msb to disable */
++ writel(0x00, priv->mmio + PHYREG27);
++
++ /*
++ * Set up SU adjust signal:
++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
++ * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b011
++ * su_trim[31:24], CKDRV adjust
++ */
++ writel(0x90, priv->mmio + PHYREG11);
++ writel(0x02, priv->mmio + PHYREG12);
++ writel(0x57, priv->mmio + PHYREG14);
++
++ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
++ }
++ break;
++
++ case REF_CLOCK_25MHz:
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
++ break;
++
++ case REF_CLOCK_100MHz:
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
++ if (priv->type == PHY_TYPE_PCIE) {
++ /* gate_tx_pck_sel length select work for L1SS */
++ writel(0xc0, priv->mmio + PHYREG30);
++
++ /* PLL KVCO tuning fine */
++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
++ val, PHYREG33);
++
++ /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
++ writel(0x4c, priv->mmio + PHYREG27);
++
++ /*
++ * Set up SU adjust signal:
++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
++ * su_trim[15:8], bypass PLL loop divider code, and
++ * PLL LPF R1 adujst bits[9:7]=3'b101
++ * su_trim[23:16], CKRCV adjust
++ * su_trim[31:24], CKDRV adjust
++ */
++ writel(0x90, priv->mmio + PHYREG11);
++ writel(0x43, priv->mmio + PHYREG12);
++ writel(0x88, priv->mmio + PHYREG13);
++ writel(0x56, priv->mmio + PHYREG14);
++ } else if (priv->type == PHY_TYPE_SATA) {
++ /* downward spread spectrum +500ppm */
++ val = FIELD_PREP(PHYREG32_SSC_DIR_MASK, PHYREG32_SSC_DOWNWARD);
++ val |= FIELD_PREP(PHYREG32_SSC_OFFSET_MASK, PHYREG32_SSC_OFFSET_500PPM);
++ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
++
++ /* ssc ppm adjust to 3500ppm */
++ rockchip_combphy_updatel(priv, PHYREG10_SSC_PCM_MASK,
++ PHYREG10_SSC_PCM_3500PPM,
++ PHYREG10);
++ }
++ break;
++
++ default:
++ dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
++ return -EINVAL;
++ }
++
++ if (priv->ext_refclk) {
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
++ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
++ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
++ val, PHYREG33);
++
++ /* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */
++ writel(0x0c, priv->mmio + PHYREG27);
++
++ /*
++ * Set up SU adjust signal:
++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
++ * su_trim[15:8], bypass PLL loop divider code, and
++ * PLL LPF R1 adujst bits[9:7]=3'b101.
++ * su_trim[23:16], CKRCV adjust
++ * su_trim[31:24], CKDRV adjust
++ */
++ writel(0x90, priv->mmio + PHYREG11);
++ writel(0x43, priv->mmio + PHYREG12);
++ writel(0x88, priv->mmio + PHYREG13);
++ writel(0x56, priv->mmio + PHYREG14);
++ }
++ }
++
++ if (priv->enable_ssc) {
++ val = readl(priv->mmio + PHYREG8);
++ val |= PHYREG8_SSC_EN;
++ writel(val, priv->mmio + PHYREG8);
++
++ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
++ /* Set PLL loop divider */
++ writel(0x00, priv->mmio + PHYREG17);
++ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
++
++ /* Set up rx_pck invert and rx msb to disable */
++ writel(0x00, priv->mmio + PHYREG27);
++
++ /*
++ * Set up SU adjust signal:
++ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
++ * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101
++ * su_trim[23:16], CKRCV adjust
++ * su_trim[31:24], CKDRV adjust
++ */
++ writel(0x90, priv->mmio + PHYREG11);
++ writel(0x02, priv->mmio + PHYREG12);
++ writel(0x08, priv->mmio + PHYREG13);
++ writel(0x57, priv->mmio + PHYREG14);
++ writel(0x40, priv->mmio + PHYREG15);
++
++ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
++
++ val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
++ writel(val, priv->mmio + PHYREG33);
++ }
++ }
++
++ return 0;
++}
++
++static const struct rockchip_combphy_grfcfg rk3576_combphy_grfcfgs = {
++ /* pipe-phy-grf */
++ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
++ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
++ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
++ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
++ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
++ .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
++ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
++ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
++ .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
++ .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
++ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
++ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
++ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
++ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
++ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
++ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
++ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
++ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
++ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
++ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
++ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
++ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
++ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
++ /* php-grf */
++ .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 },
++ .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 },
++};
++
++static const struct rockchip_combphy_cfg rk3576_combphy_cfgs = {
++ .num_phys = 2,
++ .phy_ids = {
++ 0x2b050000,
++ 0x2b060000
++ },
++ .grfcfg = &rk3576_combphy_grfcfgs,
++ .combphy_cfg = rk3576_combphy_cfg,
++};
++
+ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
+ {
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+@@ -791,6 +1066,10 @@ static const struct of_device_id rockchi
+ .data = &rk3568_combphy_cfgs,
+ },
+ {
++ .compatible = "rockchip,rk3576-naneng-combphy",
++ .data = &rk3576_combphy_cfgs,
++ },
++ {
+ .compatible = "rockchip,rk3588-naneng-combphy",
+ .data = &rk3588_combphy_cfgs,
+ },
--- /dev/null
+From c3fe7071e196e25789ecf90dbc9e8491a98884d7 Mon Sep 17 00:00:00 2001
+From: Valmantas Paliksa <walmis@gmail.com>
+Date: Mon, 30 Jun 2025 19:25:14 -0300
+Subject: [PATCH] phy: rockchip-pcie: Enable all four lanes if required
+
+Current code enables only Lane 0 because pwr_cnt will be incremented on
+first call to the function. Let's reorder the enablement code to enable
+all 4 lanes through GRF.
+
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Reviewed-by: Robin Murphy <robin.murphy@arm.com>
+
+Signed-off-by: Valmantas Paliksa <walmis@gmail.com>
+Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
+Reviewed-by: Robin Murphy <robin.murphy@arm.com>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://lore.kernel.org/r/16b610aab34e069fd31d9f57260c10df2a968f80.1751322015.git.geraldogabriel@gmail.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-pcie.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-pcie.c
++++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
+@@ -165,6 +165,12 @@ static int rockchip_pcie_phy_power_on(st
+
+ mutex_lock(&rk_phy->pcie_mutex);
+
++ regmap_write(rk_phy->reg_base,
++ rk_phy->phy_data->pcie_laneoff,
++ HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
++ PHY_LANE_IDLE_MASK,
++ PHY_LANE_IDLE_A_SHIFT + inst->index));
++
+ if (rk_phy->pwr_cnt++)
+ goto err_out;
+
+@@ -179,12 +185,6 @@ static int rockchip_pcie_phy_power_on(st
+ PHY_CFG_ADDR_MASK,
+ PHY_CFG_ADDR_SHIFT));
+
+- regmap_write(rk_phy->reg_base,
+- rk_phy->phy_data->pcie_laneoff,
+- HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
+- PHY_LANE_IDLE_MASK,
+- PHY_LANE_IDLE_A_SHIFT + inst->index));
+-
+ /*
+ * No documented timeout value for phy operation below,
+ * so we make it large enough here. And we use loop-break
--- /dev/null
+From 11f1896e60f61ca1948cb7920585a79ce5254c0c Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Mon, 28 Jul 2025 10:29:46 +0000
+Subject: [PATCH] phy: rockchip: naneng-combphy: Add SoC prefix to register
+ definitions
+
+All supported variants of naneng-combphy follow a register layout
+similar to the RK3568 variant with some exceptions of SoC-specific
+registers.
+
+Add RK3568 prefix for the common set of registers and the corresponding
+SoC prefix for SoC-specific registers, making usage of definitions clear
+and preparing for future COMBPHY variants with a different register
+layout.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://lore.kernel.org/r/20250728102947.38984-6-ziyao@disroot.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ .../rockchip/phy-rockchip-naneng-combphy.c | 560 +++++++++---------
+ 1 file changed, 288 insertions(+), 272 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+@@ -21,78 +21,80 @@
+ #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
+
+ /* COMBO PHY REG */
+-#define PHYREG6 0x14
+-#define PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
+-#define PHYREG6_PLL_DIV_SHIFT 6
+-#define PHYREG6_PLL_DIV_2 1
+-
+-#define PHYREG7 0x18
+-#define PHYREG7_TX_RTERM_MASK GENMASK(7, 4)
+-#define PHYREG7_TX_RTERM_SHIFT 4
+-#define PHYREG7_TX_RTERM_50OHM 8
+-#define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
+-#define PHYREG7_RX_RTERM_SHIFT 0
+-#define PHYREG7_RX_RTERM_44OHM 15
+-
+-#define PHYREG8 0x1C
+-#define PHYREG8_SSC_EN BIT(4)
+-
+-#define PHYREG10 0x24
+-#define PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
+-#define PHYREG10_SSC_PCM_3500PPM 7
+-
+-#define PHYREG11 0x28
+-#define PHYREG11_SU_TRIM_0_7 0xF0
+-
+-#define PHYREG12 0x2C
+-#define PHYREG12_PLL_LPF_ADJ_VALUE 4
+-
+-#define PHYREG13 0x30
+-#define PHYREG13_RESISTER_MASK GENMASK(5, 4)
+-#define PHYREG13_RESISTER_SHIFT 0x4
+-#define PHYREG13_RESISTER_HIGH_Z 3
+-#define PHYREG13_CKRCV_AMP0 BIT(7)
+-
+-#define PHYREG14 0x34
+-#define PHYREG14_CKRCV_AMP1 BIT(0)
+-
+-#define PHYREG15 0x38
+-#define PHYREG15_CTLE_EN BIT(0)
+-#define PHYREG15_SSC_CNT_MASK GENMASK(7, 6)
+-#define PHYREG15_SSC_CNT_SHIFT 6
+-#define PHYREG15_SSC_CNT_VALUE 1
+-
+-#define PHYREG16 0x3C
+-#define PHYREG16_SSC_CNT_VALUE 0x5f
+-
+-#define PHYREG17 0x40
+-
+-#define PHYREG18 0x44
+-#define PHYREG18_PLL_LOOP 0x32
+-
+-#define PHYREG21 0x50
+-#define PHYREG21_RX_SQUELCH_VAL 0x0D
+-
+-#define PHYREG27 0x6C
+-#define PHYREG27_RX_TRIM_RK3588 0x4C
+-
+-#define PHYREG30 0x74
+-
+-#define PHYREG32 0x7C
+-#define PHYREG32_SSC_MASK GENMASK(7, 4)
+-#define PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
+-#define PHYREG32_SSC_DIR_SHIFT 4
+-#define PHYREG32_SSC_UPWARD 0
+-#define PHYREG32_SSC_DOWNWARD 1
+-#define PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6)
+-#define PHYREG32_SSC_OFFSET_SHIFT 6
+-#define PHYREG32_SSC_OFFSET_500PPM 1
+-
+-#define PHYREG33 0x80
+-#define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
+-#define PHYREG33_PLL_KVCO_SHIFT 2
+-#define PHYREG33_PLL_KVCO_VALUE 2
+-#define PHYREG33_PLL_KVCO_VALUE_RK3576 4
++#define RK3568_PHYREG6 0x14
++#define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
++#define RK3568_PHYREG6_PLL_DIV_SHIFT 6
++#define RK3568_PHYREG6_PLL_DIV_2 1
++
++#define RK3568_PHYREG7 0x18
++#define RK3568_PHYREG7_TX_RTERM_MASK GENMASK(7, 4)
++#define RK3568_PHYREG7_TX_RTERM_SHIFT 4
++#define RK3568_PHYREG7_TX_RTERM_50OHM 8
++#define RK3568_PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
++#define RK3568_PHYREG7_RX_RTERM_SHIFT 0
++#define RK3568_PHYREG7_RX_RTERM_44OHM 15
++
++#define RK3568_PHYREG8 0x1C
++#define RK3568_PHYREG8_SSC_EN BIT(4)
++
++#define RK3568_PHYREG11 0x28
++#define RK3568_PHYREG11_SU_TRIM_0_7 0xF0
++
++#define RK3568_PHYREG12 0x2C
++#define RK3568_PHYREG12_PLL_LPF_ADJ_VALUE 4
++
++#define RK3568_PHYREG13 0x30
++#define RK3568_PHYREG13_RESISTER_MASK GENMASK(5, 4)
++#define RK3568_PHYREG13_RESISTER_SHIFT 0x4
++#define RK3568_PHYREG13_RESISTER_HIGH_Z 3
++#define RK3568_PHYREG13_CKRCV_AMP0 BIT(7)
++
++#define RK3568_PHYREG14 0x34
++#define RK3568_PHYREG14_CKRCV_AMP1 BIT(0)
++
++#define RK3568_PHYREG15 0x38
++#define RK3568_PHYREG15_CTLE_EN BIT(0)
++#define RK3568_PHYREG15_SSC_CNT_MASK GENMASK(7, 6)
++#define RK3568_PHYREG15_SSC_CNT_SHIFT 6
++#define RK3568_PHYREG15_SSC_CNT_VALUE 1
++
++#define RK3568_PHYREG16 0x3C
++#define RK3568_PHYREG16_SSC_CNT_VALUE 0x5f
++
++#define RK3568_PHYREG18 0x44
++#define RK3568_PHYREG18_PLL_LOOP 0x32
++
++#define RK3568_PHYREG32 0x7C
++#define RK3568_PHYREG32_SSC_MASK GENMASK(7, 4)
++#define RK3568_PHYREG32_SSC_DIR_MASK GENMASK(5, 4)
++#define RK3568_PHYREG32_SSC_DIR_SHIFT 4
++#define RK3568_PHYREG32_SSC_UPWARD 0
++#define RK3568_PHYREG32_SSC_DOWNWARD 1
++#define RK3568_PHYREG32_SSC_OFFSET_MASK GENMASK(7, 6)
++#define RK3568_PHYREG32_SSC_OFFSET_SHIFT 6
++#define RK3568_PHYREG32_SSC_OFFSET_500PPM 1
++
++#define RK3568_PHYREG33 0x80
++#define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
++#define RK3568_PHYREG33_PLL_KVCO_SHIFT 2
++#define RK3568_PHYREG33_PLL_KVCO_VALUE 2
++#define RK3576_PHYREG33_PLL_KVCO_VALUE 4
++
++/* RK3588 COMBO PHY registers */
++#define RK3588_PHYREG27 0x6C
++#define RK3588_PHYREG27_RX_TRIM 0x4C
++
++/* RK3576 COMBO PHY registers */
++#define RK3576_PHYREG10 0x24
++#define RK3576_PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
++#define RK3576_PHYREG10_SSC_PCM_3500PPM 7
++
++#define RK3576_PHYREG17 0x40
++
++#define RK3576_PHYREG21 0x50
++#define RK3576_PHYREG21_RX_SQUELCH_VAL 0x0D
++
++#define RK3576_PHYREG30 0x74
+
+ struct rockchip_combphy_priv;
+
+@@ -407,9 +409,9 @@ static int rk3568_combphy_cfg(struct roc
+ switch (priv->type) {
+ case PHY_TYPE_PCIE:
+ /* Set SSC downward spread spectrum. */
+- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
+- PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
+- PHYREG32);
++ val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
++
++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+@@ -419,30 +421,28 @@ static int rk3568_combphy_cfg(struct roc
+
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum. */
+- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
+- PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
+- PHYREG32);
++ val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT,
++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
+
+ /* Enable adaptive CTLE for USB3.0 Rx. */
+- val = readl(priv->mmio + PHYREG15);
+- val |= PHYREG15_CTLE_EN;
+- writel(val, priv->mmio + PHYREG15);
++ val = readl(priv->mmio + RK3568_PHYREG15);
++ val |= RK3568_PHYREG15_CTLE_EN;
++ writel(val, priv->mmio + RK3568_PHYREG15);
+
+ /* Set PLL KVCO fine tuning signals. */
+- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+- PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
+- PHYREG33);
++ val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT;
++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
+
+ /* Enable controlling random jitter. */
+- writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
++ writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
+
+ /* Set PLL input clock divider 1/2. */
+- rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
+- PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
+- PHYREG6);
++ rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
++ RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT,
++ RK3568_PHYREG6);
+
+- writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+- writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
++ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
++ writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+@@ -460,16 +460,16 @@ static int rk3568_combphy_cfg(struct roc
+
+ case PHY_TYPE_SATA:
+ /* Enable adaptive CTLE for SATA Rx. */
+- val = readl(priv->mmio + PHYREG15);
+- val |= PHYREG15_CTLE_EN;
+- writel(val, priv->mmio + PHYREG15);
++ val = readl(priv->mmio + RK3568_PHYREG15);
++ val |= RK3568_PHYREG15_CTLE_EN;
++ writel(val, priv->mmio + RK3568_PHYREG15);
+ /*
+ * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
+ * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
+ */
+- val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
+- val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
+- writel(val, priv->mmio + PHYREG7);
++ val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
++ val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
++ writel(val, priv->mmio + RK3568_PHYREG7);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
+@@ -504,11 +504,11 @@ static int rk3568_combphy_cfg(struct roc
+ case REF_CLOCK_24MHz:
+ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
+ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
+- val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
+- rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
+- val, PHYREG15);
++ val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT;
++ rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
++ val, RK3568_PHYREG15);
+
+- writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
++ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
+ }
+ break;
+
+@@ -520,24 +520,26 @@ static int rk3568_combphy_cfg(struct roc
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->type == PHY_TYPE_PCIE) {
+ /* PLL KVCO fine tuning. */
+- val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
+- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+- val, PHYREG33);
++ val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT;
++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
++ val, RK3568_PHYREG33);
+
+ /* Enable controlling random jitter. */
+- writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
++ writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
+
+- val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
+- rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
+- val, PHYREG6);
++ val = RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT;
++ rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
++ val, RK3568_PHYREG6);
+
+- writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+- writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
++ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
++ writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
+ } else if (priv->type == PHY_TYPE_SATA) {
+ /* downward spread spectrum +500ppm */
+- val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
+- val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
+- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
++ val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
++ val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
++ RK3568_PHYREG32_SSC_OFFSET_SHIFT;
++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
++ RK3568_PHYREG32);
+ }
+ break;
+
+@@ -549,20 +551,21 @@ static int rk3568_combphy_cfg(struct roc
+ if (priv->ext_refclk) {
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
+ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
+- val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
+- val |= PHYREG13_CKRCV_AMP0;
+- rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
+-
+- val = readl(priv->mmio + PHYREG14);
+- val |= PHYREG14_CKRCV_AMP1;
+- writel(val, priv->mmio + PHYREG14);
++ val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
++ val |= RK3568_PHYREG13_CKRCV_AMP0;
++ rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
++ RK3568_PHYREG13);
++
++ val = readl(priv->mmio + RK3568_PHYREG14);
++ val |= RK3568_PHYREG14_CKRCV_AMP1;
++ writel(val, priv->mmio + RK3568_PHYREG14);
+ }
+ }
+
+ if (priv->enable_ssc) {
+- val = readl(priv->mmio + PHYREG8);
+- val |= PHYREG8_SSC_EN;
+- writel(val, priv->mmio + PHYREG8);
++ val = readl(priv->mmio + RK3568_PHYREG8);
++ val |= RK3568_PHYREG8_SSC_EN;
++ writel(val, priv->mmio + RK3568_PHYREG8);
+ }
+
+ return 0;
+@@ -623,8 +626,8 @@ static int rk3576_combphy_cfg(struct roc
+ switch (priv->type) {
+ case PHY_TYPE_PCIE:
+ /* Set SSC downward spread spectrum */
+- val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD);
+- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
++ val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+@@ -634,32 +637,33 @@ static int rk3576_combphy_cfg(struct roc
+
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum */
+- val = FIELD_PREP(PHYREG32_SSC_MASK, PHYREG32_SSC_DOWNWARD);
+- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
++ val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
+
+ /* Enable adaptive CTLE for USB3.0 Rx */
+- val = readl(priv->mmio + PHYREG15);
+- val |= PHYREG15_CTLE_EN;
+- writel(val, priv->mmio + PHYREG15);
++ val = readl(priv->mmio + RK3568_PHYREG15);
++ val |= RK3568_PHYREG15_CTLE_EN;
++ writel(val, priv->mmio + RK3568_PHYREG15);
+
+ /* Set PLL KVCO fine tuning signals */
+- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, BIT(3), PHYREG33);
++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, BIT(3),
++ RK3568_PHYREG33);
+
+ /* Set PLL LPF R1 to su_trim[10:7]=1001 */
+- writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
++ writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
+
+ /* Set PLL input clock divider 1/2 */
+- val = FIELD_PREP(PHYREG6_PLL_DIV_MASK, PHYREG6_PLL_DIV_2);
+- rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, val, PHYREG6);
++ val = FIELD_PREP(RK3568_PHYREG6_PLL_DIV_MASK, RK3568_PHYREG6_PLL_DIV_2);
++ rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK, val, RK3568_PHYREG6);
+
+ /* Set PLL loop divider */
+- writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
++ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
+
+ /* Set PLL KVCO to min and set PLL charge pump current to max */
+- writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
++ writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
+
+ /* Set Rx squelch input filler bandwidth */
+- writel(PHYREG21_RX_SQUELCH_VAL, priv->mmio + PHYREG21);
++ writel(RK3576_PHYREG21_RX_SQUELCH_VAL, priv->mmio + RK3576_PHYREG21);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+@@ -668,14 +672,14 @@ static int rk3576_combphy_cfg(struct roc
+
+ case PHY_TYPE_SATA:
+ /* Enable adaptive CTLE for SATA Rx */
+- val = readl(priv->mmio + PHYREG15);
+- val |= PHYREG15_CTLE_EN;
+- writel(val, priv->mmio + PHYREG15);
++ val = readl(priv->mmio + RK3568_PHYREG15);
++ val |= RK3568_PHYREG15_CTLE_EN;
++ writel(val, priv->mmio + RK3568_PHYREG15);
+
+ /* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
+- val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
+- val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
+- writel(val, priv->mmio + PHYREG7);
++ val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
++ val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
++ writel(val, priv->mmio + RK3568_PHYREG7);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
+@@ -697,19 +701,21 @@ static int rk3576_combphy_cfg(struct roc
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
+ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
+ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
+- val = FIELD_PREP(PHYREG15_SSC_CNT_MASK, PHYREG15_SSC_CNT_VALUE);
+- rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
+- val, PHYREG15);
++ val = FIELD_PREP(RK3568_PHYREG15_SSC_CNT_MASK,
++ RK3568_PHYREG15_SSC_CNT_VALUE);
++ rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
++ val, RK3568_PHYREG15);
+
+- writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
++ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
+ } else if (priv->type == PHY_TYPE_PCIE) {
+ /* PLL KVCO tuning fine */
+- val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
+- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+- val, PHYREG33);
++ val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
++ RK3576_PHYREG33_PLL_KVCO_VALUE);
++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
++ val, RK3568_PHYREG33);
+
+ /* Set up rx_pck invert and rx msb to disable */
+- writel(0x00, priv->mmio + PHYREG27);
++ writel(0x00, priv->mmio + RK3588_PHYREG27);
+
+ /*
+ * Set up SU adjust signal:
+@@ -717,11 +723,11 @@ static int rk3576_combphy_cfg(struct roc
+ * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b011
+ * su_trim[31:24], CKDRV adjust
+ */
+- writel(0x90, priv->mmio + PHYREG11);
+- writel(0x02, priv->mmio + PHYREG12);
+- writel(0x57, priv->mmio + PHYREG14);
++ writel(0x90, priv->mmio + RK3568_PHYREG11);
++ writel(0x02, priv->mmio + RK3568_PHYREG12);
++ writel(0x57, priv->mmio + RK3568_PHYREG14);
+
+- writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
++ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
+ }
+ break;
+
+@@ -733,15 +739,16 @@ static int rk3576_combphy_cfg(struct roc
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->type == PHY_TYPE_PCIE) {
+ /* gate_tx_pck_sel length select work for L1SS */
+- writel(0xc0, priv->mmio + PHYREG30);
++ writel(0xc0, priv->mmio + RK3576_PHYREG30);
+
+ /* PLL KVCO tuning fine */
+- val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
+- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+- val, PHYREG33);
++ val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
++ RK3576_PHYREG33_PLL_KVCO_VALUE);
++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
++ val, RK3568_PHYREG33);
+
+ /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
+- writel(0x4c, priv->mmio + PHYREG27);
++ writel(0x4c, priv->mmio + RK3588_PHYREG27);
+
+ /*
+ * Set up SU adjust signal:
+@@ -751,20 +758,23 @@ static int rk3576_combphy_cfg(struct roc
+ * su_trim[23:16], CKRCV adjust
+ * su_trim[31:24], CKDRV adjust
+ */
+- writel(0x90, priv->mmio + PHYREG11);
+- writel(0x43, priv->mmio + PHYREG12);
+- writel(0x88, priv->mmio + PHYREG13);
+- writel(0x56, priv->mmio + PHYREG14);
++ writel(0x90, priv->mmio + RK3568_PHYREG11);
++ writel(0x43, priv->mmio + RK3568_PHYREG12);
++ writel(0x88, priv->mmio + RK3568_PHYREG13);
++ writel(0x56, priv->mmio + RK3568_PHYREG14);
+ } else if (priv->type == PHY_TYPE_SATA) {
+ /* downward spread spectrum +500ppm */
+- val = FIELD_PREP(PHYREG32_SSC_DIR_MASK, PHYREG32_SSC_DOWNWARD);
+- val |= FIELD_PREP(PHYREG32_SSC_OFFSET_MASK, PHYREG32_SSC_OFFSET_500PPM);
+- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
++ val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK,
++ RK3568_PHYREG32_SSC_DOWNWARD);
++ val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK,
++ RK3568_PHYREG32_SSC_OFFSET_500PPM);
++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
++ RK3568_PHYREG32);
+
+ /* ssc ppm adjust to 3500ppm */
+- rockchip_combphy_updatel(priv, PHYREG10_SSC_PCM_MASK,
+- PHYREG10_SSC_PCM_3500PPM,
+- PHYREG10);
++ rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK,
++ RK3576_PHYREG10_SSC_PCM_3500PPM,
++ RK3576_PHYREG10);
+ }
+ break;
+
+@@ -776,12 +786,13 @@ static int rk3576_combphy_cfg(struct roc
+ if (priv->ext_refclk) {
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
+ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
+- val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
+- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+- val, PHYREG33);
++ val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
++ RK3576_PHYREG33_PLL_KVCO_VALUE);
++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
++ val, RK3568_PHYREG33);
+
+ /* Set up rx_trim: PLL LPF C1 85pf R1 2.5kohm */
+- writel(0x0c, priv->mmio + PHYREG27);
++ writel(0x0c, priv->mmio + RK3588_PHYREG27);
+
+ /*
+ * Set up SU adjust signal:
+@@ -791,25 +802,25 @@ static int rk3576_combphy_cfg(struct roc
+ * su_trim[23:16], CKRCV adjust
+ * su_trim[31:24], CKDRV adjust
+ */
+- writel(0x90, priv->mmio + PHYREG11);
+- writel(0x43, priv->mmio + PHYREG12);
+- writel(0x88, priv->mmio + PHYREG13);
+- writel(0x56, priv->mmio + PHYREG14);
++ writel(0x90, priv->mmio + RK3568_PHYREG11);
++ writel(0x43, priv->mmio + RK3568_PHYREG12);
++ writel(0x88, priv->mmio + RK3568_PHYREG13);
++ writel(0x56, priv->mmio + RK3568_PHYREG14);
+ }
+ }
+
+ if (priv->enable_ssc) {
+- val = readl(priv->mmio + PHYREG8);
+- val |= PHYREG8_SSC_EN;
+- writel(val, priv->mmio + PHYREG8);
++ val = readl(priv->mmio + RK3568_PHYREG8);
++ val |= RK3568_PHYREG8_SSC_EN;
++ writel(val, priv->mmio + RK3568_PHYREG8);
+
+ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
+ /* Set PLL loop divider */
+- writel(0x00, priv->mmio + PHYREG17);
+- writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
++ writel(0x00, priv->mmio + RK3576_PHYREG17);
++ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
+
+ /* Set up rx_pck invert and rx msb to disable */
+- writel(0x00, priv->mmio + PHYREG27);
++ writel(0x00, priv->mmio + RK3588_PHYREG27);
+
+ /*
+ * Set up SU adjust signal:
+@@ -818,16 +829,17 @@ static int rk3576_combphy_cfg(struct roc
+ * su_trim[23:16], CKRCV adjust
+ * su_trim[31:24], CKDRV adjust
+ */
+- writel(0x90, priv->mmio + PHYREG11);
+- writel(0x02, priv->mmio + PHYREG12);
+- writel(0x08, priv->mmio + PHYREG13);
+- writel(0x57, priv->mmio + PHYREG14);
+- writel(0x40, priv->mmio + PHYREG15);
+-
+- writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
+-
+- val = FIELD_PREP(PHYREG33_PLL_KVCO_MASK, PHYREG33_PLL_KVCO_VALUE_RK3576);
+- writel(val, priv->mmio + PHYREG33);
++ writel(0x90, priv->mmio + RK3568_PHYREG11);
++ writel(0x02, priv->mmio + RK3568_PHYREG12);
++ writel(0x08, priv->mmio + RK3568_PHYREG13);
++ writel(0x57, priv->mmio + RK3568_PHYREG14);
++ writel(0x40, priv->mmio + RK3568_PHYREG15);
++
++ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
++
++ val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
++ RK3576_PHYREG33_PLL_KVCO_VALUE);
++ writel(val, priv->mmio + RK3568_PHYREG33);
+ }
+ }
+
+@@ -897,30 +909,28 @@ static int rk3588_combphy_cfg(struct roc
+ break;
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum */
+- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
+- PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
+- PHYREG32);
++ val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
+
+ /* Enable adaptive CTLE for USB3.0 Rx. */
+- val = readl(priv->mmio + PHYREG15);
+- val |= PHYREG15_CTLE_EN;
+- writel(val, priv->mmio + PHYREG15);
++ val = readl(priv->mmio + RK3568_PHYREG15);
++ val |= RK3568_PHYREG15_CTLE_EN;
++ writel(val, priv->mmio + RK3568_PHYREG15);
+
+ /* Set PLL KVCO fine tuning signals. */
+- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+- PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
+- PHYREG33);
++ val = RK3568_PHYREG33_PLL_KVCO_VALUE << RK3568_PHYREG33_PLL_KVCO_SHIFT,
++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK, val, RK3568_PHYREG33);
+
+ /* Enable controlling random jitter. */
+- writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
++ writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
+
+ /* Set PLL input clock divider 1/2. */
+- rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
+- PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
+- PHYREG6);
++ rockchip_combphy_updatel(priv, RK3568_PHYREG6_PLL_DIV_MASK,
++ RK3568_PHYREG6_PLL_DIV_2 << RK3568_PHYREG6_PLL_DIV_SHIFT,
++ RK3568_PHYREG6);
+
+- writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
+- writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
++ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
++ writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+@@ -928,16 +938,16 @@ static int rk3588_combphy_cfg(struct roc
+ break;
+ case PHY_TYPE_SATA:
+ /* Enable adaptive CTLE for SATA Rx. */
+- val = readl(priv->mmio + PHYREG15);
+- val |= PHYREG15_CTLE_EN;
+- writel(val, priv->mmio + PHYREG15);
++ val = readl(priv->mmio + RK3568_PHYREG15);
++ val |= RK3568_PHYREG15_CTLE_EN;
++ writel(val, priv->mmio + RK3568_PHYREG15);
+ /*
+ * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
+ * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
+ */
+- val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
+- val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
+- writel(val, priv->mmio + PHYREG7);
++ val = RK3568_PHYREG7_TX_RTERM_50OHM << RK3568_PHYREG7_TX_RTERM_SHIFT;
++ val |= RK3568_PHYREG7_RX_RTERM_44OHM << RK3568_PHYREG7_RX_RTERM_SHIFT;
++ writel(val, priv->mmio + RK3568_PHYREG7);
+
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
+@@ -959,11 +969,11 @@ static int rk3588_combphy_cfg(struct roc
+ case REF_CLOCK_24MHz:
+ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
+ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
+- val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
+- rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
+- val, PHYREG15);
++ val = RK3568_PHYREG15_SSC_CNT_VALUE << RK3568_PHYREG15_SSC_CNT_SHIFT;
++ rockchip_combphy_updatel(priv, RK3568_PHYREG15_SSC_CNT_MASK,
++ val, RK3568_PHYREG15);
+
+- writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
++ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
+ }
+ break;
+
+@@ -974,23 +984,25 @@ static int rk3588_combphy_cfg(struct roc
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->type == PHY_TYPE_PCIE) {
+ /* PLL KVCO fine tuning. */
+- val = 4 << PHYREG33_PLL_KVCO_SHIFT;
+- rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
+- val, PHYREG33);
++ val = 4 << RK3568_PHYREG33_PLL_KVCO_SHIFT;
++ rockchip_combphy_updatel(priv, RK3568_PHYREG33_PLL_KVCO_MASK,
++ val, RK3568_PHYREG33);
+
+ /* Enable controlling random jitter. */
+- writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
++ writel(RK3568_PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + RK3568_PHYREG12);
+
+ /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
+- writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27);
++ writel(RK3588_PHYREG27_RX_TRIM, priv->mmio + RK3588_PHYREG27);
+
+ /* Set up su_trim: */
+- writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
++ writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
+ } else if (priv->type == PHY_TYPE_SATA) {
+ /* downward spread spectrum +500ppm */
+- val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
+- val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
+- rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
++ val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
++ val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
++ RK3568_PHYREG32_SSC_OFFSET_SHIFT;
++ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
++ RK3568_PHYREG32);
+ }
+ break;
+ default:
+@@ -1001,20 +1013,21 @@ static int rk3588_combphy_cfg(struct roc
+ if (priv->ext_refclk) {
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
+ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
+- val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
+- val |= PHYREG13_CKRCV_AMP0;
+- rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
+-
+- val = readl(priv->mmio + PHYREG14);
+- val |= PHYREG14_CKRCV_AMP1;
+- writel(val, priv->mmio + PHYREG14);
++ val = RK3568_PHYREG13_RESISTER_HIGH_Z << RK3568_PHYREG13_RESISTER_SHIFT;
++ val |= RK3568_PHYREG13_CKRCV_AMP0;
++ rockchip_combphy_updatel(priv, RK3568_PHYREG13_RESISTER_MASK, val,
++ RK3568_PHYREG13);
++
++ val = readl(priv->mmio + RK3568_PHYREG14);
++ val |= RK3568_PHYREG14_CKRCV_AMP1;
++ writel(val, priv->mmio + RK3568_PHYREG14);
+ }
+ }
+
+ if (priv->enable_ssc) {
+- val = readl(priv->mmio + PHYREG8);
+- val |= PHYREG8_SSC_EN;
+- writel(val, priv->mmio + PHYREG8);
++ val = readl(priv->mmio + RK3568_PHYREG8);
++ val |= RK3568_PHYREG8_SSC_EN;
++ writel(val, priv->mmio + RK3568_PHYREG8);
+ }
+
+ return 0;
--- /dev/null
+From aee07ee1b97d9a3825e8db609a1c76157218cc59 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Mon, 28 Jul 2025 10:29:47 +0000
+Subject: [PATCH] phy: rockchip: naneng-combphy: Add RK3528 support
+
+Rockchip RK3528 integrates one naneng-combphy that is able to operate in
+PCIe and USB3 mode. The control logic is similar to previous variants of
+naneng-combphy but the register layout is apparently different from the
+RK3568 one.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://lore.kernel.org/r/20250728102947.38984-7-ziyao@disroot.org
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ .../rockchip/phy-rockchip-naneng-combphy.c | 189 +++++++++++++++++-
+ 1 file changed, 188 insertions(+), 1 deletion(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+@@ -20,7 +20,46 @@
+ #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ)
+ #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
+
+-/* COMBO PHY REG */
++/* RK3528 COMBO PHY REG */
++#define RK3528_PHYREG6 0x18
++#define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)
++#define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
++#define RK3528_PHYREG6_SSC_DIR GENMASK(5, 4)
++#define RK3528_PHYREG6_SSC_UPWARD 0
++#define RK3528_PHYREG6_SSC_DOWNWARD 1
++
++#define RK3528_PHYREG40 0x100
++#define RK3528_PHYREG40_SSC_EN BIT(20)
++#define RK3528_PHYREG40_SSC_CNT GENMASK(10, 0)
++#define RK3528_PHYREG40_SSC_CNT_VALUE 0x17d
++
++#define RK3528_PHYREG42 0x108
++#define RK3528_PHYREG42_CKDRV_CLK_SEL BIT(29)
++#define RK3528_PHYREG42_CKDRV_CLK_PLL 0
++#define RK3528_PHYREG42_CKDRV_CLK_CKRCV 1
++#define RK3528_PHYREG42_PLL_LPF_R1_ADJ GENMASK(10, 7)
++#define RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE 0x9
++#define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ GENMASK(6, 4)
++#define RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE 0x7
++#define RK3528_PHYREG42_PLL_KVCO_ADJ GENMASK(2, 0)
++#define RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE 0x0
++
++#define RK3528_PHYREG80 0x200
++#define RK3528_PHYREG80_CTLE_EN BIT(17)
++
++#define RK3528_PHYREG81 0x204
++#define RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X BIT(5)
++#define RK3528_PHYREG81_SLEW_RATE_CTRL GENMASK(2, 0)
++#define RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW 0x7
++
++#define RK3528_PHYREG83 0x20c
++#define RK3528_PHYREG83_RX_SQUELCH GENMASK(2, 0)
++#define RK3528_PHYREG83_RX_SQUELCH_VALUE 0x6
++
++#define RK3528_PHYREG86 0x218
++#define RK3528_PHYREG86_RTERM_DET_CLK_EN BIT(14)
++
++/* RK3568 COMBO PHY REG */
+ #define RK3568_PHYREG6 0x14
+ #define RK3568_PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
+ #define RK3568_PHYREG6_PLL_DIV_SHIFT 6
+@@ -400,6 +439,150 @@ static int rockchip_combphy_probe(struct
+ return PTR_ERR_OR_ZERO(phy_provider);
+ }
+
++static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
++{
++ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
++ unsigned long rate;
++ u32 val;
++
++ /* Set SSC downward spread spectrum */
++ val = FIELD_PREP(RK3528_PHYREG6_SSC_DIR, RK3528_PHYREG6_SSC_DOWNWARD);
++ rockchip_combphy_updatel(priv, RK3528_PHYREG6_SSC_DIR, val, RK3528_PHYREG6);
++
++ switch (priv->type) {
++ case PHY_TYPE_PCIE:
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
++ break;
++ case PHY_TYPE_USB3:
++ /* Enable adaptive CTLE for USB3.0 Rx */
++ rockchip_combphy_updatel(priv, RK3528_PHYREG80_CTLE_EN, RK3528_PHYREG80_CTLE_EN,
++ RK3528_PHYREG80);
++
++ /* Set slow slew rate control for PI */
++ val = FIELD_PREP(RK3528_PHYREG81_SLEW_RATE_CTRL,
++ RK3528_PHYREG81_SLEW_RATE_CTRL_SLOW);
++ rockchip_combphy_updatel(priv, RK3528_PHYREG81_SLEW_RATE_CTRL, val,
++ RK3528_PHYREG81);
++
++ /* Set CDR phase path with 2x gain */
++ rockchip_combphy_updatel(priv, RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X,
++ RK3528_PHYREG81_CDR_PHASE_PATH_GAIN_2X, RK3528_PHYREG81);
++
++ /* Set Rx squelch input filler bandwidth */
++ val = FIELD_PREP(RK3528_PHYREG83_RX_SQUELCH, RK3528_PHYREG83_RX_SQUELCH_VALUE);
++ rockchip_combphy_updatel(priv, RK3528_PHYREG83_RX_SQUELCH, val, RK3528_PHYREG83);
++
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
++ rockchip_combphy_param_write(priv->pipe_grf, &cfg->u3otg0_port_en, true);
++ break;
++ default:
++ dev_err(priv->dev, "incompatible PHY type\n");
++ return -EINVAL;
++ }
++
++ rate = clk_get_rate(priv->refclk);
++
++ switch (rate) {
++ case REF_CLOCK_24MHz:
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
++ if (priv->type == PHY_TYPE_USB3) {
++ /* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */
++ val = FIELD_PREP(RK3528_PHYREG40_SSC_CNT, RK3528_PHYREG40_SSC_CNT_VALUE);
++ rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_CNT, val,
++ RK3528_PHYREG40);
++ } else if (priv->type == PHY_TYPE_PCIE) {
++ /* tx_trim[14]=1, Enable the counting clock of the rterm detect */
++ rockchip_combphy_updatel(priv, RK3528_PHYREG86_RTERM_DET_CLK_EN,
++ RK3528_PHYREG86_RTERM_DET_CLK_EN, RK3528_PHYREG86);
++ }
++ break;
++ case REF_CLOCK_100MHz:
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
++ if (priv->type == PHY_TYPE_PCIE) {
++ /* PLL KVCO tuning fine */
++ val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
++ rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
++ RK3528_PHYREG6);
++
++ /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */
++ writel(0x570804f0, priv->mmio + RK3528_PHYREG42);
++ }
++ break;
++ default:
++ dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
++ return -EINVAL;
++ }
++
++ if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
++ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
++
++ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
++ val = FIELD_PREP(RK3528_PHYREG42_CKDRV_CLK_SEL,
++ RK3528_PHYREG42_CKDRV_CLK_CKRCV);
++ val |= FIELD_PREP(RK3528_PHYREG42_PLL_LPF_R1_ADJ,
++ RK3528_PHYREG42_PLL_LPF_R1_ADJ_VALUE);
++ val |= FIELD_PREP(RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ,
++ RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ_VALUE);
++ val |= FIELD_PREP(RK3528_PHYREG42_PLL_KVCO_ADJ,
++ RK3528_PHYREG42_PLL_KVCO_ADJ_VALUE);
++ rockchip_combphy_updatel(priv,
++ RK3528_PHYREG42_CKDRV_CLK_SEL |
++ RK3528_PHYREG42_PLL_LPF_R1_ADJ |
++ RK3528_PHYREG42_PLL_CHGPUMP_CUR_ADJ |
++ RK3528_PHYREG42_PLL_KVCO_ADJ,
++ val, RK3528_PHYREG42);
++
++ val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
++ rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
++ RK3528_PHYREG6);
++ }
++ }
++
++ if (priv->type == PHY_TYPE_PCIE) {
++ if (device_property_read_bool(priv->dev, "rockchip,enable-ssc"))
++ rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
++ RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
++ }
++
++ return 0;
++}
++
++static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
++ /* pipe-phy-grf */
++ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
++ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
++ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
++ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
++ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
++ .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
++ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
++ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
++ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
++ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
++ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
++ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
++ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x110 },
++ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x00 },
++ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x101 },
++ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
++ /* pipe-grf */
++ .u3otg0_port_en = { 0x0044, 15, 0, 0x0181, 0x1100 },
++};
++
++static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
++ .num_phys = 1,
++ .phy_ids = {
++ 0xffdc0000,
++ },
++ .grfcfg = &rk3528_combphy_grfcfgs,
++ .combphy_cfg = rk3528_combphy_cfg,
++};
++
+ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
+ {
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+@@ -1075,6 +1258,10 @@ static const struct rockchip_combphy_cfg
+
+ static const struct of_device_id rockchip_combphy_of_match[] = {
+ {
++ .compatible = "rockchip,rk3528-naneng-combphy",
++ .data = &rk3528_combphy_cfgs,
++ },
++ {
+ .compatible = "rockchip,rk3568-naneng-combphy",
+ .data = &rk3568_combphy_cfgs,
+ },
--- /dev/null
+From a2a18e5da64f8da306fa97c397b4c739ea776f37 Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Tue, 18 Nov 2025 17:52:05 +0800
+Subject: [PATCH] phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528
+
+When PCIe link enters L1 PM substates, the PHY will turn off its
+PLL for power-saving. However, it turns off the PLL too fast which
+leads the PHY to be broken. According to the PHY document, we need
+to delay PLL turnoff time.
+
+Fixes: bbcca4fac873 ("phy: rockchip: naneng-combphy: Add RK3528 support")
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
+Link: https://patch.msgid.link/1763459526-35004-1-git-send-email-shawn.lin@rock-chips.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+@@ -21,6 +21,9 @@
+ #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
+
+ /* RK3528 COMBO PHY REG */
++#define RK3528_PHYREG5 0x14
++#define RK3528_PHYREG5_GATE_TX_PCK_SEL BIT(3)
++#define RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF BIT(3)
+ #define RK3528_PHYREG6 0x18
+ #define RK3528_PHYREG6_PLL_KVCO GENMASK(12, 10)
+ #define RK3528_PHYREG6_PLL_KVCO_VALUE 0x2
+@@ -504,6 +507,10 @@ static int rk3528_combphy_cfg(struct roc
+ case REF_CLOCK_100MHz:
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->type == PHY_TYPE_PCIE) {
++ /* Gate_tx_pck_sel length select for L1ss support */
++ rockchip_combphy_updatel(priv, RK3528_PHYREG5_GATE_TX_PCK_SEL,
++ RK3528_PHYREG5_GATE_TX_PCK_DLY_PLL_OFF, RK3528_PHYREG5);
++
+ /* PLL KVCO tuning fine */
+ val = FIELD_PREP(RK3528_PHYREG6_PLL_KVCO, RK3528_PHYREG6_PLL_KVCO_VALUE);
+ rockchip_combphy_updatel(priv, RK3528_PHYREG6_PLL_KVCO, val,
--- /dev/null
+From 6b070711b702638622f4b7072e36328a47356576 Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Wed, 5 Feb 2025 14:15:54 +0800
+Subject: [PATCH] scsi: ufs: core: Export ufshcd_dme_reset() and
+ ufshcd_dme_enable()
+
+These two APIs will be used by glue driver if they need a different HCE
+process.
+
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Link: https://lore.kernel.org/r/1738736156-119203-6-git-send-email-shawn.lin@rock-chips.com
+Reviewed-by: Bart Van Assche <bvanassche@acm.org>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+---
+ drivers/ufs/core/ufshcd.c | 6 ++++--
+ include/ufs/ufshcd.h | 2 ++
+ 2 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/drivers/ufs/core/ufshcd.c
++++ b/drivers/ufs/core/ufshcd.c
+@@ -4046,7 +4046,7 @@ static int ufshcd_dme_link_startup(struc
+ *
+ * Return: 0 on success, non-zero value on failure.
+ */
+-static int ufshcd_dme_reset(struct ufs_hba *hba)
++int ufshcd_dme_reset(struct ufs_hba *hba)
+ {
+ struct uic_command uic_cmd = {
+ .command = UIC_CMD_DME_RESET,
+@@ -4060,6 +4060,7 @@ static int ufshcd_dme_reset(struct ufs_h
+
+ return ret;
+ }
++EXPORT_SYMBOL_GPL(ufshcd_dme_reset);
+
+ int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
+ int agreed_gear,
+@@ -4085,7 +4086,7 @@ EXPORT_SYMBOL_GPL(ufshcd_dme_configure_a
+ *
+ * Return: 0 on success, non-zero value on failure.
+ */
+-static int ufshcd_dme_enable(struct ufs_hba *hba)
++int ufshcd_dme_enable(struct ufs_hba *hba)
+ {
+ struct uic_command uic_cmd = {
+ .command = UIC_CMD_DME_ENABLE,
+@@ -4099,6 +4100,7 @@ static int ufshcd_dme_enable(struct ufs_
+
+ return ret;
+ }
++EXPORT_SYMBOL_GPL(ufshcd_dme_enable);
+
+ static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba)
+ {
+--- a/include/ufs/ufshcd.h
++++ b/include/ufs/ufshcd.h
+@@ -1364,6 +1364,8 @@ extern int ufshcd_system_freeze(struct d
+ extern int ufshcd_system_thaw(struct device *dev);
+ extern int ufshcd_system_restore(struct device *dev);
+
++extern int ufshcd_dme_reset(struct ufs_hba *hba);
++extern int ufshcd_dme_enable(struct ufs_hba *hba);
+ extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
+ int agreed_gear,
+ int adapt_val);
--- /dev/null
+From d3cbe455d6eb600dee27bf5294f6fe8c2bb06b5f Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Wed, 5 Feb 2025 14:15:55 +0800
+Subject: [PATCH] scsi: ufs: rockchip: Initial support for UFS
+
+RK3576 SoC contains a UFS controller, add initial support for it.
+The features are:
+
+ 1. support UFS 2.0 features
+ 2. High speed up to HS-G3
+ 3. 2RX-2TX lanes
+ 4. auto H8 entry and exit
+
+Software limitation:
+
+ 1. HCE procedure: enable controller->enable intr->dme_reset->dme_enable
+ 2. disable unipro timeout values before power mode change
+
+[mkp: fix build errors]
+
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Link: https://lore.kernel.org/r/1738736156-119203-7-git-send-email-shawn.lin@rock-chips.com
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+---
+ drivers/ufs/host/Kconfig | 12 ++
+ drivers/ufs/host/Makefile | 1 +
+ drivers/ufs/host/ufs-rockchip.c | 354 ++++++++++++++++++++++++++++++++
+ drivers/ufs/host/ufs-rockchip.h | 90 ++++++++
+ 4 files changed, 457 insertions(+)
+ create mode 100644 drivers/ufs/host/ufs-rockchip.c
+ create mode 100644 drivers/ufs/host/ufs-rockchip.h
+
+--- a/drivers/ufs/host/Kconfig
++++ b/drivers/ufs/host/Kconfig
+@@ -143,3 +143,15 @@ config SCSI_UFS_SPRD
+
+ Select this if you have UFS controller on Unisoc chipset.
+ If unsure, say N.
++
++config SCSI_UFS_ROCKCHIP
++ tristate "Rockchip UFS host controller driver"
++ depends on SCSI_UFSHCD_PLATFORM && (ARCH_ROCKCHIP || COMPILE_TEST)
++ help
++ This selects the Rockchip specific additions to UFSHCD platform driver.
++ UFS host on Rockchip needs some vendor specific configuration before
++ accessing the hardware which includes PHY configuration and vendor
++ specific registers.
++
++ Select this if you have UFS controller on Rockchip chipset.
++ If unsure, say N.
+--- a/drivers/ufs/host/Makefile
++++ b/drivers/ufs/host/Makefile
+@@ -10,5 +10,6 @@ obj-$(CONFIG_SCSI_UFSHCD_PLATFORM) += uf
+ obj-$(CONFIG_SCSI_UFS_HISI) += ufs-hisi.o
+ obj-$(CONFIG_SCSI_UFS_MEDIATEK) += ufs-mediatek.o
+ obj-$(CONFIG_SCSI_UFS_RENESAS) += ufs-renesas.o
++obj-$(CONFIG_SCSI_UFS_ROCKCHIP) += ufs-rockchip.o
+ obj-$(CONFIG_SCSI_UFS_SPRD) += ufs-sprd.o
+ obj-$(CONFIG_SCSI_UFS_TI_J721E) += ti-j721e-ufs.o
+--- /dev/null
++++ b/drivers/ufs/host/ufs-rockchip.c
+@@ -0,0 +1,354 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Rockchip UFS Host Controller driver
++ *
++ * Copyright (C) 2025 Rockchip Electronics Co., Ltd.
++ */
++
++#include <linux/clk.h>
++#include <linux/gpio.h>
++#include <linux/mfd/syscon.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_domain.h>
++#include <linux/pm_wakeup.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++
++#include <ufs/ufshcd.h>
++#include <ufs/unipro.h>
++#include "ufshcd-pltfrm.h"
++#include "ufs-rockchip.h"
++
++static int ufs_rockchip_hce_enable_notify(struct ufs_hba *hba,
++ enum ufs_notify_change_status status)
++{
++ int err = 0;
++
++ if (status == POST_CHANGE) {
++ err = ufshcd_dme_reset(hba);
++ if (err)
++ return err;
++
++ err = ufshcd_dme_enable(hba);
++ if (err)
++ return err;
++
++ return ufshcd_vops_phy_initialization(hba);
++ }
++
++ return 0;
++}
++
++static void ufs_rockchip_set_pm_lvl(struct ufs_hba *hba)
++{
++ hba->rpm_lvl = UFS_PM_LVL_5;
++ hba->spm_lvl = UFS_PM_LVL_5;
++}
++
++static int ufs_rockchip_rk3576_phy_init(struct ufs_hba *hba)
++{
++ struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
++
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(PA_LOCAL_TX_LCC_ENABLE, 0x0), 0x0);
++ /* enable the mphy DME_SET cfg */
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_ENABLE);
++ for (int i = 0; i < 2; i++) {
++ /* Configuration M - TX */
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, SEL_TX_LANE0 + i), 0x06);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, SEL_TX_LANE0 + i), 0x02);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_VALUE, SEL_TX_LANE0 + i), 0x44);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, SEL_TX_LANE0 + i), 0xe6);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, SEL_TX_LANE0 + i), 0x07);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_TASE_VALUE, SEL_TX_LANE0 + i), 0x93);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_BASE_NVALUE, SEL_TX_LANE0 + i), 0xc9);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_POWER_SAVING_CTRL, SEL_TX_LANE0 + i), 0x00);
++ /* Configuration M - RX */
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, SEL_RX_LANE0 + i), 0x06);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, SEL_RX_LANE0 + i), 0x00);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE, SEL_RX_LANE0 + i), 0x58);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_PVALUE1, SEL_RX_LANE0 + i), 0x8c);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_PVALUE2, SEL_RX_LANE0 + i), 0x02);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_OPTION, SEL_RX_LANE0 + i), 0xf6);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_POWER_SAVING_CTRL, SEL_RX_LANE0 + i), 0x69);
++ }
++
++ /* disable the mphy DME_SET cfg */
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MPHY_CFG, 0x0), MPHY_CFG_DISABLE);
++
++ ufs_sys_writel(host->mphy_base, 0x80, CMN_REG23);
++ ufs_sys_writel(host->mphy_base, 0xB5, TRSV0_REG14);
++ ufs_sys_writel(host->mphy_base, 0xB5, TRSV1_REG14);
++
++ ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG15);
++ ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG15);
++
++ ufs_sys_writel(host->mphy_base, 0x38, TRSV0_REG08);
++ ufs_sys_writel(host->mphy_base, 0x38, TRSV1_REG08);
++
++ ufs_sys_writel(host->mphy_base, 0x50, TRSV0_REG29);
++ ufs_sys_writel(host->mphy_base, 0x50, TRSV1_REG29);
++
++ ufs_sys_writel(host->mphy_base, 0x80, TRSV0_REG2E);
++ ufs_sys_writel(host->mphy_base, 0x80, TRSV1_REG2E);
++
++ ufs_sys_writel(host->mphy_base, 0x18, TRSV0_REG3C);
++ ufs_sys_writel(host->mphy_base, 0x18, TRSV1_REG3C);
++
++ ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG16);
++ ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG16);
++
++ ufs_sys_writel(host->mphy_base, 0x20, TRSV0_REG17);
++ ufs_sys_writel(host->mphy_base, 0x20, TRSV1_REG17);
++
++ ufs_sys_writel(host->mphy_base, 0xC0, TRSV0_REG18);
++ ufs_sys_writel(host->mphy_base, 0xC0, TRSV1_REG18);
++
++ ufs_sys_writel(host->mphy_base, 0x03, CMN_REG25);
++
++ ufs_sys_writel(host->mphy_base, 0x03, TRSV0_REG3D);
++ ufs_sys_writel(host->mphy_base, 0x03, TRSV1_REG3D);
++
++ ufs_sys_writel(host->mphy_base, 0xC0, CMN_REG23);
++ udelay(1);
++ ufs_sys_writel(host->mphy_base, 0x00, CMN_REG23);
++
++ usleep_range(200, 250);
++ /* start link up */
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_TX_ENDIAN, 0), 0x0);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(MIB_T_DBG_CPORT_RX_ENDIAN, 0), 0x0);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID, 0), 0x0);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(N_DEVICEID_VALID, 0), 0x1);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_PEERDEVICEID, 0), 0x1);
++ ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(T_CONNECTIONSTATE, 0), 0x1);
++
++ return 0;
++}
++
++static int ufs_rockchip_common_init(struct ufs_hba *hba)
++{
++ struct device *dev = hba->dev;
++ struct platform_device *pdev = to_platform_device(dev);
++ struct ufs_rockchip_host *host;
++ int err;
++
++ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
++ if (!host)
++ return -ENOMEM;
++
++ host->ufs_sys_ctrl = devm_platform_ioremap_resource_byname(pdev, "hci_grf");
++ if (IS_ERR(host->ufs_sys_ctrl))
++ return dev_err_probe(dev, PTR_ERR(host->ufs_sys_ctrl),
++ "Failed to map HCI system control registers\n");
++
++ host->ufs_phy_ctrl = devm_platform_ioremap_resource_byname(pdev, "mphy_grf");
++ if (IS_ERR(host->ufs_phy_ctrl))
++ return dev_err_probe(dev, PTR_ERR(host->ufs_phy_ctrl),
++ "Failed to map mphy system control registers\n");
++
++ host->mphy_base = devm_platform_ioremap_resource_byname(pdev, "mphy");
++ if (IS_ERR(host->mphy_base))
++ return dev_err_probe(dev, PTR_ERR(host->mphy_base),
++ "Failed to map mphy base registers\n");
++
++ host->rst = devm_reset_control_array_get_exclusive(dev);
++ if (IS_ERR(host->rst))
++ return dev_err_probe(dev, PTR_ERR(host->rst),
++ "failed to get reset control\n");
++
++ reset_control_assert(host->rst);
++ udelay(1);
++ reset_control_deassert(host->rst);
++
++ host->ref_out_clk = devm_clk_get_enabled(dev, "ref_out");
++ if (IS_ERR(host->ref_out_clk))
++ return dev_err_probe(dev, PTR_ERR(host->ref_out_clk),
++ "ref_out clock unavailable\n");
++
++ host->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
++ if (IS_ERR(host->rst_gpio))
++ return dev_err_probe(dev, PTR_ERR(host->rst_gpio),
++ "failed to get reset gpio\n");
++
++ err = devm_clk_bulk_get_all_enabled(dev, &host->clks);
++ if (err)
++ return dev_err_probe(dev, err, "failed to enable clocks\n");
++
++ host->hba = hba;
++
++ ufshcd_set_variant(hba, host);
++
++ return 0;
++}
++
++static int ufs_rockchip_rk3576_init(struct ufs_hba *hba)
++{
++ struct device *dev = hba->dev;
++ int ret;
++
++ hba->quirks = UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING;
++
++ /* Enable BKOPS when suspend */
++ hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
++ /* Enable putting device into deep sleep */
++ hba->caps |= UFSHCD_CAP_DEEPSLEEP;
++ /* Enable devfreq of UFS */
++ hba->caps |= UFSHCD_CAP_CLK_SCALING;
++ /* Enable WriteBooster */
++ hba->caps |= UFSHCD_CAP_WB_EN;
++
++ /* Set the default desired pm level in case no users set via sysfs */
++ ufs_rockchip_set_pm_lvl(hba);
++
++ ret = ufs_rockchip_common_init(hba);
++ if (ret)
++ return dev_err_probe(dev, ret, "ufs common init fail\n");
++
++ return 0;
++}
++
++static int ufs_rockchip_device_reset(struct ufs_hba *hba)
++{
++ struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
++
++ gpiod_set_value_cansleep(host->rst_gpio, 1);
++ usleep_range(20, 25);
++
++ gpiod_set_value_cansleep(host->rst_gpio, 0);
++ usleep_range(20, 25);
++
++ return 0;
++}
++
++static const struct ufs_hba_variant_ops ufs_hba_rk3576_vops = {
++ .name = "rk3576",
++ .init = ufs_rockchip_rk3576_init,
++ .device_reset = ufs_rockchip_device_reset,
++ .hce_enable_notify = ufs_rockchip_hce_enable_notify,
++ .phy_initialization = ufs_rockchip_rk3576_phy_init,
++};
++
++static const struct of_device_id ufs_rockchip_of_match[] = {
++ { .compatible = "rockchip,rk3576-ufshc", .data = &ufs_hba_rk3576_vops },
++ { },
++};
++MODULE_DEVICE_TABLE(of, ufs_rockchip_of_match);
++
++static int ufs_rockchip_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ const struct ufs_hba_variant_ops *vops;
++ int err;
++
++ vops = device_get_match_data(dev);
++ if (!vops)
++ return dev_err_probe(dev, -ENODATA, "ufs_hba_variant_ops not defined.\n");
++
++ err = ufshcd_pltfrm_init(pdev, vops);
++ if (err)
++ return dev_err_probe(dev, err, "ufshcd_pltfrm_init failed\n");
++
++ return 0;
++}
++
++static void ufs_rockchip_remove(struct platform_device *pdev)
++{
++ ufshcd_pltfrm_remove(pdev);
++}
++
++#ifdef CONFIG_PM
++static int ufs_rockchip_runtime_suspend(struct device *dev)
++{
++ struct ufs_hba *hba = dev_get_drvdata(dev);
++ struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
++
++ clk_disable_unprepare(host->ref_out_clk);
++
++ /* Do not power down the genpd if rpm_lvl is less than level 5 */
++ dev_pm_genpd_rpm_always_on(dev, hba->rpm_lvl < UFS_PM_LVL_5 ? true : false);
++
++ return ufshcd_runtime_suspend(dev);
++}
++
++static int ufs_rockchip_runtime_resume(struct device *dev)
++{
++ struct ufs_hba *hba = dev_get_drvdata(dev);
++ struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
++ int err;
++
++ err = clk_prepare_enable(host->ref_out_clk);
++ if (err) {
++ dev_err(hba->dev, "failed to enable ref_out clock %d\n", err);
++ return err;
++ }
++
++ reset_control_assert(host->rst);
++ udelay(1);
++ reset_control_deassert(host->rst);
++
++ return ufshcd_runtime_resume(dev);
++}
++#endif
++
++#ifdef CONFIG_PM_SLEEP
++static int ufs_rockchip_system_suspend(struct device *dev)
++{
++ struct ufs_hba *hba = dev_get_drvdata(dev);
++ struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
++ int err;
++
++ /*
++ * If spm_lvl is less than level 5, it means we need to keep the host
++ * controller in powered-on state. So device_set_awake_path() is
++ * calling pm core to notify the genpd provider to meet this requirement
++ */
++ if (hba->spm_lvl < UFS_PM_LVL_5)
++ device_set_awake_path(dev);
++
++ err = ufshcd_system_suspend(dev);
++ if (err) {
++ dev_err(hba->dev, "UFSHCD system susped failed %d\n", err);
++ return err;
++ }
++
++ clk_disable_unprepare(host->ref_out_clk);
++
++ return 0;
++}
++
++static int ufs_rockchip_system_resume(struct device *dev)
++{
++ struct ufs_hba *hba = dev_get_drvdata(dev);
++ struct ufs_rockchip_host *host = ufshcd_get_variant(hba);
++ int err;
++
++ err = clk_prepare_enable(host->ref_out_clk);
++ if (err) {
++ dev_err(hba->dev, "failed to enable ref_out clock %d\n", err);
++ return err;
++ }
++
++ return ufshcd_system_resume(dev);
++}
++#endif
++
++static const struct dev_pm_ops ufs_rockchip_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(ufs_rockchip_system_suspend, ufs_rockchip_system_resume)
++ SET_RUNTIME_PM_OPS(ufs_rockchip_runtime_suspend, ufs_rockchip_runtime_resume, NULL)
++ .prepare = ufshcd_suspend_prepare,
++ .complete = ufshcd_resume_complete,
++};
++
++static struct platform_driver ufs_rockchip_pltform = {
++ .probe = ufs_rockchip_probe,
++ .remove = ufs_rockchip_remove,
++ .driver = {
++ .name = "ufshcd-rockchip",
++ .pm = &ufs_rockchip_pm_ops,
++ .of_match_table = ufs_rockchip_of_match,
++ },
++};
++module_platform_driver(ufs_rockchip_pltform);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Rockchip UFS Host Driver");
+--- /dev/null
++++ b/drivers/ufs/host/ufs-rockchip.h
+@@ -0,0 +1,90 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Rockchip UFS Host Controller driver
++ *
++ * Copyright (C) 2025 Rockchip Electronics Co., Ltd.
++ */
++
++#ifndef _UFS_ROCKCHIP_H_
++#define _UFS_ROCKCHIP_H_
++
++#define SEL_TX_LANE0 0x0
++#define SEL_TX_LANE1 0x1
++#define SEL_TX_LANE2 0x2
++#define SEL_TX_LANE3 0x3
++#define SEL_RX_LANE0 0x4
++#define SEL_RX_LANE1 0x5
++#define SEL_RX_LANE2 0x6
++#define SEL_RX_LANE3 0x7
++
++#define VND_TX_CLK_PRD 0xAA
++#define VND_TX_CLK_PRD_EN 0xA9
++#define VND_TX_LINERESET_PVALUE2 0xAB
++#define VND_TX_LINERESET_PVALUE1 0xAC
++#define VND_TX_LINERESET_VALUE 0xAD
++#define VND_TX_BASE_NVALUE 0x93
++#define VND_TX_TASE_VALUE 0x94
++#define VND_TX_POWER_SAVING_CTRL 0x7F
++#define VND_RX_CLK_PRD 0x12
++#define VND_RX_CLK_PRD_EN 0x11
++#define VND_RX_LINERESET_PVALUE2 0x1B
++#define VND_RX_LINERESET_PVALUE1 0x1C
++#define VND_RX_LINERESET_VALUE 0x1D
++#define VND_RX_LINERESET_OPTION 0x25
++#define VND_RX_POWER_SAVING_CTRL 0x2F
++#define VND_RX_SAVE_DET_CTRL 0x1E
++
++#define CMN_REG23 0x8C
++#define CMN_REG25 0x94
++#define TRSV0_REG08 0xE0
++#define TRSV1_REG08 0x220
++#define TRSV0_REG14 0x110
++#define TRSV1_REG14 0x250
++#define TRSV0_REG15 0x134
++#define TRSV1_REG15 0x274
++#define TRSV0_REG16 0x128
++#define TRSV1_REG16 0x268
++#define TRSV0_REG17 0x12C
++#define TRSV1_REG17 0x26c
++#define TRSV0_REG18 0x120
++#define TRSV1_REG18 0x260
++#define TRSV0_REG29 0x164
++#define TRSV1_REG29 0x2A4
++#define TRSV0_REG2E 0x178
++#define TRSV1_REG2E 0x2B8
++#define TRSV0_REG3C 0x1B0
++#define TRSV1_REG3C 0x2F0
++#define TRSV0_REG3D 0x1B4
++#define TRSV1_REG3D 0x2F4
++
++#define MPHY_CFG 0x200
++#define MPHY_CFG_ENABLE 0x40
++#define MPHY_CFG_DISABLE 0x0
++
++#define MIB_T_DBG_CPORT_TX_ENDIAN 0xc022
++#define MIB_T_DBG_CPORT_RX_ENDIAN 0xc023
++
++struct ufs_rockchip_host {
++ struct ufs_hba *hba;
++ void __iomem *ufs_phy_ctrl;
++ void __iomem *ufs_sys_ctrl;
++ void __iomem *mphy_base;
++ struct gpio_desc *rst_gpio;
++ struct reset_control *rst;
++ struct clk *ref_out_clk;
++ struct clk_bulk_data *clks;
++ uint64_t caps;
++};
++
++#define ufs_sys_writel(base, val, reg) \
++ writel((val), (base) + (reg))
++#define ufs_sys_readl(base, reg) readl((base) + (reg))
++#define ufs_sys_set_bits(base, mask, reg) \
++ ufs_sys_writel( \
++ (base), ((mask) | (ufs_sys_readl((base), (reg)))), (reg))
++#define ufs_sys_ctrl_clr_bits(base, mask, reg) \
++ ufs_sys_writel((base), \
++ ((~(mask)) & (ufs_sys_readl((base), (reg)))), \
++ (reg))
++
++#endif /* _UFS_ROCKCHIP_H_ */
--- /dev/null
+From 4fffffd3b13439980d778c58b1f63439287b9fdc Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Wed, 26 Feb 2025 14:52:13 +0800
+Subject: [PATCH] scsi: ufs: rockchip: Fix devm_clk_bulk_get_all_enabled()
+ return value
+
+A positive value is for the number of clocks obtained if assigned.
+
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Link: https://lore.kernel.org/r/1740552733-182527-1-git-send-email-shawn.lin@rock-chips.com
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+---
+ drivers/ufs/host/ufs-rockchip.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/ufs/host/ufs-rockchip.c
++++ b/drivers/ufs/host/ufs-rockchip.c
+@@ -171,7 +171,7 @@ static int ufs_rockchip_common_init(stru
+ "failed to get reset gpio\n");
+
+ err = devm_clk_bulk_get_all_enabled(dev, &host->clks);
+- if (err)
++ if (err < 0)
+ return dev_err_probe(dev, err, "failed to enable clocks\n");
+
+ host->hba = hba;
--- /dev/null
+From fda1e0af7c28f96d4f33e57cf51565b0e9c14e63 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Fri, 31 Oct 2025 16:58:23 +0100
+Subject: [PATCH] mmc: sdhci-of-dwcmshc: Add command queue support for rockchip
+ SOCs
+
+This adds CQE support for the Rockchip RK3588 and RK3576 platform. To
+be functional, the eMMC device-tree node must have a 'supports-cqe;'
+flag property.
+
+As the RK3576 device-tree has been upstreamed with the 'supports-cqe;'
+property set by default, the kernel already tried to use CQE, which
+results in system hang during suspend. This fixes the issue.
+
+Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
+Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/sdhci-of-dwcmshc.c | 93 ++++++++++++++++++++++++++++-
+ 1 file changed, 90 insertions(+), 3 deletions(-)
+
+--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
+@@ -24,6 +24,7 @@
+
+ #include "sdhci-pltfm.h"
+ #include "cqhci.h"
++#include "sdhci-cqhci.h"
+
+ #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16)
+
+@@ -82,6 +83,8 @@
+ #define DWCMSHC_EMMC_DLL_TXCLK 0x808
+ #define DWCMSHC_EMMC_DLL_STRBIN 0x80c
+ #define DECMSHC_EMMC_DLL_CMDOUT 0x810
++#define DECMSHC_EMMC_MISC_CON 0x81C
++#define MISC_INTCLK_EN BIT(1)
+ #define DWCMSHC_EMMC_DLL_STATUS0 0x840
+ #define DWCMSHC_EMMC_DLL_START BIT(0)
+ #define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
+@@ -234,6 +237,7 @@ struct dwcmshc_priv {
+
+ struct dwcmshc_pltfm_data {
+ const struct sdhci_pltfm_data pdata;
++ const struct cqhci_host_ops *cqhci_host_ops;
+ int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv);
+ void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv);
+ };
+@@ -616,6 +620,68 @@ static void dwcmshc_cqhci_dumpregs(struc
+ sdhci_dumpregs(mmc_priv(mmc));
+ }
+
++static void rk35xx_sdhci_cqe_pre_enable(struct mmc_host *mmc)
++{
++ struct sdhci_host *host = mmc_priv(mmc);
++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
++ u32 reg;
++
++ reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
++ reg |= CQHCI_ENABLE;
++ sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
++}
++
++static void rk35xx_sdhci_cqe_enable(struct mmc_host *mmc)
++{
++ struct sdhci_host *host = mmc_priv(mmc);
++ u32 reg;
++
++ reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
++ while (reg & SDHCI_DATA_AVAILABLE) {
++ sdhci_readl(host, SDHCI_BUFFER);
++ reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
++ }
++
++ sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
++
++ sdhci_cqe_enable(mmc);
++}
++
++static void rk35xx_sdhci_cqe_disable(struct mmc_host *mmc, bool recovery)
++{
++ struct sdhci_host *host = mmc_priv(mmc);
++ unsigned long flags;
++ u32 ctrl;
++
++ /*
++ * During CQE command transfers, command complete bit gets latched.
++ * So s/w should clear command complete interrupt status when CQE is
++ * either halted or disabled. Otherwise unexpected SDCHI legacy
++ * interrupt gets triggered when CQE is halted/disabled.
++ */
++ spin_lock_irqsave(&host->lock, flags);
++ ctrl = sdhci_readl(host, SDHCI_INT_ENABLE);
++ ctrl |= SDHCI_INT_RESPONSE;
++ sdhci_writel(host, ctrl, SDHCI_INT_ENABLE);
++ sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS);
++ spin_unlock_irqrestore(&host->lock, flags);
++
++ sdhci_cqe_disable(mmc, recovery);
++}
++
++static void rk35xx_sdhci_cqe_post_disable(struct mmc_host *mmc)
++{
++ struct sdhci_host *host = mmc_priv(mmc);
++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
++ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
++ u32 ctrl;
++
++ ctrl = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
++ ctrl &= ~CQHCI_ENABLE;
++ sdhci_writel(host, ctrl, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
++}
++
+ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock)
+ {
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+@@ -741,6 +807,10 @@ static void rk35xx_sdhci_reset(struct sd
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+ struct rk35xx_priv *priv = dwc_priv->priv;
++ u32 extra = sdhci_readl(host, DECMSHC_EMMC_MISC_CON);
++
++ if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL))
++ cqhci_deactivate(host->mmc);
+
+ if (mask & SDHCI_RESET_ALL && priv->reset) {
+ reset_control_assert(priv->reset);
+@@ -749,6 +819,9 @@ static void rk35xx_sdhci_reset(struct sd
+ }
+
+ sdhci_reset(host, mask);
++
++ /* Enable INTERNAL CLOCK */
++ sdhci_writel(host, MISC_INTCLK_EN | extra, DECMSHC_EMMC_MISC_CON);
+ }
+
+ static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host,
+@@ -1242,6 +1315,15 @@ static const struct dwcmshc_pltfm_data s
+ };
+ #endif
+
++static const struct cqhci_host_ops rk35xx_cqhci_ops = {
++ .pre_enable = rk35xx_sdhci_cqe_pre_enable,
++ .enable = rk35xx_sdhci_cqe_enable,
++ .disable = rk35xx_sdhci_cqe_disable,
++ .post_disable = rk35xx_sdhci_cqe_post_disable,
++ .dumpregs = dwcmshc_cqhci_dumpregs,
++ .set_tran_desc = dwcmshc_set_tran_desc,
++};
++
+ static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = {
+ .pdata = {
+ .ops = &sdhci_dwcmshc_rk35xx_ops,
+@@ -1250,6 +1332,7 @@ static const struct dwcmshc_pltfm_data s
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
+ },
++ .cqhci_host_ops = &rk35xx_cqhci_ops,
+ .init = dwcmshc_rk35xx_init,
+ .postinit = dwcmshc_rk35xx_postinit,
+ };
+@@ -1299,7 +1382,8 @@ static const struct cqhci_host_ops dwcms
+ .set_tran_desc = dwcmshc_set_tran_desc,
+ };
+
+-static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev)
++static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev,
++ const struct dwcmshc_pltfm_data *pltfm_data)
+ {
+ struct cqhci_host *cq_host;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+@@ -1329,7 +1413,10 @@ static void dwcmshc_cqhci_init(struct sd
+ }
+
+ cq_host->mmio = host->ioaddr + priv->vendor_specific_area2;
+- cq_host->ops = &dwcmshc_cqhci_ops;
++ if (pltfm_data->cqhci_host_ops)
++ cq_host->ops = pltfm_data->cqhci_host_ops;
++ else
++ cq_host->ops = &dwcmshc_cqhci_ops;
+
+ /* Enable using of 128-bit task descriptors */
+ dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
+@@ -1498,7 +1585,7 @@ static int dwcmshc_probe(struct platform
+ priv->vendor_specific_area2 =
+ sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2);
+
+- dwcmshc_cqhci_init(host, pdev);
++ dwcmshc_cqhci_init(host, pdev, pltfm_data);
+ }
+
+ if (pltfm_data->postinit)
--- /dev/null
+From 69cc9d4075855661268327c38c9b0e71ac37eb1c Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Fri, 21 Nov 2025 17:26:59 +0100
+Subject: [PATCH] mmc: sdhci-of-dwcmshc: Fix command queue support for RK3576
+
+When I added command queue engine (CQE) support for the Rockchip eMMC
+controller, I missed that RK3576 has a separate platform data struct.
+While things are working fine on RK3588 (I tested the ROCK 5B) and
+the suspend issue is fixed on the RK3576 (I tested the Sige5), this
+results in stability issues. By also adding the necessary hooks for
+the RK3576 platform the following problems can be avoided:
+
+[ 15.606895] mmc0: running CQE recovery
+[ 15.616189] mmc0: running CQE recovery
+[...]
+[ 25.911484] mmc0: running CQE recovery
+[ 25.926305] mmc0: running CQE recovery
+[ 25.927468] mmc0: running CQE recovery
+[...]
+[ 26.255719] mmc0: running CQE recovery
+[ 26.257162] ------------[ cut here ]------------
+[ 26.257581] mmc0: cqhci: spurious TCN for tag 31
+[ 26.258034] WARNING: CPU: 0 PID: 0 at drivers/mmc/host/cqhci-core.c:796 cqhci_irq+0x440/0x68c
+[ 26.263786] CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 6.18.0-rc6-gd984ebbf0d15 #1 PREEMPT
+[ 26.264561] Hardware name: ArmSoM Sige5 (DT)
+[...]
+[ 26.272748] Call trace:
+[ 26.272964] cqhci_irq+0x440/0x68c (P)
+[ 26.273296] dwcmshc_cqe_irq_handler+0x54/0x88
+[ 26.273689] sdhci_irq+0xbc/0x1200
+[ 26.273991] __handle_irq_event_percpu+0x54/0x1d0
+[...]
+
+Note that the above problems do not necessarily happen with every boot.
+
+Reported-by: Adrian Hunter <adrian.hunter@intel.com>
+Closes: https://lore.kernel.org/linux-rockchip/01949bc9-4873-498b-ac7d-f008393ccc4c@intel.com/
+Fixes: fda1e0af7c28f ("mmc: sdhci-of-dwcmshc: Add command queue support for rockchip SOCs")
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/sdhci-of-dwcmshc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
+@@ -1345,6 +1345,7 @@ static const struct dwcmshc_pltfm_data s
+ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+ SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
+ },
++ .cqhci_host_ops = &rk35xx_cqhci_ops,
+ .init = dwcmshc_rk35xx_init,
+ .postinit = dwcmshc_rk3576_postinit,
+ };
--- /dev/null
+From c7ce6453b769c45006ed4983762f81e130878171 Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Wed, 26 Nov 2025 07:26:39 +0800
+Subject: [PATCH] mmc: sdhci-of-dwcmshc: Disable internal clock auto gate for
+ Rockchip SOCs
+
+Enabling CMDQ support can lead to random occurrences of the error log when
+there are RPMB access and data flush executed:
+
+"mmc2: Timeout waiting for hardware interrupt."
+
+Enabling CMDQ and then issuing a DCMD as the final command before disabling
+it causes the eMMC controller to auto-gate its internal clock. Chip simulation
+shows this results in a state machine mismatch after CMDQ mode exit, triggering
+data-timeout errors for all subsequent read and write operations.
+
+Therefore, the auto-clock-gate function must be disabled whenever CMDQ is
+enabled.
+
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Fixes: fda1e0af7c28 ("mmc: sdhci-of-dwcmshc: Add command queue support for rockchip SOCs")
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/sdhci-of-dwcmshc.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
+@@ -709,10 +709,11 @@ static void dwcmshc_rk3568_set_clock(str
+
+ sdhci_set_clock(host, clock);
+
+- /* Disable cmd conflict check */
++ /* Disable cmd conflict check and internal clock gate */
+ reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
+ extra = sdhci_readl(host, reg);
+ extra &= ~BIT(0);
++ extra |= BIT(4);
+ sdhci_writel(host, extra, reg);
+
+ if (clock <= 52000000) {
--- /dev/null
+From 79cf71c0b177c0e23d411e2469435e2c2f83f563 Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Wed, 26 Nov 2025 07:26:40 +0800
+Subject: [PATCH] mmc: sdhci-of-dwcmshc: reduce CIT for better performance
+
+CQHCI_SSC1.CIT indicates to the CQE the polling period to use for
+periodic SEND_QUEUE_STATUS (CMD13) polling. Some eMMCs have only one
+hardware queue, and CMD13 can only query one slot at a time for data
+transmission, which cannot be processed in parallel. Modifying the
+CMD13 query interval can increase the query frequency and improve
+random write performance.
+
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/cqhci.h | 1 +
+ drivers/mmc/host/sdhci-of-dwcmshc.c | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+--- a/drivers/mmc/host/cqhci.h
++++ b/drivers/mmc/host/cqhci.h
+@@ -93,6 +93,7 @@
+ /* send status config 1 */
+ #define CQHCI_SSC1 0x40
+ #define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
++#define CQHCI_SSC1_CIT_MASK GENMASK(15, 0)
+
+ /* send status config 2 */
+ #define CQHCI_SSC2 0x44
+--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
+@@ -627,6 +627,11 @@ static void rk35xx_sdhci_cqe_pre_enable(
+ struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
+ u32 reg;
+
++ /* Set Send Status Command Idle Timer to 10.66us (256 * 1 / 24) */
++ reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
++ reg = (reg & ~CQHCI_SSC1_CIT_MASK) | 0x0100;
++ sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
++
+ reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
+ reg |= CQHCI_ENABLE;
+ sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
--- /dev/null
+From 8a9aa0bbd615c9b377bd82e671519f0c4cb272dd Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Thu, 27 Feb 2025 18:40:51 +0000
+Subject: [PATCH] iio: adc: rockchip_saradc: Add support for RK3528
+
+The Successive Approximation ADC (SARADC) in RK3528 uses the v2
+controller and support:
+- 10-bit resolution
+- Up to 1MS/s sampling rate
+- 4 single-ended input channels
+- Current consumption: 0.5mA @ 1MS/s
+
+Add support for the 4 channels of 10-bit resolution supported by SARADC
+in RK3528.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patch.msgid.link/20250227184058.2964204-3-jonas@kwiboo.se
+Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+---
+ drivers/iio/adc/rockchip_saradc.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+--- a/drivers/iio/adc/rockchip_saradc.c
++++ b/drivers/iio/adc/rockchip_saradc.c
+@@ -275,6 +275,21 @@ static const struct rockchip_saradc_data
+ .power_down = rockchip_saradc_power_down_v1,
+ };
+
++static const struct iio_chan_spec rockchip_rk3528_saradc_iio_channels[] = {
++ SARADC_CHANNEL(0, "adc0", 10),
++ SARADC_CHANNEL(1, "adc1", 10),
++ SARADC_CHANNEL(2, "adc2", 10),
++ SARADC_CHANNEL(3, "adc3", 10),
++};
++
++static const struct rockchip_saradc_data rk3528_saradc_data = {
++ .channels = rockchip_rk3528_saradc_iio_channels,
++ .num_channels = ARRAY_SIZE(rockchip_rk3528_saradc_iio_channels),
++ .clk_rate = 1000000,
++ .start = rockchip_saradc_start_v2,
++ .read = rockchip_saradc_read_v2,
++};
++
+ static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
+ SARADC_CHANNEL(0, "adc0", 10),
+ SARADC_CHANNEL(1, "adc1", 10),
+@@ -325,6 +340,9 @@ static const struct of_device_id rockchi
+ .compatible = "rockchip,rk3399-saradc",
+ .data = &rk3399_saradc_data,
+ }, {
++ .compatible = "rockchip,rk3528-saradc",
++ .data = &rk3528_saradc_data,
++ }, {
+ .compatible = "rockchip,rk3568-saradc",
+ .data = &rk3568_saradc_data,
+ }, {
--- /dev/null
+From 1725f0eb37d621ce48303ccc14748fb66d618c9e Mon Sep 17 00:00:00 2001
+From: David Wu <david.wu@rock-chips.com>
+Date: Wed, 19 Mar 2025 21:44:06 +0000
+Subject: [PATCH] net: stmmac: dwmac-rk: Add GMAC support for RK3528
+
+Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
+Ethernet QoS IP.
+
+Add initial support for the RK3528 GMAC variant.
+
+Signed-off-by: David Wu <david.wu@rock-chips.com>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://patch.msgid.link/20250319214415.3086027-3-jonas@kwiboo.se
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 132 ++++++++++++++++++
+ 1 file changed, 132 insertions(+)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+@@ -1014,6 +1014,137 @@ static const struct rk_gmac_ops rk3399_o
+ .set_rmii_speed = rk3399_set_rmii_speed,
+ };
+
++#define RK3528_VO_GRF_GMAC_CON 0x0018
++#define RK3528_VO_GRF_MACPHY_CON0 0x001c
++#define RK3528_VO_GRF_MACPHY_CON1 0x0020
++#define RK3528_VPU_GRF_GMAC_CON5 0x0018
++#define RK3528_VPU_GRF_GMAC_CON6 0x001c
++
++#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
++#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
++#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
++#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
++
++#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
++#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
++
++#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
++#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
++#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
++
++#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12)
++#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12)
++
++#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
++#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
++#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
++#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
++
++#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
++#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10))
++#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10))
++
++#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
++#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
++#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
++#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
++
++static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
++ int tx_delay, int rx_delay)
++{
++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
++ RK3528_GMAC1_PHY_INTF_SEL_RGMII);
++
++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
++ DELAY_ENABLE(RK3528, tx_delay, rx_delay));
++
++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
++ RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) |
++ RK3528_GMAC_CLK_TX_DL_CFG(tx_delay));
++}
++
++static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
++{
++ if (bsp_priv->id == 1)
++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
++ RK3528_GMAC1_PHY_INTF_SEL_RMII);
++ else
++ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
++ RK3528_GMAC0_PHY_INTF_SEL_RMII |
++ RK3528_GMAC0_CLK_RMII_DIV2);
++}
++
++static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
++{
++ struct device *dev = &bsp_priv->pdev->dev;
++
++ if (speed == 10)
++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
++ RK3528_GMAC1_CLK_RGMII_DIV50);
++ else if (speed == 100)
++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
++ RK3528_GMAC1_CLK_RGMII_DIV5);
++ else if (speed == 1000)
++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
++ RK3528_GMAC1_CLK_RGMII_DIV1);
++ else
++ dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
++}
++
++static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
++{
++ struct device *dev = &bsp_priv->pdev->dev;
++ unsigned int reg, val;
++
++ if (speed == 10)
++ val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV20 :
++ RK3528_GMAC0_CLK_RMII_DIV20;
++ else if (speed == 100)
++ val = bsp_priv->id == 1 ? RK3528_GMAC1_CLK_RMII_DIV2 :
++ RK3528_GMAC0_CLK_RMII_DIV2;
++ else {
++ dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
++ return;
++ }
++
++ reg = bsp_priv->id == 1 ? RK3528_VPU_GRF_GMAC_CON5 :
++ RK3528_VO_GRF_GMAC_CON;
++
++ regmap_write(bsp_priv->grf, reg, val);
++}
++
++static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
++ bool input, bool enable)
++{
++ unsigned int val;
++
++ if (bsp_priv->id == 1) {
++ val = input ? RK3528_GMAC1_CLK_SELECT_IO :
++ RK3528_GMAC1_CLK_SELECT_CRU;
++ val |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
++ RK3528_GMAC1_CLK_RMII_GATE;
++ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
++ } else {
++ val = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
++ RK3528_GMAC0_CLK_RMII_GATE;
++ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val);
++ }
++}
++
++static const struct rk_gmac_ops rk3528_ops = {
++ .set_to_rgmii = rk3528_set_to_rgmii,
++ .set_to_rmii = rk3528_set_to_rmii,
++ .set_rgmii_speed = rk3528_set_rgmii_speed,
++ .set_rmii_speed = rk3528_set_rmii_speed,
++ .set_clock_selection = rk3528_set_clock_selection,
++ .regs_valid = true,
++ .regs = {
++ 0xffbd0000, /* gmac0 */
++ 0xffbe0000, /* gmac1 */
++ 0x0, /* sentinel */
++ },
++};
++
+ #define RK3568_GRF_GMAC0_CON0 0x0380
+ #define RK3568_GRF_GMAC0_CON1 0x0384
+ #define RK3568_GRF_GMAC1_CON0 0x0388
+@@ -2080,6 +2211,7 @@ static const struct of_device_id rk_gmac
+ { .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
+ { .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
+ { .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
++ { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
+ { .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
+ { .compatible = "rockchip,rk3576-gmac", .data = &rk3576_ops },
+ { .compatible = "rockchip,rk3588-gmac", .data = &rk3588_ops },
--- /dev/null
+From 0bed91f2b183bc38c216299ce035b44210148785 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 19 Mar 2025 21:44:07 +0000
+Subject: [PATCH] net: stmmac: dwmac-rk: Move integrated_phy_powerup/down
+ functions
+
+Rockchip RK3528 (and RV1106) has a different integrated PHY compared to
+the integrated PHY on RK3228/RK3328. Current powerup/down operation is
+not compatible with the integrated PHY found in these SoCs.
+
+Move the rk_gmac_integrated_phy_powerup/down functions to top of the
+file to prepare for them to be called directly by a GMAC variant
+specific powerup/down operation.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://patch.msgid.link/20250319214415.3086027-4-jonas@kwiboo.se
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 88 +++++++++----------
+ 1 file changed, 44 insertions(+), 44 deletions(-)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+@@ -92,6 +92,50 @@ struct rk_priv_data {
+ (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
+ ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
+
++#define RK_GRF_MACPHY_CON0 0xb00
++#define RK_GRF_MACPHY_CON1 0xb04
++#define RK_GRF_MACPHY_CON2 0xb08
++#define RK_GRF_MACPHY_CON3 0xb0c
++
++#define RK_MACPHY_ENABLE GRF_BIT(0)
++#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
++#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
++#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
++#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
++#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
++
++static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
++{
++ if (priv->ops->integrated_phy_powerup)
++ priv->ops->integrated_phy_powerup(priv);
++
++ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
++ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
++
++ regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
++ regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
++
++ if (priv->phy_reset) {
++ /* PHY needs to be disabled before trying to reset it */
++ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
++ if (priv->phy_reset)
++ reset_control_assert(priv->phy_reset);
++ usleep_range(10, 20);
++ if (priv->phy_reset)
++ reset_control_deassert(priv->phy_reset);
++ usleep_range(10, 20);
++ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
++ msleep(30);
++ }
++}
++
++static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
++{
++ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
++ if (priv->phy_reset)
++ reset_control_assert(priv->phy_reset);
++}
++
+ #define PX30_GRF_GMAC_CON1 0x0904
+
+ /* PX30_GRF_GMAC_CON1 */
+@@ -1730,50 +1774,6 @@ static const struct rk_gmac_ops rv1126_o
+ .set_rmii_speed = rv1126_set_rmii_speed,
+ };
+
+-#define RK_GRF_MACPHY_CON0 0xb00
+-#define RK_GRF_MACPHY_CON1 0xb04
+-#define RK_GRF_MACPHY_CON2 0xb08
+-#define RK_GRF_MACPHY_CON3 0xb0c
+-
+-#define RK_MACPHY_ENABLE GRF_BIT(0)
+-#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
+-#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
+-#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
+-#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
+-#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
+-
+-static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
+-{
+- if (priv->ops->integrated_phy_powerup)
+- priv->ops->integrated_phy_powerup(priv);
+-
+- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
+- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
+-
+- regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
+- regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
+-
+- if (priv->phy_reset) {
+- /* PHY needs to be disabled before trying to reset it */
+- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
+- if (priv->phy_reset)
+- reset_control_assert(priv->phy_reset);
+- usleep_range(10, 20);
+- if (priv->phy_reset)
+- reset_control_deassert(priv->phy_reset);
+- usleep_range(10, 20);
+- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
+- msleep(30);
+- }
+-}
+-
+-static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
+-{
+- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
+- if (priv->phy_reset)
+- reset_control_assert(priv->phy_reset);
+-}
+-
+ static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
+ {
+ struct rk_priv_data *bsp_priv = plat->bsp_priv;
--- /dev/null
+From 32c7bc0747bbd8ee4ee32026d36a24be56117d96 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 19 Mar 2025 21:44:08 +0000
+Subject: [PATCH] net: stmmac: dwmac-rk: Add integrated_phy_powerdown operation
+
+Rockchip RK3528 (and RV1106) has a different integrated PHY compared to
+the integrated PHY on RK3228/RK3328. Current powerup/down operation is
+not compatible with the integrated PHY found in these newer SoCs.
+
+Add a new integrated_phy_powerdown operation and change the call chain
+for integrated_phy_powerup to prepare support for the integrated PHY
+found in these newer SoCs.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://patch.msgid.link/20250319214415.3086027-5-jonas@kwiboo.se
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 26 +++++++++++--------
+ 1 file changed, 15 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+@@ -33,6 +33,7 @@ struct rk_gmac_ops {
+ void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
+ bool enable);
+ void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
++ void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv);
+ bool php_grf_required;
+ bool regs_valid;
+ u32 regs[];
+@@ -104,11 +105,8 @@ struct rk_priv_data {
+ #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
+ #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
+
+-static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
++static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
+ {
+- if (priv->ops->integrated_phy_powerup)
+- priv->ops->integrated_phy_powerup(priv);
+-
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
+
+@@ -129,7 +127,7 @@ static void rk_gmac_integrated_phy_power
+ }
+ }
+
+-static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
++static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
+ {
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
+ if (priv->phy_reset)
+@@ -423,6 +421,8 @@ static void rk3228_integrated_phy_poweru
+ {
+ regmap_write(priv->grf, RK3228_GRF_CON_MUX,
+ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
++
++ rk_gmac_integrated_ephy_powerup(priv);
+ }
+
+ static const struct rk_gmac_ops rk3228_ops = {
+@@ -430,7 +430,8 @@ static const struct rk_gmac_ops rk3228_o
+ .set_to_rmii = rk3228_set_to_rmii,
+ .set_rgmii_speed = rk3228_set_rgmii_speed,
+ .set_rmii_speed = rk3228_set_rmii_speed,
+- .integrated_phy_powerup = rk3228_integrated_phy_powerup,
++ .integrated_phy_powerup = rk3228_integrated_phy_powerup,
++ .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
+ };
+
+ #define RK3288_GRF_SOC_CON1 0x0248
+@@ -715,6 +716,8 @@ static void rk3328_integrated_phy_poweru
+ {
+ regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
+ RK3328_MACPHY_RMII_MODE);
++
++ rk_gmac_integrated_ephy_powerup(priv);
+ }
+
+ static const struct rk_gmac_ops rk3328_ops = {
+@@ -722,7 +725,8 @@ static const struct rk_gmac_ops rk3328_o
+ .set_to_rmii = rk3328_set_to_rmii,
+ .set_rgmii_speed = rk3328_set_rgmii_speed,
+ .set_rmii_speed = rk3328_set_rmii_speed,
+- .integrated_phy_powerup = rk3328_integrated_phy_powerup,
++ .integrated_phy_powerup = rk3328_integrated_phy_powerup,
++ .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown,
+ };
+
+ #define RK3366_GRF_SOC_CON6 0x0418
+@@ -2070,16 +2074,16 @@ static int rk_gmac_powerup(struct rk_pri
+
+ pm_runtime_get_sync(dev);
+
+- if (bsp_priv->integrated_phy)
+- rk_gmac_integrated_phy_powerup(bsp_priv);
++ if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup)
++ bsp_priv->ops->integrated_phy_powerup(bsp_priv);
+
+ return 0;
+ }
+
+ static void rk_gmac_powerdown(struct rk_priv_data *gmac)
+ {
+- if (gmac->integrated_phy)
+- rk_gmac_integrated_phy_powerdown(gmac);
++ if (gmac->integrated_phy && gmac->ops->integrated_phy_powerdown)
++ gmac->ops->integrated_phy_powerdown(gmac);
+
+ pm_runtime_put_sync(&gmac->pdev->dev);
+
--- /dev/null
+From 83e7b35c7879497b51fd3fcd3a17b0b07f89e81b Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 19 Mar 2025 21:44:09 +0000
+Subject: [PATCH] net: stmmac: dwmac-rk: Add initial support for RK3528
+ integrated PHY
+
+Rockchip RK3528 (and RV1106) has a different integrated PHY compared to
+the integrated PHY on RK3228/RK3328. Current powerup/down operation is
+not compatible with the integrated PHY found in these newer SoCs.
+
+Add operations to powerup/down the integrated PHY found in RK3528.
+Use helpers that can be used by other GMAC variants in the future.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://patch.msgid.link/20250319214415.3086027-6-jonas@kwiboo.se
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 41 +++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+@@ -134,6 +134,35 @@ static void rk_gmac_integrated_ephy_powe
+ reset_control_assert(priv->phy_reset);
+ }
+
++#define RK_FEPHY_SHUTDOWN GRF_BIT(1)
++#define RK_FEPHY_POWERUP GRF_CLR_BIT(1)
++#define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6)
++#define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9))
++#define RK_FEPHY_PHY_ID GRF_BIT(11)
++
++static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv,
++ unsigned int reg)
++{
++ reset_control_assert(priv->phy_reset);
++ usleep_range(20, 30);
++
++ regmap_write(priv->grf, reg,
++ RK_FEPHY_POWERUP |
++ RK_FEPHY_INTERNAL_RMII_SEL |
++ RK_FEPHY_24M_CLK_SEL |
++ RK_FEPHY_PHY_ID);
++ usleep_range(10000, 12000);
++
++ reset_control_deassert(priv->phy_reset);
++ usleep_range(50000, 60000);
++}
++
++static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv,
++ unsigned int reg)
++{
++ regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN);
++}
++
+ #define PX30_GRF_GMAC_CON1 0x0904
+
+ /* PX30_GRF_GMAC_CON1 */
+@@ -1179,12 +1208,24 @@ static void rk3528_set_clock_selection(s
+ }
+ }
+
++static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv)
++{
++ rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
++}
++
++static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv)
++{
++ rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0);
++}
++
+ static const struct rk_gmac_ops rk3528_ops = {
+ .set_to_rgmii = rk3528_set_to_rgmii,
+ .set_to_rmii = rk3528_set_to_rmii,
+ .set_rgmii_speed = rk3528_set_rgmii_speed,
+ .set_rmii_speed = rk3528_set_rmii_speed,
+ .set_clock_selection = rk3528_set_clock_selection,
++ .integrated_phy_powerup = rk3528_integrated_phy_powerup,
++ .integrated_phy_powerdown = rk3528_integrated_phy_powerdown,
+ .regs_valid = true,
+ .regs = {
+ 0xffbd0000, /* gmac0 */
--- /dev/null
+From 41f35564cb71e7043e0afcf30078b4a6145cab64 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 8 Mar 2025 21:37:15 +0000
+Subject: [PATCH] net: stmmac: dwmac-rk: Remove unneeded GRF and peripheral GRF
+ checks
+
+Now that GRF, and peripheral GRF where needed, is validated at probe
+time there is no longer any need to check and log an error in each SoC
+specific operation.
+
+Remove unneeded IS_ERR() checks and early bail out from each SoC
+specific operation.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://patch.msgid.link/20250308213720.2517944-4-jonas@kwiboo.se
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 249 ------------------
+ 1 file changed, 249 deletions(-)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+@@ -173,13 +173,6 @@ static void rk_gmac_integrated_fephy_pow
+
+ static void px30_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, PX30_GRF_GMAC_CON1,
+ PX30_GMAC_PHY_INTF_SEL_RMII);
+ }
+@@ -253,13 +246,6 @@ static const struct rk_gmac_ops px30_ops
+ static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
+ RK3128_GMAC_PHY_INTF_SEL_RGMII |
+ RK3128_GMAC_RMII_MODE_CLR);
+@@ -271,13 +257,6 @@ static void rk3128_set_to_rgmii(struct r
+
+ static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
+ RK3128_GMAC_PHY_INTF_SEL_RMII | RK3128_GMAC_RMII_MODE);
+ }
+@@ -286,11 +265,6 @@ static void rk3128_set_rgmii_speed(struc
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
+ RK3128_GMAC_CLK_2_5M);
+@@ -308,11 +282,6 @@ static void rk3128_set_rmii_speed(struct
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON1,
+ RK3128_GMAC_RMII_CLK_2_5M |
+@@ -369,13 +338,6 @@ static const struct rk_gmac_ops rk3128_o
+ static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+ RK3228_GMAC_PHY_INTF_SEL_RGMII |
+ RK3228_GMAC_RMII_MODE_CLR |
+@@ -388,13 +350,6 @@ static void rk3228_set_to_rgmii(struct r
+
+ static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+ RK3228_GMAC_PHY_INTF_SEL_RMII |
+ RK3228_GMAC_RMII_MODE);
+@@ -407,11 +362,6 @@ static void rk3228_set_rgmii_speed(struc
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+ RK3228_GMAC_CLK_2_5M);
+@@ -429,11 +379,6 @@ static void rk3228_set_rmii_speed(struct
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON1,
+ RK3228_GMAC_RMII_CLK_2_5M |
+@@ -494,13 +439,6 @@ static const struct rk_gmac_ops rk3228_o
+ static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
+ RK3288_GMAC_PHY_INTF_SEL_RGMII |
+ RK3288_GMAC_RMII_MODE_CLR);
+@@ -512,13 +450,6 @@ static void rk3288_set_to_rgmii(struct r
+
+ static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
+ RK3288_GMAC_PHY_INTF_SEL_RMII | RK3288_GMAC_RMII_MODE);
+ }
+@@ -527,11 +458,6 @@ static void rk3288_set_rgmii_speed(struc
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
+ RK3288_GMAC_CLK_2_5M);
+@@ -549,11 +475,6 @@ static void rk3288_set_rmii_speed(struct
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
+ RK3288_GMAC_RMII_CLK_2_5M |
+@@ -586,13 +507,6 @@ static const struct rk_gmac_ops rk3288_o
+
+ static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
+ RK3308_GMAC_PHY_INTF_SEL_RMII);
+ }
+@@ -601,11 +515,6 @@ static void rk3308_set_rmii_speed(struct
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3308_GRF_MAC_CON0,
+ RK3308_GMAC_SPEED_10M);
+@@ -658,13 +567,6 @@ static const struct rk_gmac_ops rk3308_o
+ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+ RK3328_GMAC_PHY_INTF_SEL_RGMII |
+ RK3328_GMAC_RMII_MODE_CLR |
+@@ -678,14 +580,8 @@ static void rk3328_set_to_rgmii(struct r
+
+ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int reg;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
+ RK3328_GRF_MAC_CON1;
+
+@@ -698,11 +594,6 @@ static void rk3328_set_rgmii_speed(struc
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+ RK3328_GMAC_CLK_2_5M);
+@@ -721,11 +612,6 @@ static void rk3328_set_rmii_speed(struct
+ struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int reg;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ reg = bsp_priv->integrated_phy ? RK3328_GRF_MAC_CON2 :
+ RK3328_GRF_MAC_CON1;
+
+@@ -789,13 +675,6 @@ static const struct rk_gmac_ops rk3328_o
+ static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+ RK3366_GMAC_PHY_INTF_SEL_RGMII |
+ RK3366_GMAC_RMII_MODE_CLR);
+@@ -807,13 +686,6 @@ static void rk3366_set_to_rgmii(struct r
+
+ static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+ RK3366_GMAC_PHY_INTF_SEL_RMII | RK3366_GMAC_RMII_MODE);
+ }
+@@ -822,11 +694,6 @@ static void rk3366_set_rgmii_speed(struc
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+ RK3366_GMAC_CLK_2_5M);
+@@ -844,11 +711,6 @@ static void rk3366_set_rmii_speed(struct
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON6,
+ RK3366_GMAC_RMII_CLK_2_5M |
+@@ -900,13 +762,6 @@ static const struct rk_gmac_ops rk3366_o
+ static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
+ RK3368_GMAC_PHY_INTF_SEL_RGMII |
+ RK3368_GMAC_RMII_MODE_CLR);
+@@ -918,13 +773,6 @@ static void rk3368_set_to_rgmii(struct r
+
+ static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
+ RK3368_GMAC_PHY_INTF_SEL_RMII | RK3368_GMAC_RMII_MODE);
+ }
+@@ -933,11 +781,6 @@ static void rk3368_set_rgmii_speed(struc
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
+ RK3368_GMAC_CLK_2_5M);
+@@ -955,11 +798,6 @@ static void rk3368_set_rmii_speed(struct
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON15,
+ RK3368_GMAC_RMII_CLK_2_5M |
+@@ -1011,13 +849,6 @@ static const struct rk_gmac_ops rk3368_o
+ static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
+ RK3399_GMAC_PHY_INTF_SEL_RGMII |
+ RK3399_GMAC_RMII_MODE_CLR);
+@@ -1029,13 +860,6 @@ static void rk3399_set_to_rgmii(struct r
+
+ static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
+ RK3399_GMAC_PHY_INTF_SEL_RMII | RK3399_GMAC_RMII_MODE);
+ }
+@@ -1044,11 +868,6 @@ static void rk3399_set_rgmii_speed(struc
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ if (speed == 10)
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
+ RK3399_GMAC_CLK_2_5M);
+@@ -1066,11 +885,6 @@ static void rk3399_set_rmii_speed(struct
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON5,
+ RK3399_GMAC_RMII_CLK_2_5M |
+@@ -1258,14 +1072,8 @@ static const struct rk_gmac_ops rk3528_o
+ static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+ u32 con0, con1;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ con0 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON0 :
+ RK3568_GRF_GMAC0_CON0;
+ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
+@@ -1283,14 +1091,8 @@ static void rk3568_set_to_rgmii(struct r
+
+ static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+ u32 con1;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ con1 = (bsp_priv->id == 1) ? RK3568_GRF_GMAC1_CON1 :
+ RK3568_GRF_GMAC0_CON1;
+ regmap_write(bsp_priv->grf, con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
+@@ -1377,14 +1179,8 @@ static const struct rk_gmac_ops rk3568_o
+ static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int offset_con;
+
+- if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
+- dev_err(dev, "Missing rockchip,grf or rockchip,php-grf property\n");
+- return;
+- }
+-
+ offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
+ RK3576_GRF_GMAC_CON0;
+
+@@ -1410,14 +1206,8 @@ static void rk3576_set_to_rgmii(struct r
+
+ static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int offset_con;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ offset_con = bsp_priv->id == 1 ? RK3576_GRF_GMAC_CON1 :
+ RK3576_GRF_GMAC_CON0;
+
+@@ -1537,14 +1327,8 @@ static const struct rk_gmac_ops rk3576_o
+ static void rk3588_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+ u32 offset_con, id = bsp_priv->id;
+
+- if (IS_ERR(bsp_priv->grf) || IS_ERR(bsp_priv->php_grf)) {
+- dev_err(dev, "Missing rockchip,grf or rockchip,php_grf property\n");
+- return;
+- }
+-
+ offset_con = bsp_priv->id == 1 ? RK3588_GRF_GMAC_CON9 :
+ RK3588_GRF_GMAC_CON8;
+
+@@ -1565,13 +1349,6 @@ static void rk3588_set_to_rgmii(struct r
+
+ static void rk3588_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->php_grf)) {
+- dev_err(dev, "%s: Missing rockchip,php_grf property\n", __func__);
+- return;
+- }
+-
+ regmap_write(bsp_priv->php_grf, RK3588_GRF_GMAC_CON0,
+ RK3588_GMAC_PHY_INTF_SEL_RMII(bsp_priv->id));
+
+@@ -1655,13 +1432,6 @@ static const struct rk_gmac_ops rk3588_o
+
+ static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
+ RV1108_GMAC_PHY_INTF_SEL_RMII);
+ }
+@@ -1670,11 +1440,6 @@ static void rv1108_set_rmii_speed(struct
+ {
+ struct device *dev = &bsp_priv->pdev->dev;
+
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ if (speed == 10) {
+ regmap_write(bsp_priv->grf, RV1108_GRF_GMAC_CON0,
+ RV1108_GMAC_RMII_CLK_2_5M |
+@@ -1723,13 +1488,6 @@ static const struct rk_gmac_ops rv1108_o
+ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
+ int tx_delay, int rx_delay)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "Missing rockchip,grf property\n");
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
+ RV1126_GMAC_PHY_INTF_SEL_RGMII |
+ RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
+@@ -1748,13 +1506,6 @@ static void rv1126_set_to_rgmii(struct r
+
+ static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
+ {
+- struct device *dev = &bsp_priv->pdev->dev;
+-
+- if (IS_ERR(bsp_priv->grf)) {
+- dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
+- return;
+- }
+-
+ regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
+ RV1126_GMAC_PHY_INTF_SEL_RMII);
+ }
--- /dev/null
+From 57b1ce9039665c6cb6907aee4b517f43e1557d2f Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Tue, 3 Sep 2024 11:22:38 -0400
+Subject: [PATCH] arm64: dts: rockchip: Add rk3576 SoC base DT
+
+This device tree contains all devices necessary for booting from network
+or SD Card.
+
+It supports CPU, CRU, PM domains, dma, interrupts, timers, UART, I2C
+and SDHCI (everything necessary to boot Linux on this system on chip)
+as well as Ethernet, SPI, GPU and RTC.
+
+Signed-off-by: Liang Chen <cl@rock-chips.com>
+Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
+Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
+Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+Tested-by: Liang Chen <cl@rock-chips.com>
+Link: https://lore.kernel.org/r/20240903152308.13565-9-detlev.casanova@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3576-pinctrl.dtsi | 5775 +++++++++++++++++
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1678 +++++
+ 2 files changed, 7453 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3576.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3576-pinctrl.dtsi
+@@ -0,0 +1,5775 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
++ */
++
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rockchip-pinconf.dtsi"
++
++/*
++ * This file is auto generated by pin2dts tool, please keep these code
++ * by adding changes at end of this file.
++ */
++&pinctrl {
++ aupll_clk {
++ /omit-if-no-ref/
++ aupll_clkm0_pins: aupll_clkm0-pins {
++ rockchip,pins =
++ /* aupll_clk_in_m0 */
++ <0 RK_PA0 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ aupll_clkm1_pins: aupll_clkm1-pins {
++ rockchip,pins =
++ /* aupll_clk_in_m1 */
++ <0 RK_PB0 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ aupll_clkm2_pins: aupll_clkm2-pins {
++ rockchip,pins =
++ /* aupll_clk_in_m2 */
++ <4 RK_PA2 3 &pcfg_pull_none>;
++ };
++ };
++
++ cam_clk0 {
++ /omit-if-no-ref/
++ cam_clk0m0_clk0: cam_clk0m0-clk0 {
++ rockchip,pins =
++ /* cam_clk0_out_m0 */
++ <3 RK_PD7 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ cam_clk0m1_clk0: cam_clk0m1-clk0 {
++ rockchip,pins =
++ /* cam_clk0_out_m1 */
++ <2 RK_PD2 1 &pcfg_pull_none>;
++ };
++ };
++
++ cam_clk1 {
++ /omit-if-no-ref/
++ cam_clk1m0_clk1: cam_clk1m0-clk1 {
++ rockchip,pins =
++ /* cam_clk1_out_m0 */
++ <4 RK_PA0 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ cam_clk1m1_clk1: cam_clk1m1-clk1 {
++ rockchip,pins =
++ /* cam_clk1_out_m1 */
++ <2 RK_PD6 1 &pcfg_pull_none>;
++ };
++ };
++
++ cam_clk2 {
++ /omit-if-no-ref/
++ cam_clk2m0_clk2: cam_clk2m0-clk2 {
++ rockchip,pins =
++ /* cam_clk2_out_m0 */
++ <4 RK_PA1 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ cam_clk2m1_clk2: cam_clk2m1-clk2 {
++ rockchip,pins =
++ /* cam_clk2_out_m1 */
++ <2 RK_PD7 1 &pcfg_pull_none>;
++ };
++ };
++
++ can0 {
++ /omit-if-no-ref/
++ can0m0_pins: can0m0-pins {
++ rockchip,pins =
++ /* can0_rx_m0 */
++ <2 RK_PA0 13 &pcfg_pull_none>,
++ /* can0_tx_m0 */
++ <2 RK_PA1 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ can0m1_pins: can0m1-pins {
++ rockchip,pins =
++ /* can0_rx_m1 */
++ <4 RK_PC3 12 &pcfg_pull_none>,
++ /* can0_tx_m1 */
++ <4 RK_PC2 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ can0m2_pins: can0m2-pins {
++ rockchip,pins =
++ /* can0_rx_m2 */
++ <4 RK_PA6 13 &pcfg_pull_none>,
++ /* can0_tx_m2 */
++ <4 RK_PA4 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ can0m3_pins: can0m3-pins {
++ rockchip,pins =
++ /* can0_rx_m3 */
++ <3 RK_PC1 12 &pcfg_pull_none>,
++ /* can0_tx_m3 */
++ <3 RK_PC4 12 &pcfg_pull_none>;
++ };
++ };
++
++ can1 {
++ /omit-if-no-ref/
++ can1m0_pins: can1m0-pins {
++ rockchip,pins =
++ /* can1_rx_m0 */
++ <2 RK_PA2 13 &pcfg_pull_none>,
++ /* can1_tx_m0 */
++ <2 RK_PA3 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ can1m1_pins: can1m1-pins {
++ rockchip,pins =
++ /* can1_rx_m1 */
++ <4 RK_PC7 13 &pcfg_pull_none>,
++ /* can1_tx_m1 */
++ <4 RK_PC6 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ can1m2_pins: can1m2-pins {
++ rockchip,pins =
++ /* can1_rx_m2 */
++ <4 RK_PB4 13 &pcfg_pull_none>,
++ /* can1_tx_m2 */
++ <4 RK_PB5 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ can1m3_pins: can1m3-pins {
++ rockchip,pins =
++ /* can1_rx_m3 */
++ <3 RK_PA3 11 &pcfg_pull_none>,
++ /* can1_tx_m3 */
++ <3 RK_PA2 11 &pcfg_pull_none>;
++ };
++ };
++
++ clk0_32k {
++ /omit-if-no-ref/
++ clk0_32k_pins: clk0_32k-pins {
++ rockchip,pins =
++ /* clk0_32k_out */
++ <0 RK_PA2 10 &pcfg_pull_none>;
++ };
++ };
++
++ clk1_32k {
++ /omit-if-no-ref/
++ clk1_32k_pins: clk1_32k-pins {
++ rockchip,pins =
++ /* clk1_32k_out */
++ <1 RK_PD5 13 &pcfg_pull_none>;
++ };
++ };
++
++ clk_32k {
++ /omit-if-no-ref/
++ clk_32k_pins: clk_32k-pins {
++ rockchip,pins =
++ /* clk_32k_in */
++ <0 RK_PA2 9 &pcfg_pull_none>;
++ };
++ };
++
++ cpubig {
++ /omit-if-no-ref/
++ cpubig_pins: cpubig-pins {
++ rockchip,pins =
++ /* cpubig_avs */
++ <0 RK_PD2 11 &pcfg_pull_none>;
++ };
++ };
++
++ cpulit {
++ /omit-if-no-ref/
++ cpulit_pins: cpulit-pins {
++ rockchip,pins =
++ /* cpulit_avs */
++ <0 RK_PC0 11 &pcfg_pull_none>;
++ };
++ };
++
++ debug0_test {
++ /omit-if-no-ref/
++ debug0_test_pins: debug0_test-pins {
++ rockchip,pins =
++ /* debug0_test_out */
++ <1 RK_PC4 7 &pcfg_pull_none>;
++ };
++ };
++
++ debug1_test {
++ /omit-if-no-ref/
++ debug1_test_pins: debug1_test-pins {
++ rockchip,pins =
++ /* debug1_test_out */
++ <1 RK_PC5 7 &pcfg_pull_none>;
++ };
++ };
++
++ debug2_test {
++ /omit-if-no-ref/
++ debug2_test_pins: debug2_test-pins {
++ rockchip,pins =
++ /* debug2_test_out */
++ <1 RK_PC6 7 &pcfg_pull_none>;
++ };
++ };
++
++ debug3_test {
++ /omit-if-no-ref/
++ debug3_test_pins: debug3_test-pins {
++ rockchip,pins =
++ /* debug3_test_out */
++ <1 RK_PC7 7 &pcfg_pull_none>;
++ };
++ };
++
++ debug4_test {
++ /omit-if-no-ref/
++ debug4_test_pins: debug4_test-pins {
++ rockchip,pins =
++ /* debug4_test_out */
++ <1 RK_PD0 7 &pcfg_pull_none>;
++ };
++ };
++
++ debug5_test {
++ /omit-if-no-ref/
++ debug5_test_pins: debug5_test-pins {
++ rockchip,pins =
++ /* debug5_test_out */
++ <1 RK_PD1 7 &pcfg_pull_none>;
++ };
++ };
++
++ debug6_test {
++ /omit-if-no-ref/
++ debug6_test_pins: debug6_test-pins {
++ rockchip,pins =
++ /* debug6_test_out */
++ <1 RK_PD2 7 &pcfg_pull_none>;
++ };
++ };
++
++ debug7_test {
++ /omit-if-no-ref/
++ debug7_test_pins: debug7_test-pins {
++ rockchip,pins =
++ /* debug7_test_out */
++ <1 RK_PD3 7 &pcfg_pull_none>;
++ };
++ };
++
++ dp {
++ /omit-if-no-ref/
++ dpm0_pins: dpm0-pins {
++ rockchip,pins =
++ /* dp_hpdin_m0 */
++ <4 RK_PC4 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ dpm1_pins: dpm1-pins {
++ rockchip,pins =
++ /* dp_hpdin_m1 */
++ <0 RK_PC5 9 &pcfg_pull_none>;
++ };
++ };
++
++ dsm_aud {
++ /omit-if-no-ref/
++ dsm_audm0_ln: dsm_audm0-ln {
++ rockchip,pins =
++ /* dsm_aud_ln_m0 */
++ <2 RK_PA1 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ dsm_audm0_lp: dsm_audm0-lp {
++ rockchip,pins =
++ /* dsm_aud_lp_m0 */
++ <2 RK_PA0 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ dsm_audm0_rn: dsm_audm0-rn {
++ rockchip,pins =
++ /* dsm_aud_rn_m0 */
++ <2 RK_PA3 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ dsm_audm0_rp: dsm_audm0-rp {
++ rockchip,pins =
++ /* dsm_aud_rp_m0 */
++ <2 RK_PA2 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ dsm_audm1_ln: dsm_audm1-ln {
++ rockchip,pins =
++ /* dsm_aud_ln_m1 */
++ <4 RK_PC1 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ dsm_audm1_lp: dsm_audm1-lp {
++ rockchip,pins =
++ /* dsm_aud_lp_m1 */
++ <4 RK_PC0 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ dsm_audm1_rn: dsm_audm1-rn {
++ rockchip,pins =
++ /* dsm_aud_rn_m1 */
++ <4 RK_PC3 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ dsm_audm1_rp: dsm_audm1-rp {
++ rockchip,pins =
++ /* dsm_aud_rp_m1 */
++ <4 RK_PC2 1 &pcfg_pull_none>;
++ };
++ };
++
++ dsmc {
++ /omit-if-no-ref/
++ dsmc_clkn: dsmc-clkn {
++ rockchip,pins =
++ /* dsmc_clkn */
++ <3 RK_PD6 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_clkp: dsmc-clkp {
++ rockchip,pins =
++ /* dsmc_clkp */
++ <3 RK_PD5 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_csn0: dsmc-csn0 {
++ rockchip,pins =
++ /* dsmc_csn0 */
++ <3 RK_PD3 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_csn1: dsmc-csn1 {
++ rockchip,pins =
++ /* dsmc_csn1 */
++ <3 RK_PB0 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_csn2: dsmc-csn2 {
++ rockchip,pins =
++ /* dsmc_csn2 */
++ <3 RK_PD1 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_csn3: dsmc-csn3 {
++ rockchip,pins =
++ /* dsmc_csn3 */
++ <3 RK_PD2 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data0: dsmc-data0 {
++ rockchip,pins =
++ /* dsmc_data0 */
++ <3 RK_PD4 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data1: dsmc-data1 {
++ rockchip,pins =
++ /* dsmc_data1 */
++ <3 RK_PD0 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data2: dsmc-data2 {
++ rockchip,pins =
++ /* dsmc_data2 */
++ <3 RK_PC7 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data3: dsmc-data3 {
++ rockchip,pins =
++ /* dsmc_data3 */
++ <3 RK_PC6 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data4: dsmc-data4 {
++ rockchip,pins =
++ /* dsmc_data4 */
++ <3 RK_PC5 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data5: dsmc-data5 {
++ rockchip,pins =
++ /* dsmc_data5 */
++ <3 RK_PC4 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data6: dsmc-data6 {
++ rockchip,pins =
++ /* dsmc_data6 */
++ <3 RK_PC1 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data7: dsmc-data7 {
++ rockchip,pins =
++ /* dsmc_data7 */
++ <3 RK_PC0 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data8: dsmc-data8 {
++ rockchip,pins =
++ /* dsmc_data8 */
++ <3 RK_PB5 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data9: dsmc-data9 {
++ rockchip,pins =
++ /* dsmc_data9 */
++ <3 RK_PB4 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data10: dsmc-data10 {
++ rockchip,pins =
++ /* dsmc_data10 */
++ <3 RK_PB3 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data11: dsmc-data11 {
++ rockchip,pins =
++ /* dsmc_data11 */
++ <3 RK_PB2 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data12: dsmc-data12 {
++ rockchip,pins =
++ /* dsmc_data12 */
++ <3 RK_PB1 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data13: dsmc-data13 {
++ rockchip,pins =
++ /* dsmc_data13 */
++ <3 RK_PA7 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data14: dsmc-data14 {
++ rockchip,pins =
++ /* dsmc_data14 */
++ <3 RK_PA6 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_data15: dsmc-data15 {
++ rockchip,pins =
++ /* dsmc_data15 */
++ <3 RK_PA5 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_dqs0: dsmc-dqs0 {
++ rockchip,pins =
++ /* dsmc_dqs0 */
++ <3 RK_PB7 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_dqs1: dsmc-dqs1 {
++ rockchip,pins =
++ /* dsmc_dqs1 */
++ <3 RK_PB6 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_int0: dsmc-int0 {
++ rockchip,pins =
++ /* dsmc_int0 */
++ <4 RK_PA0 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_int1: dsmc-int1 {
++ rockchip,pins =
++ /* dsmc_int1 */
++ <3 RK_PC2 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_int2: dsmc-int2 {
++ rockchip,pins =
++ /* dsmc_int2 */
++ <4 RK_PA1 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_int3: dsmc-int3 {
++ rockchip,pins =
++ /* dsmc_int3 */
++ <3 RK_PC3 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_rdyn: dsmc-rdyn {
++ rockchip,pins =
++ /* dsmc_rdyn */
++ <3 RK_PA4 5 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ dsmc_resetn: dsmc-resetn {
++ rockchip,pins =
++ /* dsmc_resetn */
++ <3 RK_PD7 5 &pcfg_pull_none>;
++ };
++ };
++
++ dsmc_testclk {
++ /omit-if-no-ref/
++ dsmc_testclk_out: dsmc-testclk-out {
++ rockchip,pins =
++ /* dsmc_testclk_out */
++ <3 RK_PC2 7 &pcfg_pull_none>;
++ };
++ };
++
++ dsmc_testdata {
++ /omit-if-no-ref/
++ dsmc_testdata_out: dsmc-testdata-out {
++ rockchip,pins =
++ /* dsmc_testdata_out */
++ <3 RK_PC3 7 &pcfg_pull_none>;
++ };
++ };
++
++ edp_tx {
++ /omit-if-no-ref/
++ edp_txm0_pins: edp_txm0-pins {
++ rockchip,pins =
++ /* edp_tx_hpdin_m0 */
++ <4 RK_PC1 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ edp_txm1_pins: edp_txm1-pins {
++ rockchip,pins =
++ /* edp_tx_hpdin_m1 */
++ <0 RK_PB6 10 &pcfg_pull_none>;
++ };
++ };
++
++ emmc {
++ /omit-if-no-ref/
++ emmc_rstnout: emmc-rstnout {
++ rockchip,pins =
++ /* emmc_rstn */
++ <1 RK_PB3 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ emmc_bus8: emmc-bus8 {
++ rockchip,pins =
++ /* emmc_d0 */
++ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d1 */
++ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d2 */
++ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d3 */
++ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d4 */
++ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d5 */
++ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d6 */
++ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d7 */
++ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ emmc_clk: emmc-clk {
++ rockchip,pins =
++ /* emmc_clk */
++ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ emmc_cmd: emmc-cmd {
++ rockchip,pins =
++ /* emmc_cmd */
++ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ emmc_strb: emmc-strb {
++ rockchip,pins =
++ /* emmc_strb */
++ <1 RK_PB2 1 &pcfg_pull_none>;
++ };
++ };
++
++ emmc_testclk {
++ /omit-if-no-ref/
++ emmc_testclk_test: emmc_testclk-test {
++ rockchip,pins =
++ /* emmc_testclk_out */
++ <1 RK_PB3 6 &pcfg_pull_none>;
++ };
++ };
++
++ emmc_testdata {
++ /omit-if-no-ref/
++ emmc_testdata_test: emmc_testdata-test {
++ rockchip,pins =
++ /* emmc_testdata_out */
++ <1 RK_PB7 5 &pcfg_pull_none>;
++ };
++ };
++
++ eth0 {
++ /omit-if-no-ref/
++ eth0m0_miim: eth0m0-miim {
++ rockchip,pins =
++ /* eth0_mdc_m0 */
++ <3 RK_PA6 3 &pcfg_pull_none>,
++ /* eth0_mdio_m0 */
++ <3 RK_PA5 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m0_rx_bus2: eth0m0-rx_bus2 {
++ rockchip,pins =
++ /* eth0_rxctl_m0 */
++ <3 RK_PA7 3 &pcfg_pull_none>,
++ /* eth0_rxd0_m0 */
++ <3 RK_PB2 3 &pcfg_pull_none>,
++ /* eth0_rxd1_m0 */
++ <3 RK_PB1 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m0_tx_bus2: eth0m0-tx_bus2 {
++ rockchip,pins =
++ /* eth0_txctl_m0 */
++ <3 RK_PB3 3 &pcfg_pull_none>,
++ /* eth0_txd0_m0 */
++ <3 RK_PB5 3 &pcfg_pull_none>,
++ /* eth0_txd1_m0 */
++ <3 RK_PB4 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m0_rgmii_clk: eth0m0-rgmii_clk {
++ rockchip,pins =
++ /* eth0_rxclk_m0 */
++ <3 RK_PD1 3 &pcfg_pull_none>,
++ /* eth0_txclk_m0 */
++ <3 RK_PB6 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m0_rgmii_bus: eth0m0-rgmii_bus {
++ rockchip,pins =
++ /* eth0_rxd2_m0 */
++ <3 RK_PD3 3 &pcfg_pull_none>,
++ /* eth0_rxd3_m0 */
++ <3 RK_PD2 3 &pcfg_pull_none>,
++ /* eth0_txd2_m0 */
++ <3 RK_PC3 3 &pcfg_pull_none>,
++ /* eth0_txd3_m0 */
++ <3 RK_PC2 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m0_mclk: eth0m0-mclk {
++ rockchip,pins =
++ /* eth0m0_mclk */
++ <3 RK_PB0 3 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ eth0m0_ppsclk: eth0m0-ppsclk {
++ rockchip,pins =
++ /* eth0m0_ppsclk */
++ <3 RK_PC0 3 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ eth0m0_ppstrig: eth0m0-ppstrig {
++ rockchip,pins =
++ /* eth0m0_ppstrig */
++ <3 RK_PB7 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m1_miim: eth0m1-miim {
++ rockchip,pins =
++ /* eth0_mdc_m1 */
++ <3 RK_PA1 3 &pcfg_pull_none>,
++ /* eth0_mdio_m1 */
++ <3 RK_PA0 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m1_rx_bus2: eth0m1-rx_bus2 {
++ rockchip,pins =
++ /* eth0_rxctl_m1 */
++ <3 RK_PA2 3 &pcfg_pull_none>,
++ /* eth0_rxd0_m1 */
++ <2 RK_PA6 3 &pcfg_pull_none>,
++ /* eth0_rxd1_m1 */
++ <3 RK_PA3 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m1_tx_bus2: eth0m1-tx_bus2 {
++ rockchip,pins =
++ /* eth0_txctl_m1 */
++ <2 RK_PA7 3 &pcfg_pull_none>,
++ /* eth0_txd0_m1 */
++ <2 RK_PB1 3 &pcfg_pull_none>,
++ /* eth0_txd1_m1 */
++ <2 RK_PB0 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m1_rgmii_clk: eth0m1-rgmii_clk {
++ rockchip,pins =
++ /* eth0_rxclk_m1 */
++ <2 RK_PB5 3 &pcfg_pull_none>,
++ /* eth0_txclk_m1 */
++ <2 RK_PB3 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m1_rgmii_bus: eth0m1-rgmii_bus {
++ rockchip,pins =
++ /* eth0_rxd2_m1 */
++ <2 RK_PB7 3 &pcfg_pull_none>,
++ /* eth0_rxd3_m1 */
++ <2 RK_PB6 3 &pcfg_pull_none>,
++ /* eth0_txd2_m1 */
++ <2 RK_PB4 3 &pcfg_pull_none>,
++ /* eth0_txd3_m1 */
++ <2 RK_PB2 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m1_mclk: eth0m1-mclk {
++ rockchip,pins =
++ /* eth0m1_mclk */
++ <2 RK_PD6 3 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ eth0m1_ppsclk: eth0m1-ppsclk {
++ rockchip,pins =
++ /* eth0m1_ppsclk */
++ <2 RK_PC1 3 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ eth0m1_ppstrig: eth0m1-ppstrig {
++ rockchip,pins =
++ /* eth0m1_ppstrig */
++ <2 RK_PC2 3 &pcfg_pull_none>;
++ };
++ };
++
++ eth1 {
++ /omit-if-no-ref/
++ eth1m0_miim: eth1m0-miim {
++ rockchip,pins =
++ /* eth1_mdc_m0 */
++ <2 RK_PD4 2 &pcfg_pull_none>,
++ /* eth1_mdio_m0 */
++ <2 RK_PD5 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m0_rx_bus2: eth1m0-rx_bus2 {
++ rockchip,pins =
++ /* eth1_rxctl_m0 */
++ <2 RK_PD3 2 &pcfg_pull_none>,
++ /* eth1_rxd0_m0 */
++ <2 RK_PD1 2 &pcfg_pull_none>,
++ /* eth1_rxd1_m0 */
++ <2 RK_PD2 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m0_tx_bus2: eth1m0-tx_bus2 {
++ rockchip,pins =
++ /* eth1_txctl_m0 */
++ <2 RK_PD0 2 &pcfg_pull_none>,
++ /* eth1_txd0_m0 */
++ <2 RK_PC6 2 &pcfg_pull_none>,
++ /* eth1_txd1_m0 */
++ <2 RK_PC7 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m0_rgmii_clk: eth1m0-rgmii_clk {
++ rockchip,pins =
++ /* eth1_rxclk_m0 */
++ <2 RK_PC2 2 &pcfg_pull_none>,
++ /* eth1_txclk_m0 */
++ <2 RK_PC5 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m0_rgmii_bus: eth1m0-rgmii_bus {
++ rockchip,pins =
++ /* eth1_rxd2_m0 */
++ <2 RK_PC0 2 &pcfg_pull_none>,
++ /* eth1_rxd3_m0 */
++ <2 RK_PC1 2 &pcfg_pull_none>,
++ /* eth1_txd2_m0 */
++ <2 RK_PC3 2 &pcfg_pull_none>,
++ /* eth1_txd3_m0 */
++ <2 RK_PC4 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m0_mclk: eth1m0-mclk {
++ rockchip,pins =
++ /* eth1m0_mclk */
++ <2 RK_PD7 2 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ eth1m0_ppsclk: eth1m0-ppsclk {
++ rockchip,pins =
++ /* eth1m0_ppsclk */
++ <3 RK_PA2 2 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ eth1m0_ppstrig: eth1m0-ppstrig {
++ rockchip,pins =
++ /* eth1m0_ppstrig */
++ <3 RK_PA1 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m1_miim: eth1m1-miim {
++ rockchip,pins =
++ /* eth1_mdc_m1 */
++ <1 RK_PD2 1 &pcfg_pull_none>,
++ /* eth1_mdio_m1 */
++ <1 RK_PD3 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m1_rx_bus2: eth1m1-rx_bus2 {
++ rockchip,pins =
++ /* eth1_rxctl_m1 */
++ <1 RK_PD1 1 &pcfg_pull_none>,
++ /* eth1_rxd0_m1 */
++ <1 RK_PC7 1 &pcfg_pull_none>,
++ /* eth1_rxd1_m1 */
++ <1 RK_PD0 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m1_tx_bus2: eth1m1-tx_bus2 {
++ rockchip,pins =
++ /* eth1_txctl_m1 */
++ <1 RK_PC6 1 &pcfg_pull_none>,
++ /* eth1_txd0_m1 */
++ <1 RK_PC4 1 &pcfg_pull_none>,
++ /* eth1_txd1_m1 */
++ <1 RK_PC5 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m1_rgmii_clk: eth1m1-rgmii_clk {
++ rockchip,pins =
++ /* eth1_rxclk_m1 */
++ <1 RK_PB6 1 &pcfg_pull_none>,
++ /* eth1_txclk_m1 */
++ <1 RK_PC1 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m1_rgmii_bus: eth1m1-rgmii_bus {
++ rockchip,pins =
++ /* eth1_rxd2_m1 */
++ <1 RK_PB4 1 &pcfg_pull_none>,
++ /* eth1_rxd3_m1 */
++ <1 RK_PB5 1 &pcfg_pull_none>,
++ /* eth1_txd2_m1 */
++ <1 RK_PB7 1 &pcfg_pull_none>,
++ /* eth1_txd3_m1 */
++ <1 RK_PC0 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m1_mclk: eth1m1-mclk {
++ rockchip,pins =
++ /* eth1m1_mclk */
++ <1 RK_PD4 1 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ eth1m1_ppsclk: eth1m1-ppsclk {
++ rockchip,pins =
++ /* eth1m1_ppsclk */
++ <1 RK_PC2 1 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ eth1m1_ppstrig: eth1m1-ppstrig {
++ rockchip,pins =
++ /* eth1m1_ppstrig */
++ <1 RK_PC3 1 &pcfg_pull_none>;
++ };
++ };
++
++ eth0_ptp {
++ /omit-if-no-ref/
++ eth0m0_ptp_refclk: eth0m0-ptp-refclk {
++ rockchip,pins =
++ /* eth0m0_ptp_refclk */
++ <3 RK_PC1 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0m1_ptp_refclk: eth0m1-ptp-refclk {
++ rockchip,pins =
++ /* eth0m1_ptp_refclk */
++ <2 RK_PC0 3 &pcfg_pull_none>;
++ };
++ };
++
++ eth0_testrxclk {
++ /omit-if-no-ref/
++ eth0_testrxclkm0_test: eth0_testrxclkm0-test {
++ rockchip,pins =
++ /* eth0_testrxclk_out_m0 */
++ <3 RK_PC7 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0_testrxclkm1_test: eth0_testrxclkm1-test {
++ rockchip,pins =
++ /* eth0_testrxclk_out_m1 */
++ <2 RK_PC5 6 &pcfg_pull_none>;
++ };
++ };
++
++ eth0_testrxd {
++ /omit-if-no-ref/
++ eth0_testrxdm0_test: eth0_testrxdm0-test {
++ rockchip,pins =
++ /* eth0_testrxd_out_m0 */
++ <3 RK_PD0 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth0_testrxdm1_test: eth0_testrxdm1-test {
++ rockchip,pins =
++ /* eth0_testrxd_out_m1 */
++ <2 RK_PC4 6 &pcfg_pull_none>;
++ };
++ };
++
++ eth1_ptp {
++ /omit-if-no-ref/
++ eth1m0_ptp_refclk: eth1m0-ptp-refclk {
++ rockchip,pins =
++ /* eth1m0_ptp_refclk */
++ <3 RK_PA3 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1m1_ptp_refclk: eth1m1-ptp-refclk {
++ rockchip,pins =
++ /* eth1m1_ptp_refclk */
++ <2 RK_PB6 2 &pcfg_pull_none>;
++ };
++ };
++
++ eth1_testrxclk {
++ /omit-if-no-ref/
++ eth1_testrxclkm0_test: eth1_testrxclkm0-test {
++ rockchip,pins =
++ /* eth1_testrxclk_out_m0 */
++ <3 RK_PA1 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1_testrxclkm1_test: eth1_testrxclkm1-test {
++ rockchip,pins =
++ /* eth1_testrxclk_out_m1 */
++ <1 RK_PC3 6 &pcfg_pull_none>;
++ };
++ };
++
++ eth1_testrxd {
++ /omit-if-no-ref/
++ eth1_testrxdm0_test: eth1_testrxdm0-test {
++ rockchip,pins =
++ /* eth1_testrxd_out_m0 */
++ <3 RK_PA0 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ eth1_testrxdm1_test: eth1_testrxdm1-test {
++ rockchip,pins =
++ /* eth1_testrxd_out_m1 */
++ <1 RK_PC2 6 &pcfg_pull_none>;
++ };
++ };
++
++ eth_clk0_25m {
++ /omit-if-no-ref/
++ ethm0_clk0_25m_out: ethm0-clk0-25m-out {
++ rockchip,pins =
++ /* ethm0_clk0_25m_out */
++ <3 RK_PA4 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ ethm1_clk0_25m_out: ethm1-clk0-25m-out {
++ rockchip,pins =
++ /* ethm1_clk0_25m_out */
++ <2 RK_PD7 3 &pcfg_pull_none>;
++ };
++ };
++
++ eth_clk1_25m {
++ /omit-if-no-ref/
++ ethm0_clk1_25m_out: ethm0-clk1-25m-out {
++ rockchip,pins =
++ /* ethm0_clk1_25m_out */
++ <2 RK_PD6 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ ethm1_clk1_25m_out: ethm1-clk1-25m-out {
++ rockchip,pins =
++ /* ethm1_clk1_25m_out */
++ <1 RK_PD5 1 &pcfg_pull_none>;
++ };
++ };
++
++ flexbus0 {
++ /omit-if-no-ref/
++ flexbus0m0_csn: flexbus0m0-csn {
++ rockchip,pins =
++ /* flexbus0_csn_m0 */
++ <3 RK_PA4 8 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0m0_d13: flexbus0m0-d13 {
++ rockchip,pins =
++ /* flexbus0_d13_m0 */
++ <4 RK_PA0 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0m0_d14: flexbus0m0-d14 {
++ rockchip,pins =
++ /* flexbus0_d14_m0 */
++ <4 RK_PA1 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0m0_d15: flexbus0m0-d15 {
++ rockchip,pins =
++ /* flexbus0_d15_m0 */
++ <3 RK_PD7 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0m1_csn: flexbus0m1-csn {
++ rockchip,pins =
++ /* flexbus0_csn_m1 */
++ <4 RK_PA1 8 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0m1_d13: flexbus0m1-d13 {
++ rockchip,pins =
++ /* flexbus0_d13_m1 */
++ <4 RK_PA4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0m1_d14: flexbus0m1-d14 {
++ rockchip,pins =
++ /* flexbus0_d14_m1 */
++ <4 RK_PA6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0m1_d15: flexbus0m1-d15 {
++ rockchip,pins =
++ /* flexbus0_d15_m1 */
++ <4 RK_PB5 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0m2_csn: flexbus0m2-csn {
++ rockchip,pins =
++ /* flexbus0_csn_m2 */
++ <3 RK_PC3 8 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0m3_csn: flexbus0m3-csn {
++ rockchip,pins =
++ /* flexbus0_csn_m3 */
++ <3 RK_PD2 8 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0m4_csn: flexbus0m4-csn {
++ rockchip,pins =
++ /* flexbus0_csn_m4 */
++ <4 RK_PB4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_clk: flexbus0-clk {
++ rockchip,pins =
++ /* flexbus0_clk */
++ <3 RK_PB6 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d10: flexbus0-d10 {
++ rockchip,pins =
++ /* flexbus0_d10 */
++ <3 RK_PC3 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d11: flexbus0-d11 {
++ rockchip,pins =
++ /* flexbus0_d11 */
++ <3 RK_PD1 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d12: flexbus0-d12 {
++ rockchip,pins =
++ /* flexbus0_d12 */
++ <3 RK_PD2 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d0: flexbus0-d0 {
++ rockchip,pins =
++ /* flexbus0_d0 */
++ <3 RK_PB5 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d1: flexbus0-d1 {
++ rockchip,pins =
++ /* flexbus0_d1 */
++ <3 RK_PB4 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d2: flexbus0-d2 {
++ rockchip,pins =
++ /* flexbus0_d2 */
++ <3 RK_PB3 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d3: flexbus0-d3 {
++ rockchip,pins =
++ /* flexbus0_d3 */
++ <3 RK_PB2 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d4: flexbus0-d4 {
++ rockchip,pins =
++ /* flexbus0_d4 */
++ <3 RK_PB1 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d5: flexbus0-d5 {
++ rockchip,pins =
++ /* flexbus0_d5 */
++ <3 RK_PA7 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d6: flexbus0-d6 {
++ rockchip,pins =
++ /* flexbus0_d6 */
++ <3 RK_PA6 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d7: flexbus0-d7 {
++ rockchip,pins =
++ /* flexbus0_d7 */
++ <3 RK_PA5 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d8: flexbus0-d8 {
++ rockchip,pins =
++ /* flexbus0_d8 */
++ <3 RK_PB0 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus0_d9: flexbus0-d9 {
++ rockchip,pins =
++ /* flexbus0_d9 */
++ <3 RK_PC2 6 &pcfg_pull_none>;
++ };
++ };
++
++ flexbus1 {
++ /omit-if-no-ref/
++ flexbus1m0_csn: flexbus1m0-csn {
++ rockchip,pins =
++ /* flexbus1_csn_m0 */
++ <3 RK_PB7 8 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m0_d12: flexbus1m0-d12 {
++ rockchip,pins =
++ /* flexbus1_d12_m0 */
++ <3 RK_PD7 7 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m0_d13: flexbus1m0-d13 {
++ rockchip,pins =
++ /* flexbus1_d13_m0 */
++ <4 RK_PA1 7 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m0_d14: flexbus1m0-d14 {
++ rockchip,pins =
++ /* flexbus1_d14_m0 */
++ <4 RK_PA0 7 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m0_d15: flexbus1m0-d15 {
++ rockchip,pins =
++ /* flexbus1_d15_m0 */
++ <3 RK_PD2 7 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m1_csn: flexbus1m1-csn {
++ rockchip,pins =
++ /* flexbus1_csn_m1 */
++ <3 RK_PD7 8 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m1_d12: flexbus1m1-d12 {
++ rockchip,pins =
++ /* flexbus1_d12_m1 */
++ <4 RK_PA5 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m1_d13: flexbus1m1-d13 {
++ rockchip,pins =
++ /* flexbus1_d13_m1 */
++ <4 RK_PB0 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m1_d14: flexbus1m1-d14 {
++ rockchip,pins =
++ /* flexbus1_d14_m1 */
++ <4 RK_PB1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m1_d15: flexbus1m1-d15 {
++ rockchip,pins =
++ /* flexbus1_d15_m1 */
++ <4 RK_PB2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m2_csn: flexbus1m2-csn {
++ rockchip,pins =
++ /* flexbus1_csn_m2 */
++ <3 RK_PD1 8 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m3_csn: flexbus1m3-csn {
++ rockchip,pins =
++ /* flexbus1_csn_m3 */
++ <4 RK_PA0 8 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1m4_csn: flexbus1m4-csn {
++ rockchip,pins =
++ /* flexbus1_csn_m4 */
++ <4 RK_PA3 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_clk: flexbus1-clk {
++ rockchip,pins =
++ /* flexbus1_clk */
++ <3 RK_PD6 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d10: flexbus1-d10 {
++ rockchip,pins =
++ /* flexbus1_d10 */
++ <3 RK_PB7 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d11: flexbus1-d11 {
++ rockchip,pins =
++ /* flexbus1_d11 */
++ <3 RK_PA4 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d0: flexbus1-d0 {
++ rockchip,pins =
++ /* flexbus1_d0 */
++ <3 RK_PD5 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d1: flexbus1-d1 {
++ rockchip,pins =
++ /* flexbus1_d1 */
++ <3 RK_PD4 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d2: flexbus1-d2 {
++ rockchip,pins =
++ /* flexbus1_d2 */
++ <3 RK_PD3 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d3: flexbus1-d3 {
++ rockchip,pins =
++ /* flexbus1_d3 */
++ <3 RK_PD0 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d4: flexbus1-d4 {
++ rockchip,pins =
++ /* flexbus1_d4 */
++ <3 RK_PC7 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d5: flexbus1-d5 {
++ rockchip,pins =
++ /* flexbus1_d5 */
++ <3 RK_PC6 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d6: flexbus1-d6 {
++ rockchip,pins =
++ /* flexbus1_d6 */
++ <3 RK_PC5 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d7: flexbus1-d7 {
++ rockchip,pins =
++ /* flexbus1_d7 */
++ <3 RK_PC4 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d8: flexbus1-d8 {
++ rockchip,pins =
++ /* flexbus1_d8 */
++ <3 RK_PC1 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ flexbus1_d9: flexbus1-d9 {
++ rockchip,pins =
++ /* flexbus1_d9 */
++ <3 RK_PC0 6 &pcfg_pull_none>;
++ };
++ };
++
++ flexbus0_testclk {
++ /omit-if-no-ref/
++ flexbus0_testclk_testclk: flexbus0_testclk-testclk {
++ rockchip,pins =
++ /* flexbus0_testclk_out */
++ <2 RK_PA3 6 &pcfg_pull_none>;
++ };
++ };
++
++ flexbus0_testdata {
++ /omit-if-no-ref/
++ flexbus0_testdata_testdata: flexbus0_testdata-testdata {
++ rockchip,pins =
++ /* flexbus0_testdata_out */
++ <2 RK_PA2 6 &pcfg_pull_none>;
++ };
++ };
++
++ flexbus1_testclk {
++ /omit-if-no-ref/
++ flexbus1_testclk_testclk: flexbus1_testclk-testclk {
++ rockchip,pins =
++ /* flexbus1_testclk_out */
++ <2 RK_PA5 6 &pcfg_pull_none>;
++ };
++ };
++
++ flexbus1_testdata {
++ /omit-if-no-ref/
++ flexbus1_testdata_testdata: flexbus1_testdata-testdata {
++ rockchip,pins =
++ /* flexbus1_testdata_out */
++ <2 RK_PA4 6 &pcfg_pull_none>;
++ };
++ };
++
++ fspi0 {
++ /omit-if-no-ref/
++ fspi0_pins: fspi0-pins {
++ rockchip,pins =
++ /* fspi0_clk */
++ <1 RK_PB1 2 &pcfg_pull_none>,
++ /* fspi0_d0 */
++ <1 RK_PA0 2 &pcfg_pull_none>,
++ /* fspi0_d1 */
++ <1 RK_PA1 2 &pcfg_pull_none>,
++ /* fspi0_d2 */
++ <1 RK_PA2 2 &pcfg_pull_none>,
++ /* fspi0_d3 */
++ <1 RK_PA3 2 &pcfg_pull_none>,
++ /* fspi0_d4 */
++ <1 RK_PA4 2 &pcfg_pull_none>,
++ /* fspi0_d5 */
++ <1 RK_PA5 2 &pcfg_pull_none>,
++ /* fspi0_d6 */
++ <1 RK_PA6 2 &pcfg_pull_none>,
++ /* fspi0_d7 */
++ <1 RK_PA7 2 &pcfg_pull_none>,
++ /* fspi0_dqs */
++ <1 RK_PB2 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ fspi0_csn0: fspi0-csn0 {
++ rockchip,pins =
++ /* fspi0_csn0 */
++ <1 RK_PB3 2 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ fspi0_csn1: fspi0-csn1 {
++ rockchip,pins =
++ /* fspi0_csn1 */
++ <1 RK_PB0 2 &pcfg_pull_none>;
++ };
++ };
++
++ fspi1 {
++ /omit-if-no-ref/
++ fspi1m0_pins: fspi1m0-pins {
++ rockchip,pins =
++ /* fspi1_clk_m0 */
++ <2 RK_PA5 2 &pcfg_pull_none>,
++ /* fspi1_d0_m0 */
++ <2 RK_PA0 2 &pcfg_pull_none>,
++ /* fspi1_d1_m0 */
++ <2 RK_PA1 2 &pcfg_pull_none>,
++ /* fspi1_d2_m0 */
++ <2 RK_PA2 2 &pcfg_pull_none>,
++ /* fspi1_d3_m0 */
++ <2 RK_PA3 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ fspi1m0_csn0: fspi1m0-csn0 {
++ rockchip,pins =
++ /* fspi1m0_csn0 */
++ <2 RK_PA4 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ fspi1m1_pins: fspi1m1-pins {
++ rockchip,pins =
++ /* fspi1_clk_m1 */
++ <1 RK_PD5 3 &pcfg_pull_none>,
++ /* fspi1_d0_m1 */
++ <1 RK_PC4 3 &pcfg_pull_none>,
++ /* fspi1_d1_m1 */
++ <1 RK_PC5 3 &pcfg_pull_none>,
++ /* fspi1_d2_m1 */
++ <1 RK_PC6 3 &pcfg_pull_none>,
++ /* fspi1_d3_m1 */
++ <1 RK_PC7 3 &pcfg_pull_none>,
++ /* fspi1_d4_m1 */
++ <1 RK_PD0 3 &pcfg_pull_none>,
++ /* fspi1_d5_m1 */
++ <1 RK_PD1 3 &pcfg_pull_none>,
++ /* fspi1_d6_m1 */
++ <1 RK_PD2 3 &pcfg_pull_none>,
++ /* fspi1_d7_m1 */
++ <1 RK_PD3 3 &pcfg_pull_none>,
++ /* fspi1_dqs_m1 */
++ <1 RK_PD4 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ fspi1m1_csn0: fspi1m1-csn0 {
++ rockchip,pins =
++ /* fspi1m1_csn0 */
++ <1 RK_PC3 3 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ fspi1m1_csn1: fspi1m1-csn1 {
++ rockchip,pins =
++ /* fspi1m1_csn1 */
++ <1 RK_PC2 3 &pcfg_pull_none>;
++ };
++ };
++
++ fspi0_testclk {
++ /omit-if-no-ref/
++ fspi0_testclk_test: fspi0_testclk-test {
++ rockchip,pins =
++ /* fspi0_testclk_out */
++ <1 RK_PB0 6 &pcfg_pull_none>;
++ };
++ };
++
++ fspi0_testdata {
++ /omit-if-no-ref/
++ fspi0_testdata_test: fspi0_testdata-test {
++ rockchip,pins =
++ /* fspi0_testdata_out */
++ <1 RK_PB7 6 &pcfg_pull_none>;
++ };
++ };
++
++ fspi1_testclk {
++ /omit-if-no-ref/
++ fspi1_testclkm1_test: fspi1_testclkm1-test {
++ rockchip,pins =
++ /* fspi1_testclk_out_m1 */
++ <1 RK_PC1 7 &pcfg_pull_none>;
++ };
++ };
++
++ fspi1_testdata {
++ /omit-if-no-ref/
++ fspi1_testdatam1_test: fspi1_testdatam1-test {
++ rockchip,pins =
++ /* fspi1_testdata_out_m1 */
++ <1 RK_PB7 7 &pcfg_pull_none>;
++ };
++ };
++
++ gpu {
++ /omit-if-no-ref/
++ gpu_pins: gpu-pins {
++ rockchip,pins =
++ /* gpu_avs */
++ <0 RK_PD3 11 &pcfg_pull_none>;
++ };
++ };
++
++ hdmi_tx {
++ /omit-if-no-ref/
++ hdmi_txm0_pins: hdmi_txm0-pins {
++ rockchip,pins =
++ /* hdmi_tx_cec_m0 */
++ <4 RK_PC0 9 &pcfg_pull_none>,
++ /* hdmi_tx_hpdin_m0 */
++ <4 RK_PC1 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ hdmi_txm1_pins: hdmi_txm1-pins {
++ rockchip,pins =
++ /* hdmi_tx_cec_m1 */
++ <0 RK_PC3 9 &pcfg_pull_none>,
++ /* hdmi_tx_hpdin_m1 */
++ <0 RK_PB6 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ hdmi_tx_scl: hdmi-tx-scl {
++ rockchip,pins =
++ /* hdmi_tx_scl */
++ <4 RK_PC2 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ hdmi_tx_sda: hdmi-tx-sda {
++ rockchip,pins =
++ /* hdmi_tx_sda */
++ <4 RK_PC3 9 &pcfg_pull_none>;
++ };
++ };
++
++ i2c0 {
++ /omit-if-no-ref/
++ i2c0m0_xfer: i2c0m0-xfer {
++ rockchip,pins =
++ /* i2c0_scl_m0 */
++ <0 RK_PB0 11 &pcfg_pull_none_smt>,
++ /* i2c0_sda_m0 */
++ <0 RK_PB1 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c0m1_xfer: i2c0m1-xfer {
++ rockchip,pins =
++ /* i2c0_scl_m1 */
++ <0 RK_PC1 9 &pcfg_pull_none_smt>,
++ /* i2c0_sda_m1 */
++ <0 RK_PC2 9 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c1 {
++ /omit-if-no-ref/
++ i2c1m0_xfer: i2c1m0-xfer {
++ rockchip,pins =
++ /* i2c1_scl_m0 */
++ <0 RK_PB2 11 &pcfg_pull_none_smt>,
++ /* i2c1_sda_m0 */
++ <0 RK_PB3 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c1m1_xfer: i2c1m1-xfer {
++ rockchip,pins =
++ /* i2c1_scl_m1 */
++ <0 RK_PB4 9 &pcfg_pull_none_smt>,
++ /* i2c1_sda_m1 */
++ <0 RK_PB5 9 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c2 {
++ /omit-if-no-ref/
++ i2c2m0_xfer: i2c2m0-xfer {
++ rockchip,pins =
++ /* i2c2_scl_m0 */
++ <0 RK_PB7 9 &pcfg_pull_none_smt>,
++ /* i2c2_sda_m0 */
++ <0 RK_PC0 9 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c2m1_xfer: i2c2m1-xfer {
++ rockchip,pins =
++ /* i2c2_scl_m1 */
++ <1 RK_PA0 10 &pcfg_pull_none_smt>,
++ /* i2c2_sda_m1 */
++ <1 RK_PA1 10 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c2m2_xfer: i2c2m2-xfer {
++ rockchip,pins =
++ /* i2c2_scl_m2 */
++ <4 RK_PA3 11 &pcfg_pull_none_smt>,
++ /* i2c2_sda_m2 */
++ <4 RK_PA5 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c2m3_xfer: i2c2m3-xfer {
++ rockchip,pins =
++ /* i2c2_scl_m3 */
++ <4 RK_PC2 11 &pcfg_pull_none_smt>,
++ /* i2c2_sda_m3 */
++ <4 RK_PC3 11 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c3 {
++ /omit-if-no-ref/
++ i2c3m0_xfer: i2c3m0-xfer {
++ rockchip,pins =
++ /* i2c3_scl_m0 */
++ <4 RK_PB5 11 &pcfg_pull_none_smt>,
++ /* i2c3_sda_m0 */
++ <4 RK_PB4 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c3m1_xfer: i2c3m1-xfer {
++ rockchip,pins =
++ /* i2c3_scl_m1 */
++ <0 RK_PC6 9 &pcfg_pull_none_smt>,
++ /* i2c3_sda_m1 */
++ <0 RK_PC7 9 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c3m2_xfer: i2c3m2-xfer {
++ rockchip,pins =
++ /* i2c3_scl_m2 */
++ <3 RK_PD4 11 &pcfg_pull_none_smt>,
++ /* i2c3_sda_m2 */
++ <3 RK_PD5 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c3m3_xfer: i2c3m3-xfer {
++ rockchip,pins =
++ /* i2c3_scl_m3 */
++ <4 RK_PC4 11 &pcfg_pull_none_smt>,
++ /* i2c3_sda_m3 */
++ <4 RK_PC5 11 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c4 {
++ /omit-if-no-ref/
++ i2c4m0_xfer: i2c4m0-xfer {
++ rockchip,pins =
++ /* i2c4_scl_m0 */
++ <0 RK_PD2 9 &pcfg_pull_none_smt>,
++ /* i2c4_sda_m0 */
++ <0 RK_PD3 9 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c4m1_xfer: i2c4m1-xfer {
++ rockchip,pins =
++ /* i2c4_scl_m1 */
++ <4 RK_PA4 11 &pcfg_pull_none_smt>,
++ /* i2c4_sda_m1 */
++ <4 RK_PA6 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c4m2_xfer: i2c4m2-xfer {
++ rockchip,pins =
++ /* i2c4_scl_m2 */
++ <2 RK_PA6 11 &pcfg_pull_none_smt>,
++ /* i2c4_sda_m2 */
++ <2 RK_PA7 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c4m3_xfer: i2c4m3-xfer {
++ rockchip,pins =
++ /* i2c4_scl_m3 */
++ <3 RK_PC0 11 &pcfg_pull_none_smt>,
++ /* i2c4_sda_m3 */
++ <3 RK_PB7 11 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c5 {
++ /omit-if-no-ref/
++ i2c5m0_xfer: i2c5m0-xfer {
++ rockchip,pins =
++ /* i2c5_scl_m0 */
++ <2 RK_PA5 11 &pcfg_pull_none_smt>,
++ /* i2c5_sda_m0 */
++ <2 RK_PA4 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c5m1_xfer: i2c5m1-xfer {
++ rockchip,pins =
++ /* i2c5_scl_m1 */
++ <1 RK_PD4 10 &pcfg_pull_none_smt>,
++ /* i2c5_sda_m1 */
++ <1 RK_PD5 10 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c5m2_xfer: i2c5m2-xfer {
++ rockchip,pins =
++ /* i2c5_scl_m2 */
++ <2 RK_PC6 11 &pcfg_pull_none_smt>,
++ /* i2c5_sda_m2 */
++ <2 RK_PC7 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c5m3_xfer: i2c5m3-xfer {
++ rockchip,pins =
++ /* i2c5_scl_m3 */
++ <3 RK_PC4 11 &pcfg_pull_none_smt>,
++ /* i2c5_sda_m3 */
++ <3 RK_PC1 11 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c6 {
++ /omit-if-no-ref/
++ i2c6m0_xfer: i2c6m0-xfer {
++ rockchip,pins =
++ /* i2c6_scl_m0 */
++ <0 RK_PA2 11 &pcfg_pull_none_smt>,
++ /* i2c6_sda_m0 */
++ <0 RK_PA5 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c6m1_xfer: i2c6m1-xfer {
++ rockchip,pins =
++ /* i2c6_scl_m1 */
++ <1 RK_PC2 10 &pcfg_pull_none_smt>,
++ /* i2c6_sda_m1 */
++ <1 RK_PC3 10 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c6m2_xfer: i2c6m2-xfer {
++ rockchip,pins =
++ /* i2c6_scl_m2 */
++ <2 RK_PD0 11 &pcfg_pull_none_smt>,
++ /* i2c6_sda_m2 */
++ <2 RK_PD1 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c6m3_xfer: i2c6m3-xfer {
++ rockchip,pins =
++ /* i2c6_scl_m3 */
++ <4 RK_PC6 11 &pcfg_pull_none_smt>,
++ /* i2c6_sda_m3 */
++ <4 RK_PC7 11 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c7 {
++ /omit-if-no-ref/
++ i2c7m0_xfer: i2c7m0-xfer {
++ rockchip,pins =
++ /* i2c7_scl_m0 */
++ <1 RK_PB0 10 &pcfg_pull_none_smt>,
++ /* i2c7_sda_m0 */
++ <1 RK_PB3 10 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c7m1_xfer: i2c7m1-xfer {
++ rockchip,pins =
++ /* i2c7_scl_m1 */
++ <3 RK_PA0 11 &pcfg_pull_none_smt>,
++ /* i2c7_sda_m1 */
++ <3 RK_PA1 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c7m2_xfer: i2c7m2-xfer {
++ rockchip,pins =
++ /* i2c7_scl_m2 */
++ <4 RK_PA0 11 &pcfg_pull_none_smt>,
++ /* i2c7_sda_m2 */
++ <4 RK_PA1 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c7m3_xfer: i2c7m3-xfer {
++ rockchip,pins =
++ /* i2c7_scl_m3 */
++ <4 RK_PC0 11 &pcfg_pull_none_smt>,
++ /* i2c7_sda_m3 */
++ <4 RK_PC1 11 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c8 {
++ /omit-if-no-ref/
++ i2c8m0_xfer: i2c8m0-xfer {
++ rockchip,pins =
++ /* i2c8_scl_m0 */
++ <2 RK_PA0 11 &pcfg_pull_none_smt>,
++ /* i2c8_sda_m0 */
++ <2 RK_PA1 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c8m1_xfer: i2c8m1-xfer {
++ rockchip,pins =
++ /* i2c8_scl_m1 */
++ <1 RK_PC6 10 &pcfg_pull_none_smt>,
++ /* i2c8_sda_m1 */
++ <1 RK_PC7 10 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c8m2_xfer: i2c8m2-xfer {
++ rockchip,pins =
++ /* i2c8_scl_m2 */
++ <2 RK_PB6 11 &pcfg_pull_none_smt>,
++ /* i2c8_sda_m2 */
++ <2 RK_PB7 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c8m3_xfer: i2c8m3-xfer {
++ rockchip,pins =
++ /* i2c8_scl_m3 */
++ <3 RK_PB3 11 &pcfg_pull_none_smt>,
++ /* i2c8_sda_m3 */
++ <3 RK_PB2 11 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c9 {
++ /omit-if-no-ref/
++ i2c9m0_xfer: i2c9m0-xfer {
++ rockchip,pins =
++ /* i2c9_scl_m0 */
++ <1 RK_PA5 10 &pcfg_pull_none_smt>,
++ /* i2c9_sda_m0 */
++ <1 RK_PA6 10 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c9m1_xfer: i2c9m1-xfer {
++ rockchip,pins =
++ /* i2c9_scl_m1 */
++ <1 RK_PB5 10 &pcfg_pull_none_smt>,
++ /* i2c9_sda_m1 */
++ <1 RK_PB4 10 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c9m2_xfer: i2c9m2-xfer {
++ rockchip,pins =
++ /* i2c9_scl_m2 */
++ <2 RK_PD5 11 &pcfg_pull_none_smt>,
++ /* i2c9_sda_m2 */
++ <2 RK_PD4 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c9m3_xfer: i2c9m3-xfer {
++ rockchip,pins =
++ /* i2c9_scl_m3 */
++ <3 RK_PC2 11 &pcfg_pull_none_smt>,
++ /* i2c9_sda_m3 */
++ <3 RK_PC3 11 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i3c0 {
++ /omit-if-no-ref/
++ i3c0m0_xfer: i3c0m0-xfer {
++ rockchip,pins =
++ /* i3c0_scl_m0 */
++ <0 RK_PC1 11 &pcfg_pull_none_smt>,
++ /* i3c0_sda_m0 */
++ <0 RK_PC2 11 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i3c0m1_xfer: i3c0m1-xfer {
++ rockchip,pins =
++ /* i3c0_scl_m1 */
++ <1 RK_PD2 10 &pcfg_pull_none_smt>,
++ /* i3c0_sda_m1 */
++ <1 RK_PD3 10 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i3c1 {
++ /omit-if-no-ref/
++ i3c1m0_xfer: i3c1m0-xfer {
++ rockchip,pins =
++ /* i3c1_scl_m0 */
++ <2 RK_PD2 12 &pcfg_pull_none_smt>,
++ /* i3c1_sda_m0 */
++ <2 RK_PD3 12 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i3c1m1_xfer: i3c1m1-xfer {
++ rockchip,pins =
++ /* i3c1_scl_m1 */
++ <2 RK_PA2 14 &pcfg_pull_none_smt>,
++ /* i3c1_sda_m1 */
++ <2 RK_PA3 14 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i3c1m2_xfer: i3c1m2-xfer {
++ rockchip,pins =
++ /* i3c1_scl_m2 */
++ <3 RK_PD3 11 &pcfg_pull_none_smt>,
++ /* i3c1_sda_m2 */
++ <3 RK_PD2 11 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i3c0_sda {
++ /omit-if-no-ref/
++ i3c0_sdam0_pu: i3c0_sdam0-pu {
++ rockchip,pins =
++ /* i3c0_sda_pu_m0 */
++ <0 RK_PC5 11 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ i3c0_sdam1_pu: i3c0_sdam1-pu {
++ rockchip,pins =
++ /* i3c0_sda_pu_m1 */
++ <1 RK_PD1 10 &pcfg_pull_none>;
++ };
++ };
++
++ i3c1_sda {
++ /omit-if-no-ref/
++ i3c1_sdam0_pu: i3c1_sdam0-pu {
++ rockchip,pins =
++ /* i3c1_sda_pu_m0 */
++ <2 RK_PD6 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ i3c1_sdam1_pu: i3c1_sdam1-pu {
++ rockchip,pins =
++ /* i3c1_sda_pu_m1 */
++ <2 RK_PA5 14 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ i3c1_sdam2_pu: i3c1_sdam2-pu {
++ rockchip,pins =
++ /* i3c1_sda_pu_m2 */
++ <3 RK_PD1 11 &pcfg_pull_none>;
++ };
++ };
++
++ isp_flash {
++ /omit-if-no-ref/
++ isp_flashm0_pins: isp_flashm0-pins {
++ rockchip,pins =
++ /* isp_flash_trigout_m0 */
++ <2 RK_PD5 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ isp_flashm1_pins: isp_flashm1-pins {
++ rockchip,pins =
++ /* isp_flash_trigout_m1 */
++ <4 RK_PC5 1 &pcfg_pull_none>;
++ };
++ };
++
++ isp_prelight {
++ /omit-if-no-ref/
++ isp_prelightm0_pins: isp_prelightm0-pins {
++ rockchip,pins =
++ /* isp_prelight_trig_m0 */
++ <2 RK_PD4 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ isp_prelightm1_pins: isp_prelightm1-pins {
++ rockchip,pins =
++ /* isp_prelight_trig_m1 */
++ <4 RK_PC4 1 &pcfg_pull_none>;
++ };
++ };
++
++ jtag {
++ /omit-if-no-ref/
++ jtagm0_pins: jtagm0-pins {
++ rockchip,pins =
++ /* jtag_tck_m0 */
++ <2 RK_PA2 9 &pcfg_pull_none>,
++ /* jtag_tms_m0 */
++ <2 RK_PA3 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ jtagm1_pins: jtagm1-pins {
++ rockchip,pins =
++ /* jtag_tck_m1 */
++ <0 RK_PD4 10 &pcfg_pull_none>,
++ /* jtag_tms_m1 */
++ <0 RK_PD5 10 &pcfg_pull_none>;
++ };
++ };
++
++ mipi {
++ /omit-if-no-ref/
++ mipim0_pins: mipim0-pins {
++ rockchip,pins =
++ /* mipi_te_m0 */
++ <4 RK_PB2 11 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ mipim1_pins: mipim1-pins {
++ rockchip,pins =
++ /* mipi_te_m1 */
++ <3 RK_PA2 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ mipim2_pins: mipim2-pins {
++ rockchip,pins =
++ /* mipi_te_m2 */
++ <4 RK_PA0 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ mipim3_pins: mipim3-pins {
++ rockchip,pins =
++ /* mipi_te_m3 */
++ <1 RK_PB3 11 &pcfg_pull_none>;
++ };
++ };
++
++ npu {
++ /omit-if-no-ref/
++ npu_pins: npu-pins {
++ rockchip,pins =
++ /* npu_avs */
++ <0 RK_PB7 11 &pcfg_pull_none>;
++ };
++ };
++
++ pcie0 {
++ /omit-if-no-ref/
++ pcie0m0_pins: pcie0m0-pins {
++ rockchip,pins =
++ /* pcie21_port0_clkreq_m0 */
++ <2 RK_PB2 11 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ pcie0m1_pins: pcie0m1-pins {
++ rockchip,pins =
++ /* pcie0_clkreq_m1 */
++ <1 RK_PB6 12 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ pcie0m2_pins: pcie0m2-pins {
++ rockchip,pins =
++ /* pcie0_clkreq_m2 */
++ <4 RK_PB5 12 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ pcie0m3_pins: pcie0m3-pins {
++ rockchip,pins =
++ /* pcie0_clkreq_m3 */
++ <4 RK_PC6 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ pcie0_buttonrst: pcie21-port0-buttonrst {
++ rockchip,pins =
++ /* pcie0_buttonrst */
++ <1 RK_PC4 12 &pcfg_pull_none>;
++ };
++ };
++
++ pcie1 {
++ /omit-if-no-ref/
++ pcie1m0_pins: pcie1m0-pins {
++ rockchip,pins =
++ /* pcie1_clkreq_m0 */
++ <2 RK_PB3 11 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ pcie1m1_pins: pcie1m1-pins {
++ rockchip,pins =
++ /* pcie1_clkreq_m1 */
++ <1 RK_PB4 12 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ pcie1m2_pins: pcie1m2-pins {
++ rockchip,pins =
++ /* pcie1_clkreq_m2 */
++ <4 RK_PA5 12 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ pcie1m3_pins: pcie1m3-pins {
++ rockchip,pins =
++ /* pcie1_clkreq_m3 */
++ <4 RK_PC1 10 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ pcie1_buttonrst: pcie21-port1-buttonrst {
++ rockchip,pins =
++ /* pcie1_buttonrst */
++ <1 RK_PC5 12 &pcfg_pull_none>;
++ };
++ };
++
++ pdm0 {
++ /omit-if-no-ref/
++ pdm0m0_clk0: pdm0m0-clk0 {
++ rockchip,pins =
++ /* pdm0_clk0_m0 */
++ <0 RK_PC4 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m0_clk1: pdm0m0-clk1 {
++ rockchip,pins =
++ /* pdm0_clk1_m0 */
++ <0 RK_PC3 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m0_sdi0: pdm0m0-sdi0 {
++ rockchip,pins =
++ /* pdm0_sdi0_m0 */
++ <0 RK_PD0 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m0_sdi1: pdm0m0-sdi1 {
++ rockchip,pins =
++ /* pdm0_sdi1_m0 */
++ <0 RK_PD1 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m0_sdi2: pdm0m0-sdi2 {
++ rockchip,pins =
++ /* pdm0_sdi2_m0 */
++ <0 RK_PD2 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m0_sdi3: pdm0m0-sdi3 {
++ rockchip,pins =
++ /* pdm0_sdi3_m0 */
++ <0 RK_PD3 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m1_clk0: pdm0m1-clk0 {
++ rockchip,pins =
++ /* pdm0_clk0_m1 */
++ <1 RK_PB1 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m1_clk1: pdm0m1-clk1 {
++ rockchip,pins =
++ /* pdm0_clk1_m1 */
++ <1 RK_PA6 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m1_sdi0: pdm0m1-sdi0 {
++ rockchip,pins =
++ /* pdm0_sdi0_m1 */
++ <1 RK_PB2 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m1_sdi1: pdm0m1-sdi1 {
++ rockchip,pins =
++ /* pdm0_sdi1_m1 */
++ <1 RK_PA3 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m1_sdi2: pdm0m1-sdi2 {
++ rockchip,pins =
++ /* pdm0_sdi2_m1 */
++ <1 RK_PA5 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m1_sdi3: pdm0m1-sdi3 {
++ rockchip,pins =
++ /* pdm0_sdi3_m1 */
++ <1 RK_PA2 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m2_clk0: pdm0m2-clk0 {
++ rockchip,pins =
++ /* pdm0_clk0_m2 */
++ <1 RK_PC1 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m2_clk1: pdm0m2-clk1 {
++ rockchip,pins =
++ /* pdm0_clk1_m2 */
++ <1 RK_PD5 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m2_sdi0: pdm0m2-sdi0 {
++ rockchip,pins =
++ /* pdm0_sdi0_m2 */
++ <1 RK_PC6 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m2_sdi1: pdm0m2-sdi1 {
++ rockchip,pins =
++ /* pdm0_sdi1_m2 */
++ <1 RK_PC7 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m2_sdi2: pdm0m2-sdi2 {
++ rockchip,pins =
++ /* pdm0_sdi2_m2 */
++ <1 RK_PC0 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m2_sdi3: pdm0m2-sdi3 {
++ rockchip,pins =
++ /* pdm0_sdi3_m2 */
++ <1 RK_PD4 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m3_clk0: pdm0m3-clk0 {
++ rockchip,pins =
++ /* pdm0_clk0_m3 */
++ <2 RK_PB5 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m3_clk1: pdm0m3-clk1 {
++ rockchip,pins =
++ /* pdm0_clk1_m3 */
++ <2 RK_PB3 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m3_sdi0: pdm0m3-sdi0 {
++ rockchip,pins =
++ /* pdm0_sdi0_m3 */
++ <2 RK_PB4 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m3_sdi1: pdm0m3-sdi1 {
++ rockchip,pins =
++ /* pdm0_sdi1_m3 */
++ <2 RK_PB2 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m3_sdi2: pdm0m3-sdi2 {
++ rockchip,pins =
++ /* pdm0_sdi2_m3 */
++ <2 RK_PB1 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm0m3_sdi3: pdm0m3-sdi3 {
++ rockchip,pins =
++ /* pdm0_sdi3_m3 */
++ <2 RK_PB0 5 &pcfg_pull_none>;
++ };
++ };
++
++ pdm1 {
++ /omit-if-no-ref/
++ pdm1m0_clk0: pdm1m0-clk0 {
++ rockchip,pins =
++ /* pdm1_clk0_m0 */
++ <2 RK_PC5 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m0_clk1: pdm1m0-clk1 {
++ rockchip,pins =
++ /* pdm1_clk1_m0 */
++ <2 RK_PC1 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m0_sdi0: pdm1m0-sdi0 {
++ rockchip,pins =
++ /* pdm1_sdi0_m0 */
++ <2 RK_PC4 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m0_sdi1: pdm1m0-sdi1 {
++ rockchip,pins =
++ /* pdm1_sdi1_m0 */
++ <2 RK_PC0 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m0_sdi2: pdm1m0-sdi2 {
++ rockchip,pins =
++ /* pdm1_sdi2_m0 */
++ <2 RK_PC2 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m0_sdi3: pdm1m0-sdi3 {
++ rockchip,pins =
++ /* pdm1_sdi3_m0 */
++ <2 RK_PC3 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m1_clk0: pdm1m1-clk0 {
++ rockchip,pins =
++ /* pdm1_clk0_m1 */
++ <4 RK_PA6 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m1_clk1: pdm1m1-clk1 {
++ rockchip,pins =
++ /* pdm1_clk1_m1 */
++ <4 RK_PB0 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m1_sdi0: pdm1m1-sdi0 {
++ rockchip,pins =
++ /* pdm1_sdi0_m1 */
++ <4 RK_PB3 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m1_sdi1: pdm1m1-sdi1 {
++ rockchip,pins =
++ /* pdm1_sdi1_m1 */
++ <4 RK_PB2 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m1_sdi2: pdm1m1-sdi2 {
++ rockchip,pins =
++ /* pdm1_sdi2_m1 */
++ <4 RK_PB1 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m1_sdi3: pdm1m1-sdi3 {
++ rockchip,pins =
++ /* pdm1_sdi3_m1 */
++ <4 RK_PA4 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m2_clk0: pdm1m2-clk0 {
++ rockchip,pins =
++ /* pdm1_clk0_m2 */
++ <3 RK_PB1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m2_clk1: pdm1m2-clk1 {
++ rockchip,pins =
++ /* pdm1_clk1_m2 */
++ <3 RK_PA7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m2_sdi0: pdm1m2-sdi0 {
++ rockchip,pins =
++ /* pdm1_sdi0_m2 */
++ <3 RK_PB3 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m2_sdi1: pdm1m2-sdi1 {
++ rockchip,pins =
++ /* pdm1_sdi1_m2 */
++ <3 RK_PB2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m2_sdi2: pdm1m2-sdi2 {
++ rockchip,pins =
++ /* pdm1_sdi2_m2 */
++ <3 RK_PA6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm1m2_sdi3: pdm1m2-sdi3 {
++ rockchip,pins =
++ /* pdm1_sdi3_m2 */
++ <3 RK_PA5 4 &pcfg_pull_none>;
++ };
++ };
++
++ pmu_debug_test {
++ /omit-if-no-ref/
++ pmu_debug_test_pins: pmu_debug_test-pins {
++ rockchip,pins =
++ /* pmu_debug_test_out */
++ <0 RK_PB0 2 &pcfg_pull_none>;
++ };
++ };
++
++ pwm0 {
++ /omit-if-no-ref/
++ pwm0m0_ch0: pwm0m0-ch0 {
++ rockchip,pins =
++ /* pwm0_ch0_m0 */
++ <0 RK_PC4 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm0m0_ch1: pwm0m0-ch1 {
++ rockchip,pins =
++ /* pwm0_ch1_m0 */
++ <0 RK_PC3 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm0m1_ch0: pwm0m1-ch0 {
++ rockchip,pins =
++ /* pwm0_ch0_m1 */
++ <1 RK_PC0 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm0m1_ch1: pwm0m1-ch1 {
++ rockchip,pins =
++ /* pwm0_ch1_m1 */
++ <4 RK_PC1 14 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm0m2_ch0: pwm0m2-ch0 {
++ rockchip,pins =
++ /* pwm0_ch0_m2 */
++ <2 RK_PC3 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm0m2_ch1: pwm0m2-ch1 {
++ rockchip,pins =
++ /* pwm0_ch1_m2 */
++ <2 RK_PC7 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm0m3_ch0: pwm0m3-ch0 {
++ rockchip,pins =
++ /* pwm0_ch0_m3 */
++ <3 RK_PB0 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm0m3_ch1: pwm0m3-ch1 {
++ rockchip,pins =
++ /* pwm0_ch1_m3 */
++ <3 RK_PB6 12 &pcfg_pull_none_drv_level_2>;
++ };
++ };
++
++ pwm1 {
++ /omit-if-no-ref/
++ pwm1m0_ch0: pwm1m0-ch0 {
++ rockchip,pins =
++ /* pwm1_ch0_m0 */
++ <0 RK_PB4 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m0_ch1: pwm1m0-ch1 {
++ rockchip,pins =
++ /* pwm1_ch1_m0 */
++ <0 RK_PB5 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m0_ch2: pwm1m0-ch2 {
++ rockchip,pins =
++ /* pwm1_ch2_m0 */
++ <0 RK_PB6 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m0_ch3: pwm1m0-ch3 {
++ rockchip,pins =
++ /* pwm1_ch3_m0 */
++ <0 RK_PC0 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m0_ch4: pwm1m0-ch4 {
++ rockchip,pins =
++ /* pwm1_ch4_m0 */
++ <0 RK_PB7 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m0_ch5: pwm1m0-ch5 {
++ rockchip,pins =
++ /* pwm1_ch5_m0 */
++ <0 RK_PD2 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m1_ch0: pwm1m1-ch0 {
++ rockchip,pins =
++ /* pwm1_ch0_m1 */
++ <1 RK_PB4 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m1_ch1: pwm1m1-ch1 {
++ rockchip,pins =
++ /* pwm1_ch1_m1 */
++ <1 RK_PB5 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m1_ch2: pwm1m1-ch2 {
++ rockchip,pins =
++ /* pwm1_ch2_m1 */
++ <1 RK_PC2 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m1_ch3: pwm1m1-ch3 {
++ rockchip,pins =
++ /* pwm1_ch3_m1 */
++ <1 RK_PD2 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m1_ch4: pwm1m1-ch4 {
++ rockchip,pins =
++ /* pwm1_ch4_m1 */
++ <1 RK_PD3 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m1_ch5: pwm1m1-ch5 {
++ rockchip,pins =
++ /* pwm1_ch5_m1 */
++ <4 RK_PC0 14 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m2_ch0: pwm1m2-ch0 {
++ rockchip,pins =
++ /* pwm1_ch0_m2 */
++ <2 RK_PC0 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m2_ch1: pwm1m2-ch1 {
++ rockchip,pins =
++ /* pwm1_ch1_m2 */
++ <2 RK_PC1 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m2_ch2: pwm1m2-ch2 {
++ rockchip,pins =
++ /* pwm1_ch2_m2 */
++ <2 RK_PC2 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m2_ch3: pwm1m2-ch3 {
++ rockchip,pins =
++ /* pwm1_ch3_m2 */
++ <2 RK_PC4 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m2_ch4: pwm1m2-ch4 {
++ rockchip,pins =
++ /* pwm1_ch4_m2 */
++ <2 RK_PC5 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m2_ch5: pwm1m2-ch5 {
++ rockchip,pins =
++ /* pwm1_ch5_m2 */
++ <2 RK_PC6 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m3_ch0: pwm1m3-ch0 {
++ rockchip,pins =
++ /* pwm1_ch0_m3 */
++ <3 RK_PA4 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m3_ch1: pwm1m3-ch1 {
++ rockchip,pins =
++ /* pwm1_ch1_m3 */
++ <3 RK_PA5 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m3_ch2: pwm1m3-ch2 {
++ rockchip,pins =
++ /* pwm1_ch2_m3 */
++ <3 RK_PA6 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m3_ch3: pwm1m3-ch3 {
++ rockchip,pins =
++ /* pwm1_ch3_m3 */
++ <3 RK_PB1 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m3_ch4: pwm1m3-ch4 {
++ rockchip,pins =
++ /* pwm1_ch4_m3 */
++ <3 RK_PB4 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m3_ch5: pwm1m3-ch5 {
++ rockchip,pins =
++ /* pwm1_ch5_m3 */
++ <3 RK_PB5 12 &pcfg_pull_none>;
++ };
++ };
++
++ pwm2 {
++ /omit-if-no-ref/
++ pwm2m0_ch0: pwm2m0-ch0 {
++ rockchip,pins =
++ /* pwm2_ch0_m0 */
++ <0 RK_PD3 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m0_ch1: pwm2m0-ch1 {
++ rockchip,pins =
++ /* pwm2_ch1_m0 */
++ <1 RK_PB3 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m0_ch2: pwm2m0-ch2 {
++ rockchip,pins =
++ /* pwm2_ch2_m0 */
++ <2 RK_PA0 14 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m0_ch3: pwm2m0-ch3 {
++ rockchip,pins =
++ /* pwm2_ch3_m0 */
++ <2 RK_PA1 14 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m0_ch4: pwm2m0-ch4 {
++ rockchip,pins =
++ /* pwm2_ch4_m0 */
++ <2 RK_PA4 14 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m0_ch5: pwm2m0-ch5 {
++ rockchip,pins =
++ /* pwm2_ch5_m0 */
++ <4 RK_PA2 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m0_ch6: pwm2m0-ch6 {
++ rockchip,pins =
++ /* pwm2_ch6_m0 */
++ <4 RK_PA7 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m0_ch7: pwm2m0-ch7 {
++ rockchip,pins =
++ /* pwm2_ch7_m0 */
++ <4 RK_PB3 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m1_ch0: pwm2m1-ch0 {
++ rockchip,pins =
++ /* pwm2_ch0_m1 */
++ <4 RK_PC2 14 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m1_ch1: pwm2m1-ch1 {
++ rockchip,pins =
++ /* pwm2_ch1_m1 */
++ <4 RK_PC3 14 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m1_ch2: pwm2m1-ch2 {
++ rockchip,pins =
++ /* pwm2_ch2_m1 */
++ <4 RK_PC6 14 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m1_ch3: pwm2m1-ch3 {
++ rockchip,pins =
++ /* pwm2_ch3_m1 */
++ <4 RK_PC7 14 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m1_ch4: pwm2m1-ch4 {
++ rockchip,pins =
++ /* pwm2_ch4_m1 */
++ <4 RK_PA3 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m1_ch5: pwm2m1-ch5 {
++ rockchip,pins =
++ /* pwm2_ch5_m1 */
++ <4 RK_PC5 14 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m1_ch6: pwm2m1-ch6 {
++ rockchip,pins =
++ /* pwm2_ch6_m1 */
++ <4 RK_PC4 14 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m1_ch7: pwm2m1-ch7 {
++ rockchip,pins =
++ /* pwm2_ch7_m1 */
++ <1 RK_PB1 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m2_ch0: pwm2m2-ch0 {
++ rockchip,pins =
++ /* pwm2_ch0_m2 */
++ <2 RK_PD0 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m2_ch1: pwm2m2-ch1 {
++ rockchip,pins =
++ /* pwm2_ch1_m2 */
++ <2 RK_PD1 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m2_ch2: pwm2m2-ch2 {
++ rockchip,pins =
++ /* pwm2_ch2_m2 */
++ <2 RK_PD2 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m2_ch3: pwm2m2-ch3 {
++ rockchip,pins =
++ /* pwm2_ch3_m2 */
++ <2 RK_PD3 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m2_ch4: pwm2m2-ch4 {
++ rockchip,pins =
++ /* pwm2_ch4_m2 */
++ <2 RK_PD4 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m2_ch5: pwm2m2-ch5 {
++ rockchip,pins =
++ /* pwm2_ch5_m2 */
++ <2 RK_PD5 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m2_ch6: pwm2m2-ch6 {
++ rockchip,pins =
++ /* pwm2_ch6_m2 */
++ <2 RK_PD6 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m2_ch7: pwm2m2-ch7 {
++ rockchip,pins =
++ /* pwm2_ch7_m2 */
++ <2 RK_PD7 13 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m3_ch0: pwm2m3-ch0 {
++ rockchip,pins =
++ /* pwm2_ch0_m3 */
++ <3 RK_PC2 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m3_ch1: pwm2m3-ch1 {
++ rockchip,pins =
++ /* pwm2_ch1_m3 */
++ <3 RK_PC3 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m3_ch2: pwm2m3-ch2 {
++ rockchip,pins =
++ /* pwm2_ch2_m3 */
++ <3 RK_PC5 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m3_ch3: pwm2m3-ch3 {
++ rockchip,pins =
++ /* pwm2_ch3_m3 */
++ <3 RK_PD0 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m3_ch4: pwm2m3-ch4 {
++ rockchip,pins =
++ /* pwm2_ch4_m3 */
++ <3 RK_PD2 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m3_ch5: pwm2m3-ch5 {
++ rockchip,pins =
++ /* pwm2_ch5_m3 */
++ <3 RK_PD3 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m3_ch6: pwm2m3-ch6 {
++ rockchip,pins =
++ /* pwm2_ch6_m3 */
++ <3 RK_PD6 12 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m3_ch7: pwm2m3-ch7 {
++ rockchip,pins =
++ /* pwm2_ch7_m3 */
++ <3 RK_PD7 12 &pcfg_pull_none_drv_level_2>;
++ };
++ };
++
++ ref_clk0 {
++ /omit-if-no-ref/
++ ref_clk0_clk0: ref_clk0-clk0 {
++ rockchip,pins =
++ /* ref_clk0_out */
++ <0 RK_PA0 1 &pcfg_pull_none>;
++ };
++ };
++
++ ref_clk1 {
++ /omit-if-no-ref/
++ ref_clk1_clk1: ref_clk1-clk1 {
++ rockchip,pins =
++ /* ref_clk1_out */
++ <0 RK_PB4 1 &pcfg_pull_none>;
++ };
++ };
++
++ ref_clk2 {
++ /omit-if-no-ref/
++ ref_clk2_clk2: ref_clk2-clk2 {
++ rockchip,pins =
++ /* ref_clk2_out */
++ <0 RK_PB5 1 &pcfg_pull_none>;
++ };
++ };
++
++ sai0 {
++ /omit-if-no-ref/
++ sai0m0_lrck: sai0m0-lrck {
++ rockchip,pins =
++ /* sai0_lrck_m0 */
++ <2 RK_PB7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m0_mclk: sai0m0-mclk {
++ rockchip,pins =
++ /* sai0_mclk_m0 */
++ <2 RK_PB5 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m0_sclk: sai0m0-sclk {
++ rockchip,pins =
++ /* sai0_sclk_m0 */
++ <2 RK_PB6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m0_sdi0: sai0m0-sdi0 {
++ rockchip,pins =
++ /* sai0_sdi0_m0 */
++ <2 RK_PB0 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m0_sdi1: sai0m0-sdi1 {
++ rockchip,pins =
++ /* sai0_sdi1_m0 */
++ <2 RK_PB1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m0_sdi2: sai0m0-sdi2 {
++ rockchip,pins =
++ /* sai0_sdi2_m0 */
++ <2 RK_PB2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m0_sdi3: sai0m0-sdi3 {
++ rockchip,pins =
++ /* sai0_sdi3_m0 */
++ <2 RK_PB4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m0_sdo0: sai0m0-sdo0 {
++ rockchip,pins =
++ /* sai0_sdo0_m0 */
++ <2 RK_PA6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m0_sdo1: sai0m0-sdo1 {
++ rockchip,pins =
++ /* sai0_sdo1_m0 */
++ <2 RK_PA7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m0_sdo2: sai0m0-sdo2 {
++ rockchip,pins =
++ /* sai0_sdo2_m0 */
++ <2 RK_PB3 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m0_sdo3: sai0m0-sdo3 {
++ rockchip,pins =
++ /* sai0_sdo3_m0 */
++ <2 RK_PD7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m1_lrck: sai0m1-lrck {
++ rockchip,pins =
++ /* sai0_lrck_m1 */
++ <0 RK_PC7 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m1_mclk: sai0m1-mclk {
++ rockchip,pins =
++ /* sai0_mclk_m1 */
++ <0 RK_PC4 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m1_sclk: sai0m1-sclk {
++ rockchip,pins =
++ /* sai0_sclk_m1 */
++ <0 RK_PC6 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m1_sdi0: sai0m1-sdi0 {
++ rockchip,pins =
++ /* sai0_sdi0_m1 */
++ <0 RK_PD0 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m1_sdi1: sai0m1-sdi1 {
++ rockchip,pins =
++ /* sai0_sdi1_m1 */
++ <0 RK_PD1 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m1_sdi2: sai0m1-sdi2 {
++ rockchip,pins =
++ /* sai0_sdi2_m1 */
++ <0 RK_PD2 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m1_sdi3: sai0m1-sdi3 {
++ rockchip,pins =
++ /* sai0_sdi3_m1 */
++ <0 RK_PD3 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m1_sdo0: sai0m1-sdo0 {
++ rockchip,pins =
++ /* sai0_sdo0_m1 */
++ <0 RK_PC5 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m1_sdo1: sai0m1-sdo1 {
++ rockchip,pins =
++ /* sai0_sdo1_m1 */
++ <0 RK_PD3 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m1_sdo2: sai0m1-sdo2 {
++ rockchip,pins =
++ /* sai0_sdo2_m1 */
++ <0 RK_PD2 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m1_sdo3: sai0m1-sdo3 {
++ rockchip,pins =
++ /* sai0_sdo3_m1 */
++ <0 RK_PD1 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m2_lrck: sai0m2-lrck {
++ rockchip,pins =
++ /* sai0_lrck_m2 */
++ <1 RK_PA1 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m2_mclk: sai0m2-mclk {
++ rockchip,pins =
++ /* sai0_mclk_m2 */
++ <1 RK_PA4 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m2_sclk: sai0m2-sclk {
++ rockchip,pins =
++ /* sai0_sclk_m2 */
++ <1 RK_PA0 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m2_sdi0: sai0m2-sdi0 {
++ rockchip,pins =
++ /* sai0_sdi0_m2 */
++ <1 RK_PB2 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m2_sdi1: sai0m2-sdi1 {
++ rockchip,pins =
++ /* sai0_sdi1_m2 */
++ <1 RK_PB1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m2_sdi2: sai0m2-sdi2 {
++ rockchip,pins =
++ /* sai0_sdi2_m2 */
++ <1 RK_PA3 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m2_sdi3: sai0m2-sdi3 {
++ rockchip,pins =
++ /* sai0_sdi3_m2 */
++ <1 RK_PA2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m2_sdo0: sai0m2-sdo0 {
++ rockchip,pins =
++ /* sai0_sdo0_m2 */
++ <1 RK_PA7 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m2_sdo1: sai0m2-sdo1 {
++ rockchip,pins =
++ /* sai0_sdo1_m2 */
++ <1 RK_PA2 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m2_sdo2: sai0m2-sdo2 {
++ rockchip,pins =
++ /* sai0_sdo2_m2 */
++ <1 RK_PA3 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai0m2_sdo3: sai0m2-sdo3 {
++ rockchip,pins =
++ /* sai0_sdo3_m2 */
++ <1 RK_PB1 3 &pcfg_pull_none>;
++ };
++ };
++
++ sai1 {
++ /omit-if-no-ref/
++ sai1m0_lrck: sai1m0-lrck {
++ rockchip,pins =
++ /* sai1_lrck_m0 */
++ <4 RK_PA5 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m0_mclk: sai1m0-mclk {
++ rockchip,pins =
++ /* sai1_mclk_m0 */
++ <4 RK_PA2 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m0_sclk: sai1m0-sclk {
++ rockchip,pins =
++ /* sai1_sclk_m0 */
++ <4 RK_PA3 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m0_sdi0: sai1m0-sdi0 {
++ rockchip,pins =
++ /* sai1_sdi0_m0 */
++ <4 RK_PB3 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m0_sdi1: sai1m0-sdi1 {
++ rockchip,pins =
++ /* sai1_sdi1_m0 */
++ <4 RK_PB2 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m0_sdi2: sai1m0-sdi2 {
++ rockchip,pins =
++ /* sai1_sdi2_m0 */
++ <4 RK_PB1 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m0_sdi3: sai1m0-sdi3 {
++ rockchip,pins =
++ /* sai1_sdi3_m0 */
++ <4 RK_PB0 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m0_sdo0: sai1m0-sdo0 {
++ rockchip,pins =
++ /* sai1_sdo0_m0 */
++ <4 RK_PA7 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m0_sdo1: sai1m0-sdo1 {
++ rockchip,pins =
++ /* sai1_sdo1_m0 */
++ <4 RK_PB0 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m0_sdo2: sai1m0-sdo2 {
++ rockchip,pins =
++ /* sai1_sdo2_m0 */
++ <4 RK_PB1 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m0_sdo3: sai1m0-sdo3 {
++ rockchip,pins =
++ /* sai1_sdo3_m0 */
++ <4 RK_PB2 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m1_lrck: sai1m1-lrck {
++ rockchip,pins =
++ /* sai1_lrck_m1 */
++ <3 RK_PC6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m1_mclk: sai1m1-mclk {
++ rockchip,pins =
++ /* sai1_mclk_m1 */
++ <3 RK_PD0 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m1_sclk: sai1m1-sclk {
++ rockchip,pins =
++ /* sai1_sclk_m1 */
++ <3 RK_PC7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m1_sdi0: sai1m1-sdi0 {
++ rockchip,pins =
++ /* sai1_sdi0_m1 */
++ <3 RK_PB7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m1_sdi1: sai1m1-sdi1 {
++ rockchip,pins =
++ /* sai1_sdi1_m1 */
++ <3 RK_PD4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m1_sdi2: sai1m1-sdi2 {
++ rockchip,pins =
++ /* sai1_sdi2_m1 */
++ <3 RK_PD5 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m1_sdi3: sai1m1-sdi3 {
++ rockchip,pins =
++ /* sai1_sdi3_m1 */
++ <3 RK_PD6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m1_sdo0: sai1m1-sdo0 {
++ rockchip,pins =
++ /* sai1_sdo0_m1 */
++ <3 RK_PC5 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m1_sdo1: sai1m1-sdo1 {
++ rockchip,pins =
++ /* sai1_sdo1_m1 */
++ <3 RK_PC4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m1_sdo2: sai1m1-sdo2 {
++ rockchip,pins =
++ /* sai1_sdo2_m1 */
++ <3 RK_PC1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai1m1_sdo3: sai1m1-sdo3 {
++ rockchip,pins =
++ /* sai1_sdo3_m1 */
++ <3 RK_PC0 4 &pcfg_pull_none>;
++ };
++ };
++
++ sai2 {
++ /omit-if-no-ref/
++ sai2m0_lrck: sai2m0-lrck {
++ rockchip,pins =
++ /* sai2_lrck_m0 */
++ <1 RK_PD2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai2m0_mclk: sai2m0-mclk {
++ rockchip,pins =
++ /* sai2_mclk_m0 */
++ <1 RK_PD4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai2m0_sclk: sai2m0-sclk {
++ rockchip,pins =
++ /* sai2_sclk_m0 */
++ <1 RK_PD1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai2m0_sdi: sai2m0-sdi {
++ rockchip,pins =
++ /* sai2m0_sdi */
++ <1 RK_PD3 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ sai2m0_sdo: sai2m0-sdo {
++ rockchip,pins =
++ /* sai2m0_sdo */
++ <1 RK_PD0 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai2m1_lrck: sai2m1-lrck {
++ rockchip,pins =
++ /* sai2_lrck_m1 */
++ <2 RK_PC3 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai2m1_mclk: sai2m1-mclk {
++ rockchip,pins =
++ /* sai2_mclk_m1 */
++ <2 RK_PC1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai2m1_sclk: sai2m1-sclk {
++ rockchip,pins =
++ /* sai2_sclk_m1 */
++ <2 RK_PC2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai2m1_sdi: sai2m1-sdi {
++ rockchip,pins =
++ /* sai2m1_sdi */
++ <2 RK_PC5 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ sai2m1_sdo: sai2m1-sdo {
++ rockchip,pins =
++ /* sai2m1_sdo */
++ <2 RK_PC4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai2m2_lrck: sai2m2-lrck {
++ rockchip,pins =
++ /* sai2_lrck_m2 */
++ <3 RK_PC3 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai2m2_mclk: sai2m2-mclk {
++ rockchip,pins =
++ /* sai2_mclk_m2 */
++ <3 RK_PD1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai2m2_sclk: sai2m2-sclk {
++ rockchip,pins =
++ /* sai2_sclk_m2 */
++ <3 RK_PC2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai2m2_sdi: sai2m2-sdi {
++ rockchip,pins =
++ /* sai2m2_sdi */
++ <3 RK_PD2 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ sai2m2_sdo: sai2m2-sdo {
++ rockchip,pins =
++ /* sai2m2_sdo */
++ <3 RK_PD3 4 &pcfg_pull_none>;
++ };
++ };
++
++ sai3 {
++ /omit-if-no-ref/
++ sai3m0_lrck: sai3m0-lrck {
++ rockchip,pins =
++ /* sai3_lrck_m0 */
++ <1 RK_PA6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m0_mclk: sai3m0-mclk {
++ rockchip,pins =
++ /* sai3_mclk_m0 */
++ <1 RK_PA4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m0_sclk: sai3m0-sclk {
++ rockchip,pins =
++ /* sai3_sclk_m0 */
++ <1 RK_PA5 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m0_sdi: sai3m0-sdi {
++ rockchip,pins =
++ /* sai3m0_sdi */
++ <1 RK_PA7 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ sai3m0_sdo: sai3m0-sdo {
++ rockchip,pins =
++ /* sai3m0_sdo */
++ <1 RK_PB2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m1_lrck: sai3m1-lrck {
++ rockchip,pins =
++ /* sai3_lrck_m1 */
++ <1 RK_PB5 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m1_mclk: sai3m1-mclk {
++ rockchip,pins =
++ /* sai3_mclk_m1 */
++ <1 RK_PC1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m1_sclk: sai3m1-sclk {
++ rockchip,pins =
++ /* sai3_sclk_m1 */
++ <1 RK_PB4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m1_sdi: sai3m1-sdi {
++ rockchip,pins =
++ /* sai3m1_sdi */
++ <1 RK_PB7 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ sai3m1_sdo: sai3m1-sdo {
++ rockchip,pins =
++ /* sai3m1_sdo */
++ <1 RK_PB6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m2_lrck: sai3m2-lrck {
++ rockchip,pins =
++ /* sai3_lrck_m2 */
++ <3 RK_PA1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m2_mclk: sai3m2-mclk {
++ rockchip,pins =
++ /* sai3_mclk_m2 */
++ <2 RK_PD6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m2_sclk: sai3m2-sclk {
++ rockchip,pins =
++ /* sai3_sclk_m2 */
++ <3 RK_PA0 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m2_sdi: sai3m2-sdi {
++ rockchip,pins =
++ /* sai3m2_sdi */
++ <3 RK_PA3 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ sai3m2_sdo: sai3m2-sdo {
++ rockchip,pins =
++ /* sai3m2_sdo */
++ <3 RK_PA2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m3_lrck: sai3m3-lrck {
++ rockchip,pins =
++ /* sai3_lrck_m3 */
++ <2 RK_PA2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m3_mclk: sai3m3-mclk {
++ rockchip,pins =
++ /* sai3_mclk_m3 */
++ <2 RK_PA1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m3_sclk: sai3m3-sclk {
++ rockchip,pins =
++ /* sai3_sclk_m3 */
++ <2 RK_PA5 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai3m3_sdi: sai3m3-sdi {
++ rockchip,pins =
++ /* sai3m3_sdi */
++ <2 RK_PA3 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ sai3m3_sdo: sai3m3-sdo {
++ rockchip,pins =
++ /* sai3m3_sdo */
++ <2 RK_PA4 4 &pcfg_pull_none>;
++ };
++ };
++
++ sai4 {
++ /omit-if-no-ref/
++ sai4m0_lrck: sai4m0-lrck {
++ rockchip,pins =
++ /* sai4_lrck_m0 */
++ <4 RK_PA6 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m0_mclk: sai4m0-mclk {
++ rockchip,pins =
++ /* sai4_mclk_m0 */
++ <4 RK_PA2 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m0_sclk: sai4m0-sclk {
++ rockchip,pins =
++ /* sai4_sclk_m0 */
++ <4 RK_PA4 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m0_sdi: sai4m0-sdi {
++ rockchip,pins =
++ /* sai4m0_sdi */
++ <4 RK_PA7 2 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ sai4m0_sdo: sai4m0-sdo {
++ rockchip,pins =
++ /* sai4m0_sdo */
++ <4 RK_PB3 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m1_lrck: sai4m1-lrck {
++ rockchip,pins =
++ /* sai4_lrck_m1 */
++ <4 RK_PA0 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m1_mclk: sai4m1-mclk {
++ rockchip,pins =
++ /* sai4_mclk_m1 */
++ <3 RK_PB0 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m1_sclk: sai4m1-sclk {
++ rockchip,pins =
++ /* sai4_sclk_m1 */
++ <3 RK_PD7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m1_sdi: sai4m1-sdi {
++ rockchip,pins =
++ /* sai4m1_sdi */
++ <3 RK_PA4 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ sai4m1_sdo: sai4m1-sdo {
++ rockchip,pins =
++ /* sai4m1_sdo */
++ <4 RK_PA1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m2_lrck: sai4m2-lrck {
++ rockchip,pins =
++ /* sai4_lrck_m2 */
++ <4 RK_PC4 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m2_mclk: sai4m2-mclk {
++ rockchip,pins =
++ /* sai4_mclk_m2 */
++ <4 RK_PC0 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m2_sclk: sai4m2-sclk {
++ rockchip,pins =
++ /* sai4_sclk_m2 */
++ <4 RK_PC7 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m2_sdi: sai4m2-sdi {
++ rockchip,pins =
++ /* sai4m2_sdi */
++ <4 RK_PC6 2 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ sai4m2_sdo: sai4m2-sdo {
++ rockchip,pins =
++ /* sai4m2_sdo */
++ <4 RK_PC5 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m3_lrck: sai4m3-lrck {
++ rockchip,pins =
++ /* sai4_lrck_m3 */
++ <2 RK_PC7 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m3_mclk: sai4m3-mclk {
++ rockchip,pins =
++ /* sai4_mclk_m3 */
++ <2 RK_PD2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m3_sclk: sai4m3-sclk {
++ rockchip,pins =
++ /* sai4_sclk_m3 */
++ <2 RK_PC6 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sai4m3_sdi: sai4m3-sdi {
++ rockchip,pins =
++ /* sai4m3_sdi */
++ <2 RK_PD0 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ sai4m3_sdo: sai4m3-sdo {
++ rockchip,pins =
++ /* sai4m3_sdo */
++ <2 RK_PD1 4 &pcfg_pull_none>;
++ };
++ };
++
++ sata30 {
++ /omit-if-no-ref/
++ sata30_sata: sata30-sata {
++ rockchip,pins =
++ /* sata30_cpdet */
++ <1 RK_PC7 12 &pcfg_pull_none>,
++ /* sata30_cppod */
++ <1 RK_PC6 12 &pcfg_pull_none>,
++ /* sata30_mpswit */
++ <1 RK_PD5 12 &pcfg_pull_none>;
++ };
++ };
++
++ sata30_port0 {
++ /omit-if-no-ref/
++ sata30_port0m0_port0: sata30_port0m0-port0 {
++ rockchip,pins =
++ /* sata30_port0_actled_m0 */
++ <2 RK_PB4 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sata30_port0m1_port0: sata30_port0m1-port0 {
++ rockchip,pins =
++ /* sata30_port0_actled_m1 */
++ <4 RK_PC6 10 &pcfg_pull_none>;
++ };
++ };
++
++ sata30_port1 {
++ /omit-if-no-ref/
++ sata30_port1m0_port1: sata30_port1m0-port1 {
++ rockchip,pins =
++ /* sata30_port1_actled_m0 */
++ <2 RK_PB5 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sata30_port1m1_port1: sata30_port1m1-port1 {
++ rockchip,pins =
++ /* sata30_port1_actled_m1 */
++ <4 RK_PC5 10 &pcfg_pull_none>;
++ };
++ };
++
++ sdmmc0 {
++ /omit-if-no-ref/
++ sdmmc0_bus4: sdmmc0-bus4 {
++ rockchip,pins =
++ /* sdmmc0_d0 */
++ <2 RK_PA0 1 &pcfg_pull_up_drv_level_3>,
++ /* sdmmc0_d1 */
++ <2 RK_PA1 1 &pcfg_pull_up_drv_level_3>,
++ /* sdmmc0_d2 */
++ <2 RK_PA2 1 &pcfg_pull_up_drv_level_3>,
++ /* sdmmc0_d3 */
++ <2 RK_PA3 1 &pcfg_pull_up_drv_level_3>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc0_clk: sdmmc0-clk {
++ rockchip,pins =
++ /* sdmmc0_clk */
++ <2 RK_PA5 1 &pcfg_pull_up_drv_level_3>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc0_cmd: sdmmc0-cmd {
++ rockchip,pins =
++ /* sdmmc0_cmd */
++ <2 RK_PA4 1 &pcfg_pull_up_drv_level_3>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc0_det: sdmmc0-det {
++ rockchip,pins =
++ /* sdmmc0_detn */
++ <0 RK_PA7 1 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc0_pwren: sdmmc0-pwren {
++ rockchip,pins =
++ /* sdmmc0_pwren */
++ <0 RK_PB6 1 &pcfg_pull_none>;
++ };
++ };
++
++ sdmmc1 {
++ /omit-if-no-ref/
++ sdmmc1m0_bus4: sdmmc1m0-bus4 {
++ rockchip,pins =
++ /* sdmmc1_d0_m0 */
++ <1 RK_PB4 2 &pcfg_pull_up_drv_level_2>,
++ /* sdmmc1_d1_m0 */
++ <1 RK_PB5 2 &pcfg_pull_up_drv_level_2>,
++ /* sdmmc1_d2_m0 */
++ <1 RK_PB6 2 &pcfg_pull_up_drv_level_2>,
++ /* sdmmc1_d3_m0 */
++ <1 RK_PB7 2 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc1m0_clk: sdmmc1m0-clk {
++ rockchip,pins =
++ /* sdmmc1_clk_m0 */
++ <1 RK_PC1 2 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc1m0_cmd: sdmmc1m0-cmd {
++ rockchip,pins =
++ /* sdmmc1_cmd_m0 */
++ <1 RK_PC0 2 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc1m0_det: sdmmc1m0-det {
++ rockchip,pins =
++ /* sdmmc1_detn_m0 */
++ <1 RK_PC3 2 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc1m0_pwren: sdmmc1m0-pwren {
++ rockchip,pins =
++ /* sdmmc1m0_pwren */
++ <1 RK_PC2 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc1m1_bus4: sdmmc1m1-bus4 {
++ rockchip,pins =
++ /* sdmmc1_d0_m1 */
++ <2 RK_PA6 2 &pcfg_pull_up_drv_level_2>,
++ /* sdmmc1_d1_m1 */
++ <2 RK_PA7 2 &pcfg_pull_up_drv_level_2>,
++ /* sdmmc1_d2_m1 */
++ <2 RK_PB0 2 &pcfg_pull_up_drv_level_2>,
++ /* sdmmc1_d3_m1 */
++ <2 RK_PB1 2 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc1m1_clk: sdmmc1m1-clk {
++ rockchip,pins =
++ /* sdmmc1_clk_m1 */
++ <2 RK_PB3 2 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc1m1_cmd: sdmmc1m1-cmd {
++ rockchip,pins =
++ /* sdmmc1_cmd_m1 */
++ <2 RK_PB2 2 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc1m1_det: sdmmc1m1-det {
++ rockchip,pins =
++ /* sdmmc1_detn_m1 */
++ <2 RK_PB5 2 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc1m1_pwren: sdmmc1m1-pwren {
++ rockchip,pins =
++ /* sdmmc1m1_pwren */
++ <2 RK_PB4 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc1m2_det: sdmmc1m2-det {
++ rockchip,pins =
++ /* sdmmc1_detn_m2 */
++ <0 RK_PB6 2 &pcfg_pull_up>;
++ };
++ };
++
++ sdmmc0_testclk {
++ /omit-if-no-ref/
++ sdmmc0_testclk_test: sdmmc0_testclk-test {
++ rockchip,pins =
++ /* sdmmc0_testclk_out */
++ <1 RK_PC4 6 &pcfg_pull_none>;
++ };
++ };
++
++ sdmmc0_testdata {
++ /omit-if-no-ref/
++ sdmmc0_testdata_test: sdmmc0_testdata-test {
++ rockchip,pins =
++ /* sdmmc0_testdata_out */
++ <1 RK_PC5 6 &pcfg_pull_none>;
++ };
++ };
++
++ sdmmc1_testclk {
++ /omit-if-no-ref/
++ sdmmc1_testclkm0_test: sdmmc1_testclkm0-test {
++ rockchip,pins =
++ /* sdmmc1_testclk_out_m0 */
++ <1 RK_PC4 5 &pcfg_pull_none>;
++ };
++ };
++
++ sdmmc1_testdata {
++ /omit-if-no-ref/
++ sdmmc1_testdatam0_test: sdmmc1_testdatam0-test {
++ rockchip,pins =
++ /* sdmmc1_testdata_out_m0 */
++ <1 RK_PC5 5 &pcfg_pull_none>;
++ };
++ };
++
++ spdif {
++ /omit-if-no-ref/
++ spdifm0_rx0: spdifm0-rx0 {
++ rockchip,pins =
++ /* spdif_rx0_m0 */
++ <4 RK_PB4 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm0_rx1: spdifm0-rx1 {
++ rockchip,pins =
++ /* spdif_rx1_m0 */
++ <3 RK_PB4 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm0_tx0: spdifm0-tx0 {
++ rockchip,pins =
++ /* spdif_tx0_m0 */
++ <4 RK_PB5 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm0_tx1: spdifm0-tx1 {
++ rockchip,pins =
++ /* spdif_tx1_m0 */
++ <3 RK_PB5 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm1_rx0: spdifm1-rx0 {
++ rockchip,pins =
++ /* spdif_rx0_m1 */
++ <4 RK_PA0 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm1_rx1: spdifm1-rx1 {
++ rockchip,pins =
++ /* spdif_rx1_m1 */
++ <3 RK_PA2 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm1_tx0: spdifm1-tx0 {
++ rockchip,pins =
++ /* spdif_tx0_m1 */
++ <4 RK_PA1 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm1_tx1: spdifm1-tx1 {
++ rockchip,pins =
++ /* spdif_tx1_m1 */
++ <3 RK_PA3 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm2_rx0: spdifm2-rx0 {
++ rockchip,pins =
++ /* spdif_rx0_m2 */
++ <2 RK_PD6 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm2_rx1: spdifm2-rx1 {
++ rockchip,pins =
++ /* spdif_rx1_m2 */
++ <1 RK_PD4 6 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm2_tx0: spdifm2-tx0 {
++ rockchip,pins =
++ /* spdif_tx0_m2 */
++ <2 RK_PD7 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm2_tx1: spdifm2-tx1 {
++ rockchip,pins =
++ /* spdif_tx1_m2 */
++ <1 RK_PD5 6 &pcfg_pull_none>;
++ };
++ };
++
++ spi0 {
++ /omit-if-no-ref/
++ spi0m0_pins: spi0m0-pins {
++ rockchip,pins =
++ /* spi0_clk_m0 */
++ <0 RK_PC7 11 &pcfg_pull_none>,
++ /* spi0_miso_m0 */
++ <0 RK_PD1 11 &pcfg_pull_none>,
++ /* spi0_mosi_m0 */
++ <0 RK_PD0 11 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi0m0_csn0: spi0m0-csn0 {
++ rockchip,pins =
++ /* spi0m0_csn0 */
++ <0 RK_PC6 11 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi0m0_csn1: spi0m0-csn1 {
++ rockchip,pins =
++ /* spi0m0_csn1 */
++ <0 RK_PC3 11 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi0m1_pins: spi0m1-pins {
++ rockchip,pins =
++ /* spi0_clk_m1 */
++ <2 RK_PA5 12 &pcfg_pull_none>,
++ /* spi0_miso_m1 */
++ <2 RK_PA1 12 &pcfg_pull_none>,
++ /* spi0_mosi_m1 */
++ <2 RK_PA0 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi0m1_csn0: spi0m1-csn0 {
++ rockchip,pins =
++ /* spi0m1_csn0 */
++ <2 RK_PA4 12 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi0m1_csn1: spi0m1-csn1 {
++ rockchip,pins =
++ /* spi0m1_csn1 */
++ <2 RK_PA2 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi0m2_pins: spi0m2-pins {
++ rockchip,pins =
++ /* spi0_clk_m2 */
++ <1 RK_PA7 9 &pcfg_pull_none>,
++ /* spi0_miso_m2 */
++ <1 RK_PA6 9 &pcfg_pull_none>,
++ /* spi0_mosi_m2 */
++ <1 RK_PA5 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi0m2_csn0: spi0m2-csn0 {
++ rockchip,pins =
++ /* spi0m2_csn0 */
++ <1 RK_PA4 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi0m2_csn1: spi0m2-csn1 {
++ rockchip,pins =
++ /* spi0m2_csn1 */
++ <1 RK_PB2 9 &pcfg_pull_none>;
++ };
++ };
++
++ spi1 {
++ /omit-if-no-ref/
++ spi1m0_pins: spi1m0-pins {
++ rockchip,pins =
++ /* spi1_clk_m0 */
++ <1 RK_PB4 11 &pcfg_pull_none>,
++ /* spi1_miso_m0 */
++ <1 RK_PB6 11 &pcfg_pull_none>,
++ /* spi1_mosi_m0 */
++ <1 RK_PB5 11 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi1m0_csn0: spi1m0-csn0 {
++ rockchip,pins =
++ /* spi1m0_csn0 */
++ <1 RK_PB7 11 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi1m0_csn1: spi1m0-csn1 {
++ rockchip,pins =
++ /* spi1m0_csn1 */
++ <1 RK_PC0 11 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi1m1_pins: spi1m1-pins {
++ rockchip,pins =
++ /* spi1_clk_m1 */
++ <2 RK_PC5 10 &pcfg_pull_none>,
++ /* spi1_miso_m1 */
++ <2 RK_PC3 10 &pcfg_pull_none>,
++ /* spi1_mosi_m1 */
++ <2 RK_PC2 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi1m1_csn0: spi1m1-csn0 {
++ rockchip,pins =
++ /* spi1m1_csn0 */
++ <2 RK_PC4 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi1m1_csn1: spi1m1-csn1 {
++ rockchip,pins =
++ /* spi1m1_csn1 */
++ <2 RK_PC1 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi1m2_pins: spi1m2-pins {
++ rockchip,pins =
++ /* spi1_clk_m2 */
++ <3 RK_PC7 10 &pcfg_pull_none>,
++ /* spi1_miso_m2 */
++ <3 RK_PC5 10 &pcfg_pull_none>,
++ /* spi1_mosi_m2 */
++ <3 RK_PC6 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi1m2_csn0: spi1m2-csn0 {
++ rockchip,pins =
++ /* spi1m2_csn0 */
++ <3 RK_PD0 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi1m2_csn1: spi1m2-csn1 {
++ rockchip,pins =
++ /* spi1m2_csn1 */
++ <4 RK_PA0 10 &pcfg_pull_none>;
++ };
++ };
++
++ spi2 {
++ /omit-if-no-ref/
++ spi2m0_pins: spi2m0-pins {
++ rockchip,pins =
++ /* spi2_clk_m0 */
++ <0 RK_PB2 9 &pcfg_pull_none>,
++ /* spi2_miso_m0 */
++ <0 RK_PB1 9 &pcfg_pull_none>,
++ /* spi2_mosi_m0 */
++ <0 RK_PB3 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi2m0_csn0: spi2m0-csn0 {
++ rockchip,pins =
++ /* spi2m0_csn0 */
++ <0 RK_PB0 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi2m0_csn1: spi2m0-csn1 {
++ rockchip,pins =
++ /* spi2m0_csn1 */
++ <0 RK_PA7 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi2m1_pins: spi2m1-pins {
++ rockchip,pins =
++ /* spi2_clk_m1 */
++ <1 RK_PD5 11 &pcfg_pull_none>,
++ /* spi2_miso_m1 */
++ <1 RK_PC5 11 &pcfg_pull_none>,
++ /* spi2_mosi_m1 */
++ <1 RK_PC4 11 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi2m1_csn0: spi2m1-csn0 {
++ rockchip,pins =
++ /* spi2m1_csn0 */
++ <1 RK_PC3 11 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi2m1_csn1: spi2m1-csn1 {
++ rockchip,pins =
++ /* spi2m1_csn1 */
++ <1 RK_PC2 11 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi2m2_pins: spi2m2-pins {
++ rockchip,pins =
++ /* spi2_clk_m2 */
++ <3 RK_PA4 10 &pcfg_pull_none>,
++ /* spi2_miso_m2 */
++ <3 RK_PC1 10 &pcfg_pull_none>,
++ /* spi2_mosi_m2 */
++ <3 RK_PB0 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi2m2_csn0: spi2m2-csn0 {
++ rockchip,pins =
++ /* spi2m2_csn0 */
++ <3 RK_PC4 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi2m2_csn1: spi2m2-csn1 {
++ rockchip,pins =
++ /* spi2m2_csn1 */
++ <3 RK_PA5 10 &pcfg_pull_none>;
++ };
++ };
++
++ spi3 {
++ /omit-if-no-ref/
++ spi3m0_pins: spi3m0-pins {
++ rockchip,pins =
++ /* spi3_clk_m0 */
++ <3 RK_PA0 10 &pcfg_pull_none>,
++ /* spi3_miso_m0 */
++ <3 RK_PA2 10 &pcfg_pull_none>,
++ /* spi3_mosi_m0 */
++ <3 RK_PA1 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi3m0_csn0: spi3m0-csn0 {
++ rockchip,pins =
++ /* spi3m0_csn0 */
++ <3 RK_PA3 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi3m0_csn1: spi3m0-csn1 {
++ rockchip,pins =
++ /* spi3m0_csn1 */
++ <2 RK_PD7 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi3m1_pins: spi3m1-pins {
++ rockchip,pins =
++ /* spi3_clk_m1 */
++ <3 RK_PD4 10 &pcfg_pull_none>,
++ /* spi3_miso_m1 */
++ <3 RK_PD5 10 &pcfg_pull_none>,
++ /* spi3_mosi_m1 */
++ <3 RK_PD6 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi3m1_csn0: spi3m1-csn0 {
++ rockchip,pins =
++ /* spi3m1_csn0 */
++ <3 RK_PB6 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi3m1_csn1: spi3m1-csn1 {
++ rockchip,pins =
++ /* spi3m1_csn1 */
++ <3 RK_PD7 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi3m2_pins: spi3m2-pins {
++ rockchip,pins =
++ /* spi3_clk_m2 */
++ <4 RK_PA7 9 &pcfg_pull_none>,
++ /* spi3_miso_m2 */
++ <4 RK_PA6 9 &pcfg_pull_none>,
++ /* spi3_mosi_m2 */
++ <4 RK_PA4 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi3m2_csn0: spi3m2-csn0 {
++ rockchip,pins =
++ /* spi3m2_csn0 */
++ <4 RK_PA3 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi3m2_csn1: spi3m2-csn1 {
++ rockchip,pins =
++ /* spi3m2_csn1 */
++ <4 RK_PB3 10 &pcfg_pull_none>;
++ };
++ };
++
++ spi4 {
++ /omit-if-no-ref/
++ spi4m0_pins: spi4m0-pins {
++ rockchip,pins =
++ /* spi4_clk_m0 */
++ <4 RK_PC7 12 &pcfg_pull_none>,
++ /* spi4_miso_m0 */
++ <4 RK_PC6 12 &pcfg_pull_none>,
++ /* spi4_mosi_m0 */
++ <4 RK_PC5 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi4m0_csn0: spi4m0-csn0 {
++ rockchip,pins =
++ /* spi4m0_csn0 */
++ <4 RK_PC4 12 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi4m0_csn1: spi4m0-csn1 {
++ rockchip,pins =
++ /* spi4m0_csn1 */
++ <4 RK_PC0 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi4m1_pins: spi4m1-pins {
++ rockchip,pins =
++ /* spi4_clk_m1 */
++ <3 RK_PD1 10 &pcfg_pull_none>,
++ /* spi4_miso_m1 */
++ <3 RK_PC2 10 &pcfg_pull_none>,
++ /* spi4_mosi_m1 */
++ <3 RK_PC3 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi4m1_csn0: spi4m1-csn0 {
++ rockchip,pins =
++ /* spi4m1_csn0 */
++ <3 RK_PB1 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi4m1_csn1: spi4m1-csn1 {
++ rockchip,pins =
++ /* spi4m1_csn1 */
++ <3 RK_PD2 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi4m2_pins: spi4m2-pins {
++ rockchip,pins =
++ /* spi4_clk_m2 */
++ <4 RK_PB0 9 &pcfg_pull_none>,
++ /* spi4_miso_m2 */
++ <4 RK_PB2 9 &pcfg_pull_none>,
++ /* spi4_mosi_m2 */
++ <4 RK_PB1 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi4m2_csn0: spi4m2-csn0 {
++ rockchip,pins =
++ /* spi4m2_csn0 */
++ <4 RK_PB3 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi4m2_csn1: spi4m2-csn1 {
++ rockchip,pins =
++ /* spi4m2_csn1 */
++ <4 RK_PA5 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi4m3_pins: spi4m3-pins {
++ rockchip,pins =
++ /* spi4_clk_m3 */
++ <2 RK_PB3 10 &pcfg_pull_none>,
++ /* spi4_miso_m3 */
++ <2 RK_PB5 10 &pcfg_pull_none>,
++ /* spi4_mosi_m3 */
++ <2 RK_PB4 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spi4m3_csn0: spi4m3-csn0 {
++ rockchip,pins =
++ /* spi4m3_csn0 */
++ <2 RK_PB2 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ spi4m3_csn1: spi4m3-csn1 {
++ rockchip,pins =
++ /* spi4m3_csn1 */
++ <2 RK_PA6 10 &pcfg_pull_none>;
++ };
++ };
++
++ test_clk {
++ /omit-if-no-ref/
++ test_clk_pins: test_clk-pins {
++ rockchip,pins =
++ /* test_clk_out */
++ <2 RK_PA5 5 &pcfg_pull_none>;
++ };
++ };
++
++ tsadc {
++ /omit-if-no-ref/
++ tsadcm0_pins: tsadcm0-pins {
++ rockchip,pins =
++ /* tsadc_ctrl_m0 */
++ <0 RK_PA1 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ tsadcm1_pins: tsadcm1-pins {
++ rockchip,pins =
++ /* tsadc_ctrl_m1 */
++ <0 RK_PA3 10 &pcfg_pull_none>;
++ };
++ };
++
++ tsadc_ctrl {
++ /omit-if-no-ref/
++ tsadc_ctrl_pins: tsadc_ctrl-pins {
++ rockchip,pins =
++ /* tsadc_ctrl_org */
++ <0 RK_PA1 10 &pcfg_pull_none>;
++ };
++ };
++
++ uart0 {
++ /omit-if-no-ref/
++ uart0m0_xfer: uart0m0-xfer {
++ rockchip,pins =
++ /* uart0_rx_m0 */
++ <0 RK_PD5 9 &pcfg_pull_up>,
++ /* uart0_tx_m0 */
++ <0 RK_PD4 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart0m1_xfer: uart0m1-xfer {
++ rockchip,pins =
++ /* uart0_rx_m1 */
++ <2 RK_PA0 9 &pcfg_pull_up>,
++ /* uart0_tx_m1 */
++ <2 RK_PA1 9 &pcfg_pull_up>;
++ };
++ };
++
++ uart1 {
++ /omit-if-no-ref/
++ uart1m0_xfer: uart1m0-xfer {
++ rockchip,pins =
++ /* uart1_rx_m0 */
++ <0 RK_PC0 10 &pcfg_pull_up>,
++ /* uart1_tx_m0 */
++ <0 RK_PB7 10 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart1m0_ctsn: uart1m0-ctsn {
++ rockchip,pins =
++ /* uart1m0_ctsn */
++ <0 RK_PD2 13 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart1m0_rtsn: uart1m0-rtsn {
++ rockchip,pins =
++ /* uart1m0_rtsn */
++ <0 RK_PD3 13 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart1m1_xfer: uart1m1-xfer {
++ rockchip,pins =
++ /* uart1_rx_m1 */
++ <2 RK_PB1 9 &pcfg_pull_up>,
++ /* uart1_tx_m1 */
++ <2 RK_PB0 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart1m1_ctsn: uart1m1-ctsn {
++ rockchip,pins =
++ /* uart1m1_ctsn */
++ <2 RK_PB2 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart1m1_rtsn: uart1m1-rtsn {
++ rockchip,pins =
++ /* uart1m1_rtsn */
++ <2 RK_PB3 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart1m2_xfer: uart1m2-xfer {
++ rockchip,pins =
++ /* uart1_rx_m2 */
++ <3 RK_PA6 9 &pcfg_pull_up>,
++ /* uart1_tx_m2 */
++ <3 RK_PA7 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart1m2_ctsn: uart1m2-ctsn {
++ rockchip,pins =
++ /* uart1m2_ctsn */
++ <3 RK_PA4 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart1m2_rtsn: uart1m2-rtsn {
++ rockchip,pins =
++ /* uart1m2_rtsn */
++ <3 RK_PA5 9 &pcfg_pull_none>;
++ };
++ };
++
++ uart2 {
++ /omit-if-no-ref/
++ uart2m0_xfer: uart2m0-xfer {
++ rockchip,pins =
++ /* uart2_rx_m0 */
++ <1 RK_PC7 9 &pcfg_pull_up>,
++ /* uart2_tx_m0 */
++ <1 RK_PC6 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart2m0_ctsn: uart2m0-ctsn {
++ rockchip,pins =
++ /* uart2m0_ctsn */
++ <1 RK_PC5 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart2m0_rtsn: uart2m0-rtsn {
++ rockchip,pins =
++ /* uart2m0_rtsn */
++ <1 RK_PC4 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart2m1_xfer: uart2m1-xfer {
++ rockchip,pins =
++ /* uart2_rx_m1 */
++ <4 RK_PB4 10 &pcfg_pull_up>,
++ /* uart2_tx_m1 */
++ <4 RK_PB5 10 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart2m1_ctsn: uart2m1-ctsn {
++ rockchip,pins =
++ /* uart2m1_ctsn */
++ <4 RK_PB1 12 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart2m1_rtsn: uart2m1-rtsn {
++ rockchip,pins =
++ /* uart2m1_rtsn */
++ <4 RK_PB0 12 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart2m2_xfer: uart2m2-xfer {
++ rockchip,pins =
++ /* uart2_rx_m2 */
++ <3 RK_PB7 9 &pcfg_pull_up>,
++ /* uart2_tx_m2 */
++ <3 RK_PC0 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart2m2_ctsn: uart2m2-ctsn {
++ rockchip,pins =
++ /* uart2m2_ctsn */
++ <3 RK_PD3 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart2m2_rtsn: uart2m2-rtsn {
++ rockchip,pins =
++ /* uart2m2_rtsn */
++ <3 RK_PD2 9 &pcfg_pull_none>;
++ };
++ };
++
++ uart3 {
++ /omit-if-no-ref/
++ uart3m0_xfer: uart3m0-xfer {
++ rockchip,pins =
++ /* uart3_rx_m0 */
++ <3 RK_PA1 9 &pcfg_pull_up>,
++ /* uart3_tx_m0 */
++ <3 RK_PA0 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart3m0_ctsn: uart3m0-ctsn {
++ rockchip,pins =
++ /* uart3m0_ctsn */
++ <3 RK_PA2 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart3m0_rtsn: uart3m0-rtsn {
++ rockchip,pins =
++ /* uart3m0_rtsn */
++ <3 RK_PA3 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart3m1_xfer: uart3m1-xfer {
++ rockchip,pins =
++ /* uart3_rx_m1 */
++ <4 RK_PA1 9 &pcfg_pull_up>,
++ /* uart3_tx_m1 */
++ <4 RK_PA0 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart3m1_ctsn: uart3m1-ctsn {
++ rockchip,pins =
++ /* uart3m1_ctsn */
++ <3 RK_PB7 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart3m1_rtsn: uart3m1-rtsn {
++ rockchip,pins =
++ /* uart3m1_rtsn */
++ <3 RK_PC0 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart3m2_xfer: uart3m2-xfer {
++ rockchip,pins =
++ /* uart3_rx_m2 */
++ <1 RK_PC1 9 &pcfg_pull_up>,
++ /* uart3_tx_m2 */
++ <1 RK_PC0 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart3m2_ctsn: uart3m2-ctsn {
++ rockchip,pins =
++ /* uart3m2_ctsn */
++ <1 RK_PB6 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart3m2_rtsn: uart3m2-rtsn {
++ rockchip,pins =
++ /* uart3m2_rtsn */
++ <1 RK_PB7 9 &pcfg_pull_none>;
++ };
++ };
++
++ uart4 {
++ /omit-if-no-ref/
++ uart4m0_xfer: uart4m0-xfer {
++ rockchip,pins =
++ /* uart4_rx_m0 */
++ <2 RK_PD1 9 &pcfg_pull_up>,
++ /* uart4_tx_m0 */
++ <2 RK_PD0 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart4m0_ctsn: uart4m0-ctsn {
++ rockchip,pins =
++ /* uart4m0_ctsn */
++ <2 RK_PC6 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart4m0_rtsn: uart4m0-rtsn {
++ rockchip,pins =
++ /* uart4m0_rtsn */
++ <2 RK_PC7 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart4m1_xfer: uart4m1-xfer {
++ rockchip,pins =
++ /* uart4_rx_m1 */
++ <1 RK_PC5 9 &pcfg_pull_up>,
++ /* uart4_tx_m1 */
++ <1 RK_PC4 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart4m1_ctsn: uart4m1-ctsn {
++ rockchip,pins =
++ /* uart4m1_ctsn */
++ <1 RK_PC3 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart4m1_rtsn: uart4m1-rtsn {
++ rockchip,pins =
++ /* uart4m1_rtsn */
++ <1 RK_PC2 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart4m2_xfer: uart4m2-xfer {
++ rockchip,pins =
++ /* uart4_rx_m2 */
++ <0 RK_PB5 10 &pcfg_pull_up>,
++ /* uart4_tx_m2 */
++ <0 RK_PB4 10 &pcfg_pull_up>;
++ };
++ };
++
++ uart5 {
++ /omit-if-no-ref/
++ uart5m0_xfer: uart5m0-xfer {
++ rockchip,pins =
++ /* uart5_rx_m0 */
++ <3 RK_PD4 9 &pcfg_pull_up>,
++ /* uart5_tx_m0 */
++ <3 RK_PD5 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart5m0_ctsn: uart5m0-ctsn {
++ rockchip,pins =
++ /* uart5m0_ctsn */
++ <3 RK_PD6 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart5m0_rtsn: uart5m0-rtsn {
++ rockchip,pins =
++ /* uart5m0_rtsn */
++ <3 RK_PD7 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart5m1_xfer: uart5m1-xfer {
++ rockchip,pins =
++ /* uart5_rx_m1 */
++ <4 RK_PB1 10 &pcfg_pull_up>,
++ /* uart5_tx_m1 */
++ <4 RK_PB0 10 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart5m1_ctsn: uart5m1-ctsn {
++ rockchip,pins =
++ /* uart5m1_ctsn */
++ <4 RK_PA5 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart5m1_rtsn: uart5m1-rtsn {
++ rockchip,pins =
++ /* uart5m1_rtsn */
++ <4 RK_PA3 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart5m2_xfer: uart5m2-xfer {
++ rockchip,pins =
++ /* uart5_rx_m2 */
++ <2 RK_PA4 9 &pcfg_pull_up>,
++ /* uart5_tx_m2 */
++ <2 RK_PA5 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart5m2_ctsn: uart5m2-ctsn {
++ rockchip,pins =
++ /* uart5m2_ctsn */
++ <2 RK_PA3 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart5m2_rtsn: uart5m2-rtsn {
++ rockchip,pins =
++ /* uart5m2_rtsn */
++ <2 RK_PA2 10 &pcfg_pull_none>;
++ };
++ };
++
++ uart6 {
++ /omit-if-no-ref/
++ uart6m0_xfer: uart6m0-xfer {
++ rockchip,pins =
++ /* uart6_rx_m0 */
++ <4 RK_PA6 10 &pcfg_pull_up>,
++ /* uart6_tx_m0 */
++ <4 RK_PA4 10 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart6m0_ctsn: uart6m0-ctsn {
++ rockchip,pins =
++ /* uart6m0_ctsn */
++ <4 RK_PB1 11 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart6m0_rtsn: uart6m0-rtsn {
++ rockchip,pins =
++ /* uart6m0_rtsn */
++ <4 RK_PB0 11 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart6m1_xfer: uart6m1-xfer {
++ rockchip,pins =
++ /* uart6_rx_m1 */
++ <2 RK_PD3 9 &pcfg_pull_up>,
++ /* uart6_tx_m1 */
++ <2 RK_PD2 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart6m1_ctsn: uart6m1-ctsn {
++ rockchip,pins =
++ /* uart6m1_ctsn */
++ <2 RK_PD5 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart6m1_rtsn: uart6m1-rtsn {
++ rockchip,pins =
++ /* uart6m1_rtsn */
++ <2 RK_PD4 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart6m2_xfer: uart6m2-xfer {
++ rockchip,pins =
++ /* uart6_rx_m2 */
++ <1 RK_PB3 9 &pcfg_pull_up>,
++ /* uart6_tx_m2 */
++ <1 RK_PB0 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart6m2_ctsn: uart6m2-ctsn {
++ rockchip,pins =
++ /* uart6m2_ctsn */
++ <1 RK_PA3 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart6m2_rtsn: uart6m2-rtsn {
++ rockchip,pins =
++ /* uart6m2_rtsn */
++ <1 RK_PA2 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart6m3_xfer: uart6m3-xfer {
++ rockchip,pins =
++ /* uart6_rx_m3 */
++ <4 RK_PC5 13 &pcfg_pull_up>,
++ /* uart6_tx_m3 */
++ <4 RK_PC4 13 &pcfg_pull_up>;
++ };
++ };
++
++ uart7 {
++ /omit-if-no-ref/
++ uart7m0_xfer: uart7m0-xfer {
++ rockchip,pins =
++ /* uart7_rx_m0 */
++ <2 RK_PB7 9 &pcfg_pull_up>,
++ /* uart7_tx_m0 */
++ <2 RK_PB6 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart7m0_ctsn: uart7m0-ctsn {
++ rockchip,pins =
++ /* uart7m0_ctsn */
++ <2 RK_PB4 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart7m0_rtsn: uart7m0-rtsn {
++ rockchip,pins =
++ /* uart7m0_rtsn */
++ <2 RK_PB5 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart7m1_xfer: uart7m1-xfer {
++ rockchip,pins =
++ /* uart7_rx_m1 */
++ <1 RK_PA3 9 &pcfg_pull_up>,
++ /* uart7_tx_m1 */
++ <1 RK_PA2 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart7m1_ctsn: uart7m1-ctsn {
++ rockchip,pins =
++ /* uart7m1_ctsn */
++ <1 RK_PA1 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart7m1_rtsn: uart7m1-rtsn {
++ rockchip,pins =
++ /* uart7m1_rtsn */
++ <1 RK_PA0 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart7m2_xfer: uart7m2-xfer {
++ rockchip,pins =
++ /* uart7_rx_m2 */
++ <2 RK_PA0 10 &pcfg_pull_up>,
++ /* uart7_tx_m2 */
++ <2 RK_PA1 10 &pcfg_pull_up>;
++ };
++ };
++
++ uart8 {
++ /omit-if-no-ref/
++ uart8m0_xfer: uart8m0-xfer {
++ rockchip,pins =
++ /* uart8_rx_m0 */
++ <3 RK_PC5 9 &pcfg_pull_up>,
++ /* uart8_tx_m0 */
++ <3 RK_PC6 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart8m0_ctsn: uart8m0-ctsn {
++ rockchip,pins =
++ /* uart8m0_ctsn */
++ <3 RK_PD0 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart8m0_rtsn: uart8m0-rtsn {
++ rockchip,pins =
++ /* uart8m0_rtsn */
++ <3 RK_PC7 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart8m1_xfer: uart8m1-xfer {
++ rockchip,pins =
++ /* uart8_rx_m1 */
++ <2 RK_PA7 9 &pcfg_pull_up>,
++ /* uart8_tx_m1 */
++ <2 RK_PA6 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart8m1_ctsn: uart8m1-ctsn {
++ rockchip,pins =
++ /* uart8m1_ctsn */
++ <2 RK_PB7 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart8m1_rtsn: uart8m1-rtsn {
++ rockchip,pins =
++ /* uart8m1_rtsn */
++ <2 RK_PB6 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart8m2_xfer: uart8m2-xfer {
++ rockchip,pins =
++ /* uart8_rx_m2 */
++ <0 RK_PC2 10 &pcfg_pull_up>,
++ /* uart8_tx_m2 */
++ <0 RK_PC1 10 &pcfg_pull_up>;
++ };
++ };
++
++ uart9 {
++ /omit-if-no-ref/
++ uart9m0_xfer: uart9m0-xfer {
++ rockchip,pins =
++ /* uart9_rx_m0 */
++ <2 RK_PC0 9 &pcfg_pull_up>,
++ /* uart9_tx_m0 */
++ <2 RK_PC1 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart9m0_ctsn: uart9m0-ctsn {
++ rockchip,pins =
++ /* uart9m0_ctsn */
++ <2 RK_PD7 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart9m0_rtsn: uart9m0-rtsn {
++ rockchip,pins =
++ /* uart9m0_rtsn */
++ <2 RK_PD6 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart9m1_xfer: uart9m1-xfer {
++ rockchip,pins =
++ /* uart9_rx_m1 */
++ <3 RK_PB2 9 &pcfg_pull_up>,
++ /* uart9_tx_m1 */
++ <3 RK_PB3 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart9m1_ctsn: uart9m1-ctsn {
++ rockchip,pins =
++ /* uart9m1_ctsn */
++ <3 RK_PB5 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart9m1_rtsn: uart9m1-rtsn {
++ rockchip,pins =
++ /* uart9m1_rtsn */
++ <3 RK_PB4 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart9m2_xfer: uart9m2-xfer {
++ rockchip,pins =
++ /* uart9_rx_m2 */
++ <4 RK_PC3 13 &pcfg_pull_up>,
++ /* uart9_tx_m2 */
++ <4 RK_PC2 13 &pcfg_pull_up>;
++ };
++ };
++
++ uart10 {
++ /omit-if-no-ref/
++ uart10m0_xfer: uart10m0-xfer {
++ rockchip,pins =
++ /* uart10_rx_m0 */
++ <3 RK_PB0 9 &pcfg_pull_up>,
++ /* uart10_tx_m0 */
++ <3 RK_PB1 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart10m0_ctsn: uart10m0-ctsn {
++ rockchip,pins =
++ /* uart10m0_ctsn */
++ <3 RK_PA6 10 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart10m0_rtsn: uart10m0-rtsn {
++ rockchip,pins =
++ /* uart10m0_rtsn */
++ <3 RK_PA7 10 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart10m1_xfer: uart10m1-xfer {
++ rockchip,pins =
++ /* uart10_rx_m1 */
++ <1 RK_PD1 9 &pcfg_pull_up>,
++ /* uart10_tx_m1 */
++ <1 RK_PD0 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart10m1_ctsn: uart10m1-ctsn {
++ rockchip,pins =
++ /* uart10m1_ctsn */
++ <1 RK_PD5 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart10m1_rtsn: uart10m1-rtsn {
++ rockchip,pins =
++ /* uart10m1_rtsn */
++ <1 RK_PD4 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart10m2_xfer: uart10m2-xfer {
++ rockchip,pins =
++ /* uart10_rx_m2 */
++ <0 RK_PC5 10 &pcfg_pull_up>,
++ /* uart10_tx_m2 */
++ <0 RK_PC4 10 &pcfg_pull_up>;
++ };
++ };
++
++ uart11 {
++ /omit-if-no-ref/
++ uart11m0_xfer: uart11m0-xfer {
++ rockchip,pins =
++ /* uart11_rx_m0 */
++ <3 RK_PC1 9 &pcfg_pull_up>,
++ /* uart11_tx_m0 */
++ <3 RK_PC4 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart11m0_ctsn: uart11m0-ctsn {
++ rockchip,pins =
++ /* uart11m0_ctsn */
++ <3 RK_PC3 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart11m0_rtsn: uart11m0-rtsn {
++ rockchip,pins =
++ /* uart11m0_rtsn */
++ <3 RK_PC2 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart11m1_xfer: uart11m1-xfer {
++ rockchip,pins =
++ /* uart11_rx_m1 */
++ <2 RK_PC5 9 &pcfg_pull_up>,
++ /* uart11_tx_m1 */
++ <2 RK_PC4 9 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart11m1_ctsn: uart11m1-ctsn {
++ rockchip,pins =
++ /* uart11m1_ctsn */
++ <2 RK_PC2 9 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart11m1_rtsn: uart11m1-rtsn {
++ rockchip,pins =
++ /* uart11m1_rtsn */
++ <2 RK_PC3 9 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart11m2_xfer: uart11m2-xfer {
++ rockchip,pins =
++ /* uart11_rx_m2 */
++ <4 RK_PC1 13 &pcfg_pull_up>,
++ /* uart11_tx_m2 */
++ <4 RK_PC0 13 &pcfg_pull_up>;
++ };
++ };
++
++ ufs {
++ /omit-if-no-ref/
++ ufs_refclk: ufs-refclk {
++ rockchip,pins =
++ /* ufs_refclk */
++ <4 RK_PD1 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ ufs_rst: ufs-rst {
++ rockchip,pins =
++ /* ufs_rstn */
++ <4 RK_PD0 1 &pcfg_pull_none>;
++ };
++ };
++
++ ufs_testdata0 {
++ /omit-if-no-ref/
++ ufs_testdata0_test: ufs_testdata0-test {
++ rockchip,pins =
++ /* ufs_testdata0_out */
++ <4 RK_PC4 4 &pcfg_pull_none>;
++ };
++ };
++
++ ufs_testdata1 {
++ /omit-if-no-ref/
++ ufs_testdata1_test: ufs_testdata1-test {
++ rockchip,pins =
++ /* ufs_testdata1_out */
++ <4 RK_PC5 4 &pcfg_pull_none>;
++ };
++ };
++
++ ufs_testdata2 {
++ /omit-if-no-ref/
++ ufs_testdata2_test: ufs_testdata2-test {
++ rockchip,pins =
++ /* ufs_testdata2_out */
++ <4 RK_PC6 4 &pcfg_pull_none>;
++ };
++ };
++
++ ufs_testdata3 {
++ /omit-if-no-ref/
++ ufs_testdata3_test: ufs_testdata3-test {
++ rockchip,pins =
++ /* ufs_testdata3_out */
++ <4 RK_PC7 4 &pcfg_pull_none>;
++ };
++ };
++
++ vi_cif {
++ /omit-if-no-ref/
++ vi_cif_pins: vi_cif-pins {
++ rockchip,pins =
++ /* vi_cif_clki */
++ <3 RK_PA3 1 &pcfg_pull_none>,
++ /* vi_cif_clko */
++ <3 RK_PA2 1 &pcfg_pull_none>,
++ /* vi_cif_d0 */
++ <2 RK_PC5 1 &pcfg_pull_none>,
++ /* vi_cif_d1 */
++ <2 RK_PC4 1 &pcfg_pull_none>,
++ /* vi_cif_d2 */
++ <2 RK_PC3 1 &pcfg_pull_none>,
++ /* vi_cif_d3 */
++ <2 RK_PC2 1 &pcfg_pull_none>,
++ /* vi_cif_d4 */
++ <2 RK_PC1 1 &pcfg_pull_none>,
++ /* vi_cif_d5 */
++ <2 RK_PC0 1 &pcfg_pull_none>,
++ /* vi_cif_d6 */
++ <2 RK_PB7 1 &pcfg_pull_none>,
++ /* vi_cif_d7 */
++ <2 RK_PB6 1 &pcfg_pull_none>,
++ /* vi_cif_d8 */
++ <2 RK_PB5 1 &pcfg_pull_none>,
++ /* vi_cif_d9 */
++ <2 RK_PB4 1 &pcfg_pull_none>,
++ /* vi_cif_d10 */
++ <2 RK_PB3 1 &pcfg_pull_none>,
++ /* vi_cif_d11 */
++ <2 RK_PB2 1 &pcfg_pull_none>,
++ /* vi_cif_d12 */
++ <2 RK_PB1 1 &pcfg_pull_none>,
++ /* vi_cif_d13 */
++ <2 RK_PB0 1 &pcfg_pull_none>,
++ /* vi_cif_d14 */
++ <2 RK_PA7 1 &pcfg_pull_none>,
++ /* vi_cif_d15 */
++ <2 RK_PA6 1 &pcfg_pull_none>,
++ /* vi_cif_href */
++ <3 RK_PA0 1 &pcfg_pull_none>,
++ /* vi_cif_vsync */
++ <3 RK_PA1 1 &pcfg_pull_none>;
++ };
++ };
++
++ vo_lcdc {
++ /omit-if-no-ref/
++ vo_lcdc_pins: vo_lcdc-pins {
++ rockchip,pins =
++ /* vo_lcdc_clk */
++ <3 RK_PD7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d0 */
++ <3 RK_PD3 1 &pcfg_pull_none>,
++ /* vo_lcdc_d1 */
++ <3 RK_PD2 1 &pcfg_pull_none>,
++ /* vo_lcdc_d2 */
++ <3 RK_PD1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d3 */
++ <3 RK_PD0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d4 */
++ <3 RK_PC7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d5 */
++ <3 RK_PC6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d6 */
++ <3 RK_PC5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d7 */
++ <3 RK_PC4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d8 */
++ <3 RK_PC3 1 &pcfg_pull_none>,
++ /* vo_lcdc_d9 */
++ <3 RK_PC2 1 &pcfg_pull_none>,
++ /* vo_lcdc_d10 */
++ <3 RK_PC1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d11 */
++ <3 RK_PC0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d12 */
++ <3 RK_PB7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d13 */
++ <3 RK_PB6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d14 */
++ <3 RK_PB5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d15 */
++ <3 RK_PB4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d16 */
++ <3 RK_PB3 1 &pcfg_pull_none>,
++ /* vo_lcdc_d17 */
++ <3 RK_PB2 1 &pcfg_pull_none>,
++ /* vo_lcdc_d18 */
++ <3 RK_PB1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d19 */
++ <3 RK_PB0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d20 */
++ <3 RK_PA7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d21 */
++ <3 RK_PA6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d22 */
++ <3 RK_PA5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d23 */
++ <3 RK_PA4 1 &pcfg_pull_none>,
++ /* vo_lcdc_den */
++ <3 RK_PD4 1 &pcfg_pull_none>,
++ /* vo_lcdc_hsync */
++ <3 RK_PD5 1 &pcfg_pull_none>,
++ /* vo_lcdc_vsync */
++ <3 RK_PD6 1 &pcfg_pull_none>;
++ };
++ };
++
++ vo_post {
++ /omit-if-no-ref/
++ vo_post_pins: vo_post-pins {
++ rockchip,pins =
++ /* vo_post_empty */
++ <4 RK_PA1 1 &pcfg_pull_none>;
++ };
++ };
++
++ vp0_sync {
++ /omit-if-no-ref/
++ vp0_sync_pins: vp0_sync-pins {
++ rockchip,pins =
++ /* vp0_sync_out */
++ <4 RK_PC5 3 &pcfg_pull_none>;
++ };
++ };
++
++ vp1_sync {
++ /omit-if-no-ref/
++ vp1_sync_pins: vp1_sync-pins {
++ rockchip,pins =
++ /* vp1_sync_out */
++ <4 RK_PC6 3 &pcfg_pull_none>;
++ };
++ };
++
++ vp2_sync {
++ /omit-if-no-ref/
++ vp2_sync_pins: vp2_sync-pins {
++ rockchip,pins =
++ /* vp2_sync_out */
++ <4 RK_PC7 3 &pcfg_pull_none>;
++ };
++ };
++};
++
++/*
++ * This part is edited handly.
++ */
++&pinctrl {
++ pmic {
++ /omit-if-no-ref/
++ pmic_pins: pmic-pins {
++ rockchip,pins =
++ /* pmic_int */
++ <0 RK_PA6 9 &pcfg_pull_up>,
++ /* pmic_sleep */
++ <0 RK_PA4 9 &pcfg_pull_none>;
++ };
++ };
++
++ vo {
++ /omit-if-no-ref/
++ bt1120_pins: bt1120-pins {
++ rockchip,pins =
++ /* vo_lcdc_clk */
++ <3 RK_PD7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d3 */
++ <3 RK_PD0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d4 */
++ <3 RK_PC7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d5 */
++ <3 RK_PC6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d6 */
++ <3 RK_PC5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d7 */
++ <3 RK_PC4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d10 */
++ <3 RK_PC1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d11 */
++ <3 RK_PC0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d12 */
++ <3 RK_PB7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d13 */
++ <3 RK_PB6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d14 */
++ <3 RK_PB5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d15 */
++ <3 RK_PB4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d19 */
++ <3 RK_PB0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d20 */
++ <3 RK_PA7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d21 */
++ <3 RK_PA6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d22 */
++ <3 RK_PA5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d23 */
++ <3 RK_PA4 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ bt656_pins: bt656-pins {
++ rockchip,pins =
++ /* vo_lcdc_clk */
++ <3 RK_PD7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d3 */
++ <3 RK_PD0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d4 */
++ <3 RK_PC7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d5 */
++ <3 RK_PC6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d6 */
++ <3 RK_PC5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d7 */
++ <3 RK_PC4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d10 */
++ <3 RK_PC1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d11 */
++ <3 RK_PC0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d12 */
++ <3 RK_PB7 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ rgb3x8_pins_m0: rgb3x8-pins-m0 {
++ rockchip,pins =
++ /* vo_lcdc_clk */
++ <3 RK_PD7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d3 */
++ <3 RK_PD0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d4 */
++ <3 RK_PC7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d5 */
++ <3 RK_PC6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d6 */
++ <3 RK_PC5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d7 */
++ <3 RK_PC4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d10 */
++ <3 RK_PC1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d11 */
++ <3 RK_PC0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d12 */
++ <3 RK_PB7 1 &pcfg_pull_none>,
++ /* vo_lcdc_den */
++ <3 RK_PD4 1 &pcfg_pull_none>,
++ /* vo_lcdc_hsync */
++ <3 RK_PD5 1 &pcfg_pull_none>,
++ /* vo_lcdc_vsync */
++ <3 RK_PD6 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ rgb3x8_pins_m1: rgb3x8-pins-m1 {
++ rockchip,pins =
++ /* vo_lcdc_clk */
++ <3 RK_PD7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d13 */
++ <3 RK_PB6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d14 */
++ <3 RK_PB5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d15 */
++ <3 RK_PB4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d19 */
++ <3 RK_PB0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d20 */
++ <3 RK_PA7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d21 */
++ <3 RK_PA6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d22 */
++ <3 RK_PA5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d23 */
++ <3 RK_PA4 1 &pcfg_pull_none>,
++ /* vo_lcdc_den */
++ <3 RK_PD4 1 &pcfg_pull_none>,
++ /* vo_lcdc_hsync */
++ <3 RK_PD5 1 &pcfg_pull_none>,
++ /* vo_lcdc_vsync */
++ <3 RK_PD6 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ rgb565_pins: rgb565-pins {
++ rockchip,pins =
++ /* vo_lcdc_clk */
++ <3 RK_PD7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d3 */
++ <3 RK_PD0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d4 */
++ <3 RK_PC7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d5 */
++ <3 RK_PC6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d6 */
++ <3 RK_PC5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d7 */
++ <3 RK_PC4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d10 */
++ <3 RK_PC1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d11 */
++ <3 RK_PC0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d12 */
++ <3 RK_PB7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d13 */
++ <3 RK_PB6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d14 */
++ <3 RK_PB5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d15 */
++ <3 RK_PB4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d19 */
++ <3 RK_PB0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d20 */
++ <3 RK_PA7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d21 */
++ <3 RK_PA6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d22 */
++ <3 RK_PA5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d23 */
++ <3 RK_PA4 1 &pcfg_pull_none>,
++ /* vo_lcdc_den */
++ <3 RK_PD4 1 &pcfg_pull_none>,
++ /* vo_lcdc_hsync */
++ <3 RK_PD5 1 &pcfg_pull_none>,
++ /* vo_lcdc_vsync */
++ <3 RK_PD6 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ rgb666_pins: rgb666-pins {
++ rockchip,pins =
++ /* vo_lcdc_clk */
++ <3 RK_PD7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d2 */
++ <3 RK_PD1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d3 */
++ <3 RK_PD0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d4 */
++ <3 RK_PC7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d5 */
++ <3 RK_PC6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d6 */
++ <3 RK_PC5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d7 */
++ <3 RK_PC4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d10 */
++ <3 RK_PC1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d11 */
++ <3 RK_PC0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d12 */
++ <3 RK_PB7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d13 */
++ <3 RK_PB6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d14 */
++ <3 RK_PB5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d15 */
++ <3 RK_PB4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d18 */
++ <3 RK_PB1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d19 */
++ <3 RK_PB0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d20 */
++ <3 RK_PA7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d21 */
++ <3 RK_PA6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d22 */
++ <3 RK_PA5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d23 */
++ <3 RK_PA4 1 &pcfg_pull_none>,
++ /* vo_lcdc_den */
++ <3 RK_PD4 1 &pcfg_pull_none>,
++ /* vo_lcdc_hsync */
++ <3 RK_PD5 1 &pcfg_pull_none>,
++ /* vo_lcdc_vsync */
++ <3 RK_PD6 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ rgb888_pins: rgb888-pins {
++ rockchip,pins =
++ /* vo_lcdc_clk */
++ <3 RK_PD7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d0 */
++ <3 RK_PD3 1 &pcfg_pull_none>,
++ /* vo_lcdc_d1 */
++ <3 RK_PD2 1 &pcfg_pull_none>,
++ /* vo_lcdc_d2 */
++ <3 RK_PD1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d3 */
++ <3 RK_PD0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d4 */
++ <3 RK_PC7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d5 */
++ <3 RK_PC6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d6 */
++ <3 RK_PC5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d7 */
++ <3 RK_PC4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d8 */
++ <3 RK_PC3 1 &pcfg_pull_none>,
++ /* vo_lcdc_d9 */
++ <3 RK_PC2 1 &pcfg_pull_none>,
++ /* vo_lcdc_d10 */
++ <3 RK_PC1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d11 */
++ <3 RK_PC0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d12 */
++ <3 RK_PB7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d13 */
++ <3 RK_PB6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d14 */
++ <3 RK_PB5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d15 */
++ <3 RK_PB4 1 &pcfg_pull_none>,
++ /* vo_lcdc_d16 */
++ <3 RK_PB3 1 &pcfg_pull_none>,
++ /* vo_lcdc_d17 */
++ <3 RK_PB2 1 &pcfg_pull_none>,
++ /* vo_lcdc_d18 */
++ <3 RK_PB1 1 &pcfg_pull_none>,
++ /* vo_lcdc_d19 */
++ <3 RK_PB0 1 &pcfg_pull_none>,
++ /* vo_lcdc_d20 */
++ <3 RK_PA7 1 &pcfg_pull_none>,
++ /* vo_lcdc_d21 */
++ <3 RK_PA6 1 &pcfg_pull_none>,
++ /* vo_lcdc_d22 */
++ <3 RK_PA5 1 &pcfg_pull_none>,
++ /* vo_lcdc_d23 */
++ <3 RK_PA4 1 &pcfg_pull_none>,
++ /* vo_lcdc_den */
++ <3 RK_PD4 1 &pcfg_pull_none>,
++ /* vo_lcdc_hsync */
++ <3 RK_PD5 1 &pcfg_pull_none>,
++ /* vo_lcdc_vsync */
++ <3 RK_PD6 1 &pcfg_pull_none>;
++ };
++ };
++
++ vo_ebc {
++ /omit-if-no-ref/
++ vo_ebc_pins: vo_ebc-pins {
++ rockchip,pins =
++ /* vo_ebc_gdclk */
++ <3 RK_PD5 2 &pcfg_pull_none>,
++ /* vo_ebc_gdoe */
++ <3 RK_PA6 2 &pcfg_pull_none>,
++ /* vo_ebc_gdsp */
++ <3 RK_PA5 2 &pcfg_pull_none>,
++ /* vo_ebc_sdce0 */
++ <3 RK_PB3 2 &pcfg_pull_none>,
++ /* vo_ebc_sdclk */
++ <3 RK_PD6 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo0 */
++ <3 RK_PD3 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo1 */
++ <3 RK_PD2 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo2 */
++ <3 RK_PD1 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo3 */
++ <3 RK_PD0 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo4 */
++ <3 RK_PC7 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo5 */
++ <3 RK_PC6 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo6 */
++ <3 RK_PC5 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo7 */
++ <3 RK_PC4 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo8 */
++ <3 RK_PC3 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo9 */
++ <3 RK_PC2 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo10 */
++ <3 RK_PC1 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo11 */
++ <3 RK_PC0 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo12 */
++ <3 RK_PB7 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo13 */
++ <3 RK_PB6 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo14 */
++ <3 RK_PB5 2 &pcfg_pull_none>,
++ /* vo_ebc_sddo15 */
++ <3 RK_PB4 2 &pcfg_pull_none>,
++ /* vo_ebc_sdle */
++ <3 RK_PD4 2 &pcfg_pull_none>,
++ /* vo_ebc_sdoe */
++ <3 RK_PD7 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ vo_ebc_extern: vo_ebc-extern {
++ rockchip,pins =
++ /* vo_ebc_sdce1 */
++ <3 RK_PB2 2 &pcfg_pull_none>,
++ /* vo_ebc_sdce2 */
++ <3 RK_PB1 2 &pcfg_pull_none>,
++ /* vo_ebc_sdce3 */
++ <3 RK_PB0 2 &pcfg_pull_none>,
++ /* vo_ebc_sdshr */
++ <3 RK_PA4 2 &pcfg_pull_none>,
++ /* vo_ebc_vcom */
++ <3 RK_PA7 2 &pcfg_pull_none>;
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -0,0 +1,1678 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
++ */
++
++#include <dt-bindings/clock/rockchip,rk3576-cru.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/phy/phy.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/power/rockchip,rk3576-power.h>
++#include <dt-bindings/reset/rockchip,rk3576-cru.h>
++#include <dt-bindings/soc/rockchip,boot-mode.h>
++
++/ {
++ compatible = "rockchip,rk3576";
++
++ interrupt-parent = <&gic>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ aliases {
++ i2c0 = &i2c0;
++ i2c1 = &i2c1;
++ i2c2 = &i2c2;
++ i2c3 = &i2c3;
++ i2c4 = &i2c4;
++ i2c5 = &i2c5;
++ i2c6 = &i2c6;
++ i2c7 = &i2c7;
++ i2c8 = &i2c8;
++ i2c9 = &i2c9;
++ serial0 = &uart0;
++ serial1 = &uart1;
++ serial2 = &uart2;
++ serial3 = &uart3;
++ serial4 = &uart4;
++ serial5 = &uart5;
++ serial6 = &uart6;
++ serial7 = &uart7;
++ serial8 = &uart8;
++ serial9 = &uart9;
++ serial10 = &uart10;
++ serial11 = &uart11;
++ spi0 = &spi0;
++ spi1 = &spi1;
++ spi2 = &spi2;
++ spi3 = &spi3;
++ spi4 = &spi4;
++ };
++
++ xin32k: clock-xin32k {
++ compatible = "fixed-clock";
++ clock-frequency = <32768>;
++ clock-output-names = "xin32k";
++ #clock-cells = <0>;
++ };
++
++ xin24m: clock-xin24m {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <24000000>;
++ clock-output-names = "xin24m";
++ };
++
++ spll: clock-spll {
++ compatible = "fixed-clock";
++ #clock-cells = <0>;
++ clock-frequency = <702000000>;
++ clock-output-names = "spll";
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu-map {
++ cluster0 {
++ core0 {
++ cpu = <&cpu_l0>;
++ };
++ core1 {
++ cpu = <&cpu_l1>;
++ };
++ core2 {
++ cpu = <&cpu_l2>;
++ };
++ core3 {
++ cpu = <&cpu_l3>;
++ };
++ };
++ cluster1 {
++ core0 {
++ cpu = <&cpu_b0>;
++ };
++ core1 {
++ cpu = <&cpu_b1>;
++ };
++ core2 {
++ cpu = <&cpu_b2>;
++ };
++ core3 {
++ cpu = <&cpu_b3>;
++ };
++ };
++ };
++
++ cpu_l0: cpu@0 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a53";
++ reg = <0x0>;
++ enable-method = "psci";
++ capacity-dmips-mhz = <485>;
++ clocks = <&scmi_clk ARMCLK_L>;
++ operating-points-v2 = <&cluster0_opp_table>;
++ #cooling-cells = <2>;
++ dynamic-power-coefficient = <120>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ };
++
++ cpu_l1: cpu@1 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a53";
++ reg = <0x1>;
++ enable-method = "psci";
++ capacity-dmips-mhz = <485>;
++ clocks = <&scmi_clk ARMCLK_L>;
++ operating-points-v2 = <&cluster0_opp_table>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ };
++
++ cpu_l2: cpu@2 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a53";
++ reg = <0x2>;
++ enable-method = "psci";
++ capacity-dmips-mhz = <485>;
++ clocks = <&scmi_clk ARMCLK_L>;
++ operating-points-v2 = <&cluster0_opp_table>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ };
++
++ cpu_l3: cpu@3 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a53";
++ reg = <0x3>;
++ enable-method = "psci";
++ capacity-dmips-mhz = <485>;
++ clocks = <&scmi_clk ARMCLK_L>;
++ operating-points-v2 = <&cluster0_opp_table>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ };
++
++ cpu_b0: cpu@100 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72";
++ reg = <0x100>;
++ enable-method = "psci";
++ capacity-dmips-mhz = <1024>;
++ clocks = <&scmi_clk ARMCLK_B>;
++ operating-points-v2 = <&cluster1_opp_table>;
++ #cooling-cells = <2>;
++ dynamic-power-coefficient = <320>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ };
++
++ cpu_b1: cpu@101 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72";
++ reg = <0x101>;
++ enable-method = "psci";
++ capacity-dmips-mhz = <1024>;
++ clocks = <&scmi_clk ARMCLK_B>;
++ operating-points-v2 = <&cluster1_opp_table>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ };
++
++ cpu_b2: cpu@102 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72";
++ reg = <0x102>;
++ enable-method = "psci";
++ capacity-dmips-mhz = <1024>;
++ clocks = <&scmi_clk ARMCLK_B>;
++ operating-points-v2 = <&cluster1_opp_table>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ };
++
++ cpu_b3: cpu@103 {
++ device_type = "cpu";
++ compatible = "arm,cortex-a72";
++ reg = <0x103>;
++ enable-method = "psci";
++ capacity-dmips-mhz = <1024>;
++ clocks = <&scmi_clk ARMCLK_B>;
++ operating-points-v2 = <&cluster1_opp_table>;
++ cpu-idle-states = <&CPU_SLEEP>;
++ };
++
++ idle-states {
++ entry-method = "psci";
++
++ CPU_SLEEP: cpu-sleep {
++ compatible = "arm,idle-state";
++ arm,psci-suspend-param = <0x0010000>;
++ entry-latency-us = <120>;
++ exit-latency-us = <250>;
++ min-residency-us = <900>;
++ local-timer-stop;
++ };
++ };
++ };
++
++ cluster0_opp_table: opp-table-cluster0 {
++ compatible = "operating-points-v2";
++ opp-shared;
++
++ opp-408000000 {
++ opp-hz = /bits/ 64 <408000000>;
++ opp-microvolt = <700000 700000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-600000000 {
++ opp-hz = /bits/ 64 <600000000>;
++ opp-microvolt = <700000 700000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-816000000 {
++ opp-hz = /bits/ 64 <816000000>;
++ opp-microvolt = <700000 700000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1008000000 {
++ opp-hz = /bits/ 64 <1008000000>;
++ opp-microvolt = <700000 700000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1200000000 {
++ opp-hz = /bits/ 64 <1200000000>;
++ opp-microvolt = <700000 700000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1416000000 {
++ opp-hz = /bits/ 64 <1416000000>;
++ opp-microvolt = <725000 725000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1608000000 {
++ opp-hz = /bits/ 64 <1608000000>;
++ opp-microvolt = <750000 750000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1800000000 {
++ opp-hz = /bits/ 64 <1800000000>;
++ opp-microvolt = <825000 825000 950000>;
++ clock-latency-ns = <40000>;
++ opp-suspend;
++ };
++
++ opp-2016000000 {
++ opp-hz = /bits/ 64 <2016000000>;
++ opp-microvolt = <900000 900000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-2208000000 {
++ opp-hz = /bits/ 64 <2208000000>;
++ opp-microvolt = <950000 950000 950000>;
++ clock-latency-ns = <40000>;
++ };
++ };
++
++ cluster1_opp_table: opp-table-cluster1 {
++ compatible = "operating-points-v2";
++ opp-shared;
++
++ opp-408000000 {
++ opp-hz = /bits/ 64 <408000000>;
++ opp-microvolt = <700000 700000 950000>;
++ clock-latency-ns = <40000>;
++ opp-suspend;
++ };
++
++ opp-600000000 {
++ opp-hz = /bits/ 64 <600000000>;
++ opp-microvolt = <700000 700000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-816000000 {
++ opp-hz = /bits/ 64 <816000000>;
++ opp-microvolt = <700000 700000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1008000000 {
++ opp-hz = /bits/ 64 <1008000000>;
++ opp-microvolt = <700000 700000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1200000000 {
++ opp-hz = /bits/ 64 <1200000000>;
++ opp-microvolt = <700000 700000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1416000000 {
++ opp-hz = /bits/ 64 <1416000000>;
++ opp-microvolt = <712500 712500 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1608000000 {
++ opp-hz = /bits/ 64 <1608000000>;
++ opp-microvolt = <737500 737500 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1800000000 {
++ opp-hz = /bits/ 64 <1800000000>;
++ opp-microvolt = <800000 800000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-2016000000 {
++ opp-hz = /bits/ 64 <2016000000>;
++ opp-microvolt = <862500 862500 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-2208000000 {
++ opp-hz = /bits/ 64 <2208000000>;
++ opp-microvolt = <925000 925000 950000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-2304000000 {
++ opp-hz = /bits/ 64 <2304000000>;
++ opp-microvolt = <950000 950000 950000>;
++ clock-latency-ns = <40000>;
++ };
++ };
++
++ gpu_opp_table: opp-table-gpu {
++ compatible = "operating-points-v2";
++
++ opp-300000000 {
++ opp-hz = /bits/ 64 <300000000>;
++ opp-microvolt = <700000 700000 850000>;
++ };
++
++ opp-400000000 {
++ opp-hz = /bits/ 64 <400000000>;
++ opp-microvolt = <700000 700000 850000>;
++ };
++
++ opp-500000000 {
++ opp-hz = /bits/ 64 <500000000>;
++ opp-microvolt = <700000 700000 850000>;
++ };
++
++ opp-600000000 {
++ opp-hz = /bits/ 64 <600000000>;
++ opp-microvolt = <700000 700000 850000>;
++ };
++
++ opp-700000000 {
++ opp-hz = /bits/ 64 <700000000>;
++ opp-microvolt = <725000 725000 850000>;
++ };
++
++ opp-800000000 {
++ opp-hz = /bits/ 64 <800000000>;
++ opp-microvolt = <775000 775000 850000>;
++ };
++
++ opp-900000000 {
++ opp-hz = /bits/ 64 <900000000>;
++ opp-microvolt = <825000 825000 850000>;
++ };
++
++ opp-950000000 {
++ opp-hz = /bits/ 64 <950000000>;
++ opp-microvolt = <850000 850000 850000>;
++ };
++ };
++
++ firmware {
++ scmi: scmi {
++ compatible = "arm,scmi-smc";
++ arm,smc-id = <0x82000010>;
++ shmem = <&scmi_shmem>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ scmi_clk: protocol@14 {
++ reg = <0x14>;
++ #clock-cells = <1>;
++ };
++ };
++ };
++
++ pmu_a53: pmu-a53 {
++ compatible = "arm,cortex-a53-pmu";
++ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>;
++ };
++
++ pmu_a72: pmu-a72 {
++ compatible = "arm,cortex-a72-pmu";
++ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
++ };
++
++ psci {
++ compatible = "arm,psci-1.0";
++ method = "smc";
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
++ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
++ };
++
++ soc {
++ compatible = "simple-bus";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ sys_grf: syscon@2600a000 {
++ compatible = "rockchip,rk3576-sys-grf", "syscon";
++ reg = <0x0 0x2600a000 0x0 0x2000>;
++ };
++
++ bigcore_grf: syscon@2600c000 {
++ compatible = "rockchip,rk3576-bigcore-grf", "syscon";
++ reg = <0x0 0x2600c000 0x0 0x2000>;
++ };
++
++ litcore_grf: syscon@2600e000 {
++ compatible = "rockchip,rk3576-litcore-grf", "syscon";
++ reg = <0x0 0x2600e000 0x0 0x2000>;
++ };
++
++ cci_grf: syscon@26010000 {
++ compatible = "rockchip,rk3576-cci-grf", "syscon";
++ reg = <0x0 0x26010000 0x0 0x2000>;
++ };
++
++ gpu_grf: syscon@26016000 {
++ compatible = "rockchip,rk3576-gpu-grf", "syscon";
++ reg = <0x0 0x26016000 0x0 0x2000>;
++ };
++
++ npu_grf: syscon@26018000 {
++ compatible = "rockchip,rk3576-npu-grf", "syscon";
++ reg = <0x0 0x26018000 0x0 0x2000>;
++ };
++
++ vo0_grf: syscon@2601a000 {
++ compatible = "rockchip,rk3576-vo0-grf", "syscon";
++ reg = <0x0 0x2601a000 0x0 0x2000>;
++ };
++
++ usb_grf: syscon@2601e000 {
++ compatible = "rockchip,rk3576-usb-grf", "syscon";
++ reg = <0x0 0x2601e000 0x0 0x1000>;
++ };
++
++ php_grf: syscon@26020000 {
++ compatible = "rockchip,rk3576-php-grf", "syscon";
++ reg = <0x0 0x26020000 0x0 0x2000>;
++ };
++
++ pmu0_grf: syscon@26024000 {
++ compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd";
++ reg = <0x0 0x26024000 0x0 0x1000>;
++ };
++
++ pmu1_grf: syscon@26026000 {
++ compatible = "rockchip,rk3576-pmu1-grf", "syscon";
++ reg = <0x0 0x26026000 0x0 0x1000>;
++ };
++
++ pipe_phy0_grf: syscon@26028000 {
++ compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
++ reg = <0x0 0x26028000 0x0 0x2000>;
++ };
++
++ pipe_phy1_grf: syscon@2602a000 {
++ compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
++ reg = <0x0 0x2602a000 0x0 0x2000>;
++ };
++
++ usbdpphy_grf: syscon@2602c000 {
++ compatible = "rockchip,rk3576-usbdpphy-grf", "syscon";
++ reg = <0x0 0x2602c000 0x0 0x2000>;
++ };
++
++ sdgmac_grf: syscon@26038000 {
++ compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
++ reg = <0x0 0x26038000 0x0 0x1000>;
++ };
++
++ ioc_grf: syscon@26040000 {
++ compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
++ reg = <0x0 0x26040000 0x0 0xc000>;
++ };
++
++ cru: clock-controller@27200000 {
++ compatible = "rockchip,rk3576-cru";
++ reg = <0x0 0x27200000 0x0 0x50000>;
++ #clock-cells = <1>;
++ #reset-cells = <1>;
++
++ assigned-clocks =
++ <&cru CLK_AUDIO_FRAC_1_SRC>,
++ <&cru PLL_GPLL>, <&cru PLL_CPLL>,
++ <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>,
++ <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>,
++ <&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>,
++ <&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>,
++ <&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>,
++ <&cru ACLK_PHP_ROOT>;
++ assigned-clock-parents = <&cru PLL_AUPLL>;
++ assigned-clock-rates =
++ <0>,
++ <1188000000>, <1000000000>,
++ <786432000>, <18432000>,
++ <96000000>, <128000000>,
++ <45158400>, <49152000>,
++ <500000000>, <250000000>,
++ <100000000>, <500000000>,
++ <250000000>;
++ };
++
++ i2c0: i2c@27300000 {
++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
++ reg = <0x0 0x27300000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0m0_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ uart1: serial@27310000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x27310000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac0 8>, <&dmac0 9>;
++ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart1m0_xfer>;
++ status = "disabled";
++ };
++
++ pmu: power-management@27380000 {
++ compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
++ reg = <0x0 0x27380000 0x0 0x800>;
++
++ power: power-controller {
++ compatible = "rockchip,rk3576-power-controller";
++ #power-domain-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ power-domain@RK3576_PD_NPU {
++ reg = <RK3576_PD_NPU>;
++ #power-domain-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ power-domain@RK3576_PD_NPUTOP {
++ reg = <RK3576_PD_NPUTOP>;
++ clocks = <&cru ACLK_RKNN0>,
++ <&cru ACLK_RKNN1>,
++ <&cru ACLK_RKNN_CBUF>,
++ <&cru CLK_RKNN_DSU0>,
++ <&cru HCLK_RKNN_CBUF>,
++ <&cru HCLK_RKNN_ROOT>,
++ <&cru HCLK_NPU_CM0_ROOT>,
++ <&cru PCLK_NPUTOP_ROOT>;
++ pm_qos = <&qos_npu_mcu>,
++ <&qos_npu_nsp0>,
++ <&qos_npu_nsp1>,
++ <&qos_npu_m0ro>,
++ <&qos_npu_m1ro>;
++ #power-domain-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ power-domain@RK3576_PD_NPU0 {
++ reg = <RK3576_PD_NPU0>;
++ clocks = <&cru HCLK_RKNN_ROOT>,
++ <&cru ACLK_RKNN0>;
++ pm_qos = <&qos_npu_m0>;
++ #power-domain-cells = <0>;
++ };
++ power-domain@RK3576_PD_NPU1 {
++ reg = <RK3576_PD_NPU1>;
++ clocks = <&cru HCLK_RKNN_ROOT>,
++ <&cru ACLK_RKNN1>;
++ pm_qos = <&qos_npu_m1>;
++ #power-domain-cells = <0>;
++ };
++ };
++ };
++
++ power-domain@RK3576_PD_GPU {
++ reg = <RK3576_PD_GPU>;
++ clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>;
++ pm_qos = <&qos_gpu>;
++ #power-domain-cells = <0>;
++ };
++
++ power-domain@RK3576_PD_NVM {
++ reg = <RK3576_PD_NVM>;
++ clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>;
++ pm_qos = <&qos_emmc>,
++ <&qos_fspi0>;
++ #power-domain-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ power-domain@RK3576_PD_SDGMAC {
++ reg = <RK3576_PD_SDGMAC>;
++ clocks = <&cru ACLK_HSGPIO>,
++ <&cru ACLK_GMAC0>,
++ <&cru ACLK_GMAC1>,
++ <&cru CCLK_SRC_SDIO>,
++ <&cru CCLK_SRC_SDMMC0>,
++ <&cru HCLK_HSGPIO>,
++ <&cru HCLK_SDIO>,
++ <&cru HCLK_SDMMC0>,
++ <&cru PCLK_SDGMAC_ROOT>;
++ pm_qos = <&qos_fspi1>,
++ <&qos_gmac0>,
++ <&qos_gmac1>,
++ <&qos_sdio>,
++ <&qos_sdmmc>,
++ <&qos_flexbus>;
++ #power-domain-cells = <0>;
++ };
++ };
++
++ power-domain@RK3576_PD_PHP {
++ reg = <RK3576_PD_PHP>;
++ clocks = <&cru ACLK_PHP_ROOT>,
++ <&cru PCLK_PHP_ROOT>,
++ <&cru ACLK_MMU0>,
++ <&cru ACLK_MMU1>;
++ pm_qos = <&qos_mmu0>,
++ <&qos_mmu1>;
++ #power-domain-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ power-domain@RK3576_PD_SUBPHP {
++ reg = <RK3576_PD_SUBPHP>;
++ #power-domain-cells = <0>;
++ };
++ };
++
++ power-domain@RK3576_PD_AUDIO {
++ reg = <RK3576_PD_AUDIO>;
++ #power-domain-cells = <0>;
++ };
++
++ power-domain@RK3576_PD_VEPU1 {
++ reg = <RK3576_PD_VEPU1>;
++ clocks = <&cru ACLK_VEPU1>,
++ <&cru HCLK_VEPU1>;
++ pm_qos = <&qos_vepu1>;
++ #power-domain-cells = <0>;
++ };
++
++ power-domain@RK3576_PD_VPU {
++ reg = <RK3576_PD_VPU>;
++ clocks = <&cru ACLK_EBC>,
++ <&cru HCLK_EBC>,
++ <&cru ACLK_JPEG>,
++ <&cru HCLK_JPEG>,
++ <&cru ACLK_RGA2E_0>,
++ <&cru HCLK_RGA2E_0>,
++ <&cru ACLK_RGA2E_1>,
++ <&cru HCLK_RGA2E_1>,
++ <&cru ACLK_VDPP>,
++ <&cru HCLK_VDPP>;
++ pm_qos = <&qos_ebc>,
++ <&qos_jpeg>,
++ <&qos_rga0>,
++ <&qos_rga1>,
++ <&qos_vdpp>;
++ #power-domain-cells = <0>;
++ };
++
++ power-domain@RK3576_PD_VDEC {
++ reg = <RK3576_PD_VDEC>;
++ clocks = <&cru ACLK_RKVDEC_ROOT>,
++ <&cru HCLK_RKVDEC>;
++ pm_qos = <&qos_rkvdec>;
++ #power-domain-cells = <0>;
++ };
++
++ power-domain@RK3576_PD_VI {
++ reg = <RK3576_PD_VI>;
++ clocks = <&cru ACLK_VICAP>,
++ <&cru HCLK_VICAP>,
++ <&cru DCLK_VICAP>,
++ <&cru ACLK_VI_ROOT>,
++ <&cru HCLK_VI_ROOT>,
++ <&cru PCLK_VI_ROOT>,
++ <&cru CLK_ISP_CORE>,
++ <&cru ACLK_ISP>,
++ <&cru HCLK_ISP>,
++ <&cru CLK_CORE_VPSS>,
++ <&cru ACLK_VPSS>,
++ <&cru HCLK_VPSS>;
++ pm_qos = <&qos_isp_mro>,
++ <&qos_isp_mwo>,
++ <&qos_vicap_m0>,
++ <&qos_vpss_mro>,
++ <&qos_vpss_mwo>;
++ #power-domain-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ power-domain@RK3576_PD_VEPU0 {
++ reg = <RK3576_PD_VEPU0>;
++ clocks = <&cru ACLK_VEPU0>,
++ <&cru HCLK_VEPU0>;
++ pm_qos = <&qos_vepu0>;
++ #power-domain-cells = <0>;
++ };
++ };
++
++ power-domain@RK3576_PD_VOP {
++ reg = <RK3576_PD_VOP>;
++ clocks = <&cru ACLK_VOP>,
++ <&cru HCLK_VOP>,
++ <&cru HCLK_VOP_ROOT>,
++ <&cru PCLK_VOP_ROOT>;
++ pm_qos = <&qos_vop_m0>,
++ <&qos_vop_m1ro>;
++ #power-domain-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ power-domain@RK3576_PD_USB {
++ reg = <RK3576_PD_USB>;
++ clocks = <&cru PCLK_PHP_ROOT>,
++ <&cru ACLK_USB_ROOT>,
++ <&cru ACLK_MMU2>,
++ <&cru ACLK_SLV_MMU2>,
++ <&cru ACLK_UFS_SYS>;
++ pm_qos = <&qos_mmu2>,
++ <&qos_ufshc>;
++ #power-domain-cells = <0>;
++ };
++
++ power-domain@RK3576_PD_VO0 {
++ reg = <RK3576_PD_VO0>;
++ clocks = <&cru ACLK_HDCP0>,
++ <&cru HCLK_HDCP0>,
++ <&cru ACLK_VO0_ROOT>,
++ <&cru PCLK_VO0_ROOT>,
++ <&cru HCLK_VOP_ROOT>;
++ pm_qos = <&qos_hdcp0>;
++ #power-domain-cells = <0>;
++ };
++
++ power-domain@RK3576_PD_VO1 {
++ reg = <RK3576_PD_VO1>;
++ clocks = <&cru ACLK_HDCP1>,
++ <&cru HCLK_HDCP1>,
++ <&cru ACLK_VO1_ROOT>,
++ <&cru PCLK_VO1_ROOT>,
++ <&cru HCLK_VOP_ROOT>;
++ pm_qos = <&qos_hdcp1>;
++ #power-domain-cells = <0>;
++ };
++ };
++ };
++ };
++
++ gpu: gpu@27800000 {
++ compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
++ reg = <0x0 0x27800000 0x0 0x200000>;
++ assigned-clocks = <&scmi_clk CLK_GPU>;
++ assigned-clock-rates = <198000000>;
++ clocks = <&cru CLK_GPU>;
++ clock-names = "core";
++ dynamic-power-coefficient = <1625>;
++ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "job", "mmu", "gpu";
++ operating-points-v2 = <&gpu_opp_table>;
++ power-domains = <&power RK3576_PD_GPU>;
++ #cooling-cells = <2>;
++ status = "disabled";
++ };
++
++ qos_hdcp1: qos@27f02000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f02000 0x0 0x20>;
++ };
++
++ qos_fspi1: qos@27f04000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f04000 0x0 0x20>;
++ };
++
++ qos_gmac0: qos@27f04080 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f04080 0x0 0x20>;
++ };
++
++ qos_gmac1: qos@27f04100 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f04100 0x0 0x20>;
++ };
++
++ qos_sdio: qos@27f04180 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f04180 0x0 0x20>;
++ };
++
++ qos_sdmmc: qos@27f04200 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f04200 0x0 0x20>;
++ };
++
++ qos_flexbus: qos@27f04280 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f04280 0x0 0x20>;
++ };
++
++ qos_gpu: qos@27f05000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f05000 0x0 0x20>;
++ };
++
++ qos_vepu1: qos@27f06000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f06000 0x0 0x20>;
++ };
++
++ qos_npu_mcu: qos@27f08000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f08000 0x0 0x20>;
++ };
++
++ qos_npu_nsp0: qos@27f08080 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f08080 0x0 0x20>;
++ };
++
++ qos_npu_nsp1: qos@27f08100 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f08100 0x0 0x20>;
++ };
++
++ qos_emmc: qos@27f09000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f09000 0x0 0x20>;
++ };
++
++ qos_fspi0: qos@27f09080 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f09080 0x0 0x20>;
++ };
++
++ qos_mmu0: qos@27f0a000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f0a000 0x0 0x20>;
++ };
++
++ qos_mmu1: qos@27f0a080 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f0a080 0x0 0x20>;
++ };
++
++ qos_rkvdec: qos@27f0c000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f0c000 0x0 0x20>;
++ };
++
++ qos_crypto: qos@27f0d000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f0d000 0x0 0x20>;
++ };
++
++ qos_mmu2: qos@27f0e000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f0e000 0x0 0x20>;
++ };
++
++ qos_ufshc: qos@27f0e080 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f0e080 0x0 0x20>;
++ };
++
++ qos_vepu0: qos@27f0f000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f0f000 0x0 0x20>;
++ };
++
++ qos_isp_mro: qos@27f10000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f10000 0x0 0x20>;
++ };
++
++ qos_isp_mwo: qos@27f10080 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f10080 0x0 0x20>;
++ };
++
++ qos_vicap_m0: qos@27f10100 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f10100 0x0 0x20>;
++ };
++
++ qos_vpss_mro: qos@27f10180 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f10180 0x0 0x20>;
++ };
++
++ qos_vpss_mwo: qos@27f10200 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f10200 0x0 0x20>;
++ };
++
++ qos_hdcp0: qos@27f11000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f11000 0x0 0x20>;
++ };
++
++ qos_vop_m0: qos@27f12800 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f12800 0x0 0x20>;
++ };
++
++ qos_vop_m1ro: qos@27f12880 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f12880 0x0 0x20>;
++ };
++
++ qos_ebc: qos@27f13000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f13000 0x0 0x20>;
++ };
++
++ qos_rga0: qos@27f13080 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f13080 0x0 0x20>;
++ };
++
++ qos_rga1: qos@27f13100 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f13100 0x0 0x20>;
++ };
++
++ qos_jpeg: qos@27f13180 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f13180 0x0 0x20>;
++ };
++
++ qos_vdpp: qos@27f13200 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f13200 0x0 0x20>;
++ };
++
++ qos_npu_m0: qos@27f20000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f20000 0x0 0x20>;
++ };
++
++ qos_npu_m1: qos@27f21000 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f21000 0x0 0x20>;
++ };
++
++ qos_npu_m0ro: qos@27f22080 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f22080 0x0 0x20>;
++ };
++
++ qos_npu_m1ro: qos@27f22100 {
++ compatible = "rockchip,rk3576-qos", "syscon";
++ reg = <0x0 0x27f22100 0x0 0x20>;
++ };
++
++ gmac0: ethernet@2a220000 {
++ compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
++ reg = <0x0 0x2a220000 0x0 0x10000>;
++ clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>,
++ <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
++ <&cru CLK_GMAC0_PTP_REF>;
++ clock-names = "stmmaceth", "clk_mac_ref",
++ "pclk_mac", "aclk_mac",
++ "ptp_ref";
++ interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq", "eth_wake_irq";
++ power-domains = <&power RK3576_PD_SDGMAC>;
++ resets = <&cru SRST_A_GMAC0>;
++ reset-names = "stmmaceth";
++ rockchip,grf = <&sdgmac_grf>;
++ rockchip,php-grf = <&ioc_grf>;
++ snps,axi-config = <&gmac0_stmmac_axi_setup>;
++ snps,mixed-burst;
++ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
++ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
++ snps,tso;
++ status = "disabled";
++
++ mdio0: mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ };
++
++ gmac0_stmmac_axi_setup: stmmac-axi-config {
++ snps,blen = <0 0 0 0 16 8 4>;
++ snps,rd_osr_lmt = <8>;
++ snps,wr_osr_lmt = <4>;
++ };
++
++ gmac0_mtl_rx_setup: rx-queues-config {
++ snps,rx-queues-to-use = <1>;
++ queue0 {};
++ };
++
++ gmac0_mtl_tx_setup: tx-queues-config {
++ snps,tx-queues-to-use = <1>;
++ queue0 {};
++ };
++ };
++
++ gmac1: ethernet@2a230000 {
++ compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
++ reg = <0x0 0x2a230000 0x0 0x10000>;
++ clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>,
++ <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
++ <&cru CLK_GMAC1_PTP_REF>;
++ clock-names = "stmmaceth", "clk_mac_ref",
++ "pclk_mac", "aclk_mac",
++ "ptp_ref";
++ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq", "eth_wake_irq";
++ power-domains = <&power RK3576_PD_SDGMAC>;
++ resets = <&cru SRST_A_GMAC1>;
++ reset-names = "stmmaceth";
++ rockchip,grf = <&sdgmac_grf>;
++ rockchip,php-grf = <&ioc_grf>;
++ snps,axi-config = <&gmac1_stmmac_axi_setup>;
++ snps,mixed-burst;
++ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
++ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
++ snps,tso;
++ status = "disabled";
++
++ mdio1: mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ };
++
++ gmac1_stmmac_axi_setup: stmmac-axi-config {
++ snps,blen = <0 0 0 0 16 8 4>;
++ snps,rd_osr_lmt = <8>;
++ snps,wr_osr_lmt = <4>;
++ };
++
++ gmac1_mtl_rx_setup: rx-queues-config {
++ snps,rx-queues-to-use = <1>;
++ queue0 {};
++ };
++
++ gmac1_mtl_tx_setup: tx-queues-config {
++ snps,tx-queues-to-use = <1>;
++ queue0 {};
++ };
++ };
++
++ sdmmc: mmc@2a310000 {
++ compatible = "rockchip,rk3576-dw-mshc";
++ reg = <0x0 0x2a310000 0x0 0x4000>;
++ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
++ clock-names = "biu", "ciu";
++ fifo-depth = <0x100>;
++ interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
++ max-frequency = <200000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>;
++ power-domains = <&power RK3576_PD_SDGMAC>;
++ resets = <&cru SRST_H_SDMMC0>;
++ reset-names = "reset";
++ status = "disabled";
++ };
++
++ sdhci: mmc@2a330000 {
++ compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
++ reg = <0x0 0x2a330000 0x0 0x10000>;
++ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
++ assigned-clock-rates = <200000000>, <24000000>, <200000000>;
++ clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
++ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
++ <&cru TCLK_EMMC>;
++ clock-names = "core", "bus", "axi", "block", "timer";
++ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
++ max-frequency = <200000000>;
++ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
++ <&emmc_cmd>, <&emmc_strb>;
++ pinctrl-names = "default";
++ power-domains = <&power RK3576_PD_NVM>;
++ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
++ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
++ <&cru SRST_T_EMMC>;
++ reset-names = "core", "bus", "axi", "block", "timer";
++ supports-cqe;
++ status = "disabled";
++ };
++
++ gic: interrupt-controller@2a701000 {
++ compatible = "arm,gic-400";
++ reg = <0x0 0x2a701000 0 0x10000>,
++ <0x0 0x2a702000 0 0x10000>,
++ <0x0 0x2a704000 0 0x10000>,
++ <0x0 0x2a706000 0 0x10000>;
++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
++ interrupt-controller;
++ #interrupt-cells = <3>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ };
++
++ dmac0: dma-controller@2ab90000 {
++ compatible = "arm,pl330", "arm,primecell";
++ reg = <0x0 0x2ab90000 0x0 0x4000>;
++ arm,pl330-periph-burst;
++ clocks = <&cru ACLK_DMAC0>;
++ clock-names = "apb_pclk";
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
++ #dma-cells = <1>;
++ };
++
++ dmac1: dma-controller@2abb0000 {
++ compatible = "arm,pl330", "arm,primecell";
++ reg = <0x0 0x2abb0000 0x0 0x4000>;
++ arm,pl330-periph-burst;
++ clocks = <&cru ACLK_DMAC1>;
++ clock-names = "apb_pclk";
++ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
++ #dma-cells = <1>;
++ };
++
++ dmac2: dma-controller@2abd0000 {
++ compatible = "arm,pl330", "arm,primecell";
++ reg = <0x0 0x2abd0000 0x0 0x4000>;
++ arm,pl330-periph-burst;
++ clocks = <&cru ACLK_DMAC2>;
++ clock-names = "apb_pclk";
++ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
++ #dma-cells = <1>;
++ };
++
++ i2c1: i2c@2ac40000 {
++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
++ reg = <0x0 0x2ac40000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1m0_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c2: i2c@2ac50000 {
++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
++ reg = <0x0 0x2ac50000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c2m0_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c3: i2c@2ac60000 {
++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
++ reg = <0x0 0x2ac60000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c3m0_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c4: i2c@2ac70000 {
++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
++ reg = <0x0 0x2ac70000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c4m0_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c5: i2c@2ac80000 {
++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
++ reg = <0x0 0x2ac80000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c5m0_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++
++ i2c6: i2c@2ac90000 {
++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
++ reg = <0x0 0x2ac90000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c6m0_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c7: i2c@2aca0000 {
++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
++ reg = <0x0 0x2aca0000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c7m0_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c8: i2c@2acb0000 {
++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
++ reg = <0x0 0x2acb0000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c8m0_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ timer0: timer@2acc0000 {
++ compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer";
++ reg = <0x0 0x2acc0000 0x0 0x20>;
++ clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>;
++ clock-names = "pclk", "timer";
++ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ wdt: watchdog@2ace0000 {
++ compatible = "rockchip,rk3576-wdt", "snps,dw-wdt";
++ reg = <0x0 0x2ace0000 0x0 0x100>;
++ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
++ clock-names = "tclk", "pclk";
++ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ };
++
++ spi0: spi@2acf0000 {
++ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
++ reg = <0x0 0x2acf0000 0x0 0x1000>;
++ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
++ clock-names = "spiclk", "apb_pclk";
++ dmas = <&dmac0 14>, <&dmac0 15>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
++ num-cs = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ spi1: spi@2ad00000 {
++ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
++ reg = <0x0 0x2ad00000 0x0 0x1000>;
++ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
++ clock-names = "spiclk", "apb_pclk";
++ dmas = <&dmac0 16>, <&dmac0 17>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
++ num-cs = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ spi2: spi@2ad10000 {
++ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
++ reg = <0x0 0x2ad10000 0x0 0x1000>;
++ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
++ clock-names = "spiclk", "apb_pclk";
++ dmas = <&dmac1 15>, <&dmac1 16>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
++ num-cs = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ spi3: spi@2ad20000 {
++ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
++ reg = <0x0 0x2ad20000 0x0 0x1000>;
++ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
++ clock-names = "spiclk", "apb_pclk";
++ dmas = <&dmac1 17>, <&dmac1 18>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
++ num-cs = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ spi4: spi@2ad30000 {
++ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
++ reg = <0x0 0x2ad30000 0x0 0x1000>;
++ clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
++ clock-names = "spiclk", "apb_pclk";
++ dmas = <&dmac2 12>, <&dmac2 13>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
++ num-cs = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ uart0: serial@2ad40000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x2ad40000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac0 6>, <&dmac0 7>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-0 = <&uart0m0_xfer>;
++ pinctrl-names = "default";
++ status = "disabled";
++ };
++
++ uart2: serial@2ad50000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x2ad50000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac0 10>, <&dmac0 11>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart2m0_xfer>;
++ status = "disabled";
++ };
++
++ uart3: serial@2ad60000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x2ad60000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac0 12>, <&dmac0 13>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-0 = <&uart3m0_xfer>;
++ pinctrl-names = "default";
++ status = "disabled";
++ };
++
++ uart4: serial@2ad70000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x2ad70000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac1 9>, <&dmac1 10>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-0 = <&uart4m0_xfer>;
++ pinctrl-names = "default";
++ status = "disabled";
++ };
++
++ uart5: serial@2ad80000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x2ad80000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac1 11>, <&dmac1 12>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-0 = <&uart5m0_xfer>;
++ pinctrl-names = "default";
++ status = "disabled";
++ };
++
++ uart6: serial@2ad90000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x2ad90000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac1 13>, <&dmac1 14>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-0 = <&uart6m0_xfer>;
++ pinctrl-names = "default";
++ status = "disabled";
++ };
++
++ uart7: serial@2ada0000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x2ada0000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac2 6>, <&dmac2 7>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-0 = <&uart7m0_xfer>;
++ pinctrl-names = "default";
++ status = "disabled";
++ };
++
++ uart8: serial@2adb0000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x2adb0000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac2 8>, <&dmac2 9>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-0 = <&uart8m0_xfer>;
++ pinctrl-names = "default";
++ status = "disabled";
++ };
++
++ uart9: serial@2adc0000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x2adc0000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac2 10>, <&dmac2 11>;
++ dma-names = "tx", "rx";
++ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-0 = <&uart9m0_xfer>;
++ pinctrl-names = "default";
++ status = "disabled";
++ };
++
++ saradc: adc@2ae00000 {
++ compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
++ reg = <0x0 0x2ae00000 0x0 0x10000>;
++ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
++ clock-names = "saradc", "apb_pclk";
++ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&cru SRST_P_SARADC>;
++ reset-names = "saradc-apb";
++ #io-channel-cells = <1>;
++ status = "disabled";
++ };
++
++ i2c9: i2c@2ae80000 {
++ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
++ reg = <0x0 0x2ae80000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c9m0_xfer>;
++ resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>;
++ reset-names = "i2c", "apb";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ uart10: serial@2afc0000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x2afc0000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac2 21>, <&dmac2 22>;
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart10m0_xfer>;
++ status = "disabled";
++ };
++
++ uart11: serial@2afd0000 {
++ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
++ reg = <0x0 0x2afd0000 0x0 0x100>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>;
++ clock-names = "baudclk", "apb_pclk";
++ dmas = <&dmac2 23>, <&dmac2 24>;
++ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart11m0_xfer>;
++ status = "disabled";
++ };
++
++ sram: sram@3ff88000 {
++ compatible = "mmio-sram";
++ reg = <0x0 0x3ff88000 0x0 0x78000>;
++ ranges = <0x0 0x0 0x3ff88000 0x78000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ /* start address and size should be 4k align */
++ rkvdec_sram: rkvdec-sram@0 {
++ reg = <0x0 0x78000>;
++ };
++ };
++
++ scmi_shmem: scmi-shmem@4010f000 {
++ compatible = "arm,scmi-shmem";
++ reg = <0x0 0x4010f000 0x0 0x100>;
++ };
++
++ pinctrl: pinctrl {
++ compatible = "rockchip,rk3576-pinctrl";
++ rockchip,grf = <&ioc_grf>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ gpio0: gpio@27320000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0x27320000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
++ gpio-controller;
++ gpio-ranges = <&pinctrl 0 0 32>;
++ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-controller;
++ #gpio-cells = <2>;
++ #interrupt-cells = <2>;
++ };
++
++ gpio1: gpio@2ae10000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0x2ae10000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
++ gpio-controller;
++ gpio-ranges = <&pinctrl 0 32 32>;
++ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-controller;
++ #gpio-cells = <2>;
++ #interrupt-cells = <2>;
++ };
++
++ gpio2: gpio@2ae20000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0x2ae20000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
++ gpio-controller;
++ gpio-ranges = <&pinctrl 0 64 32>;
++ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-controller;
++ #gpio-cells = <2>;
++ #interrupt-cells = <2>;
++ };
++
++ gpio3: gpio@2ae30000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0x2ae30000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
++ gpio-controller;
++ gpio-ranges = <&pinctrl 0 96 32>;
++ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-controller;
++ #gpio-cells = <2>;
++ #interrupt-cells = <2>;
++ };
++
++ gpio4: gpio@2ae40000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0x2ae40000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
++ gpio-controller;
++ gpio-ranges = <&pinctrl 0 128 32>;
++ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-controller;
++ #gpio-cells = <2>;
++ #interrupt-cells = <2>;
++ };
++ };
++ };
++};
++
++#include "rk3576-pinctrl.dtsi"
--- /dev/null
+From ddbf63b25866a4a58222d763f9f2d29c309e00e8 Mon Sep 17 00:00:00 2001
+From: Kever Yang <kever.yang@rock-chips.com>
+Date: Tue, 7 Jan 2025 15:49:05 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add rk3576 naneng combphy nodes
+
+rk3576 has two naneng combo phys:
+- combophy0 is used for one of pcie and sata;
+- combophy1 is used for one of pcie, sata and usb3;
+
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+Link: https://lore.kernel.org/r/20250107074911.550057-2-kever.yang@rock-chips.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1587,6 +1587,42 @@
+ status = "disabled";
+ };
+
++ combphy0_ps: phy@2b050000 {
++ compatible = "rockchip,rk3576-naneng-combphy";
++ reg = <0x0 0x2b050000 0x0 0x100>;
++ #phy-cells = <1>;
++ clocks = <&cru CLK_REF_PCIE0_PHY>,
++ <&cru PCLK_PCIE2_COMBOPHY0>,
++ <&cru PCLK_PCIE0>;
++ clock-names = "ref", "apb", "pipe";
++ assigned-clocks = <&cru CLK_REF_PCIE0_PHY>;
++ assigned-clock-rates = <100000000>;
++ resets = <&cru SRST_PCIE0_PIPE_PHY>,
++ <&cru SRST_P_PCIE2_COMBOPHY0>;
++ reset-names = "phy", "apb";
++ rockchip,pipe-grf = <&php_grf>;
++ rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
++ status = "disabled";
++ };
++
++ combphy1_psu: phy@2b060000 {
++ compatible = "rockchip,rk3576-naneng-combphy";
++ reg = <0x0 0x2b060000 0x0 0x100>;
++ #phy-cells = <1>;
++ clocks = <&cru CLK_REF_PCIE1_PHY>,
++ <&cru PCLK_PCIE2_COMBOPHY1>,
++ <&cru PCLK_PCIE1>;
++ clock-names = "ref", "apb", "pipe";
++ assigned-clocks = <&cru CLK_REF_PCIE1_PHY>;
++ assigned-clock-rates = <100000000>;
++ resets = <&cru SRST_PCIE1_PIPE_PHY>,
++ <&cru SRST_P_PCIE2_COMBOPHY1>;
++ reset-names = "phy", "apb";
++ rockchip,pipe-grf = <&php_grf>;
++ rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
++ status = "disabled";
++ };
++
+ sram: sram@3ff88000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x3ff88000 0x0 0x78000>;
--- /dev/null
+From 23ec57a32da448cb3415d6abad3457b14c69af25 Mon Sep 17 00:00:00 2001
+From: Frank Wang <frank.wang@rock-chips.com>
+Date: Tue, 7 Jan 2025 15:49:08 +0800
+Subject: [PATCH] arm64: dts: rockchip: add usb related nodes for rk3576
+
+This adds USB and USB-PHY related nodes for RK3576 SoC.
+
+Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+Link: https://lore.kernel.org/r/20250107074911.550057-5-kever.yang@rock-chips.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 133 +++++++++++++++++++++++
+ 1 file changed, 133 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -445,6 +445,58 @@
+ #size-cells = <2>;
+ ranges;
+
++ usb_drd0_dwc3: usb@23000000 {
++ compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
++ reg = <0x0 0x23000000 0x0 0x400000>;
++ clocks = <&cru CLK_REF_USB3OTG0>,
++ <&cru CLK_SUSPEND_USB3OTG0>,
++ <&cru ACLK_USB3OTG0>;
++ clock-names = "ref_clk", "suspend_clk", "bus_clk";
++ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3576_PD_USB>;
++ resets = <&cru SRST_A_USB3OTG0>;
++ dr_mode = "otg";
++ phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>;
++ phy-names = "usb2-phy", "usb3-phy";
++ phy_type = "utmi_wide";
++ snps,dis_enblslpm_quirk;
++ snps,dis-u1-entry-quirk;
++ snps,dis-u2-entry-quirk;
++ snps,dis-u2-freeclk-exists-quirk;
++ snps,dis-del-phy-power-chg-quirk;
++ snps,dis-tx-ipgap-linecheck-quirk;
++ snps,parkmode-disable-hs-quirk;
++ snps,parkmode-disable-ss-quirk;
++ status = "disabled";
++ };
++
++ usb_drd1_dwc3: usb@23400000 {
++ compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
++ reg = <0x0 0x23400000 0x0 0x400000>;
++ clocks = <&cru CLK_REF_USB3OTG1>,
++ <&cru CLK_SUSPEND_USB3OTG1>,
++ <&cru ACLK_USB3OTG1>;
++ clock-names = "ref_clk", "suspend_clk", "bus_clk";
++ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3576_PD_PHP>;
++ resets = <&cru SRST_A_USB3OTG1>;
++ dr_mode = "otg";
++ phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>;
++ phy-names = "usb2-phy", "usb3-phy";
++ phy_type = "utmi_wide";
++ snps,dis_enblslpm_quirk;
++ snps,dis-u1-entry-quirk;
++ snps,dis-u2-entry-quirk;
++ snps,dis-u2-freeclk-exists-quirk;
++ snps,dis-del-phy-power-chg-quirk;
++ snps,dis-tx-ipgap-linecheck-quirk;
++ snps,dis_rxdet_inp3_quirk;
++ snps,parkmode-disable-hs-quirk;
++ snps,parkmode-disable-ss-quirk;
++ dma-coherent;
++ status = "disabled";
++ };
++
+ sys_grf: syscon@2600a000 {
+ compatible = "rockchip,rk3576-sys-grf", "syscon";
+ reg = <0x0 0x2600a000 0x0 0x2000>;
+@@ -515,6 +567,65 @@
+ reg = <0x0 0x2602c000 0x0 0x2000>;
+ };
+
++ usb2phy_grf: syscon@2602e000 {
++ compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
++ reg = <0x0 0x2602e000 0x0 0x4000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ u2phy0: usb2-phy@0 {
++ compatible = "rockchip,rk3576-usb2phy";
++ reg = <0x0 0x10>;
++ resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>;
++ reset-names = "phy", "apb";
++ clocks = <&cru CLK_PHY_REF_SRC>,
++ <&cru ACLK_MMU2>,
++ <&cru ACLK_SLV_MMU2>;
++ clock-names = "phyclk", "aclk", "aclk_slv";
++ clock-output-names = "usb480m_phy0";
++ #clock-cells = <0>;
++ status = "disabled";
++
++ u2phy0_otg: otg-port {
++ #phy-cells = <0>;
++ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "otg-bvalid", "otg-id", "linestate";
++ status = "disabled";
++ };
++ };
++
++ u2phy1: usb2-phy@2000 {
++ compatible = "rockchip,rk3576-usb2phy";
++ reg = <0x2000 0x10>;
++ resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>;
++ reset-names = "phy", "apb";
++ clocks = <&cru CLK_PHY_REF_SRC>,
++ <&cru ACLK_MMU1>,
++ <&cru ACLK_SLV_MMU1>;
++ clock-names = "phyclk", "aclk", "aclk_slv";
++ clock-output-names = "usb480m_phy1";
++ #clock-cells = <0>;
++ status = "disabled";
++
++ u2phy1_otg: otg-port {
++ #phy-cells = <0>;
++ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "otg-bvalid", "otg-id", "linestate";
++ status = "disabled";
++ };
++ };
++ };
++
++ vo1_grf: syscon@26036000 {
++ compatible = "rockchip,rk3576-vo1-grf", "syscon";
++ reg = <0x0 0x26036000 0x0 0x100>;
++ clocks = <&cru PCLK_VO1_ROOT>;
++ };
++
+ sdgmac_grf: syscon@26038000 {
+ compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
+ reg = <0x0 0x26038000 0x0 0x1000>;
+@@ -1623,6 +1734,28 @@
+ status = "disabled";
+ };
+
++ usbdp_phy: phy@2b010000 {
++ compatible = "rockchip,rk3576-usbdp-phy";
++ reg = <0x0 0x2b010000 0x0 0x10000>;
++ #phy-cells = <1>;
++ clocks = <&cru CLK_PHY_REF_SRC >,
++ <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>,
++ <&cru PCLK_USBDPPHY>,
++ <&u2phy0>;
++ clock-names = "refclk", "immortal", "pclk", "utmi";
++ resets = <&cru SRST_USBDP_COMBO_PHY_INIT>,
++ <&cru SRST_USBDP_COMBO_PHY_CMN>,
++ <&cru SRST_USBDP_COMBO_PHY_LANE>,
++ <&cru SRST_USBDP_COMBO_PHY_PCS>,
++ <&cru SRST_P_USBDPPHY>;
++ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
++ rockchip,u2phy-grf = <&usb2phy_grf>;
++ rockchip,usb-grf = <&usb_grf>;
++ rockchip,usbdpphy-grf = <&usbdpphy_grf>;
++ rockchip,vo-grf = <&vo1_grf>;
++ status = "disabled";
++ };
++
+ sram: sram@3ff88000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x3ff88000 0x0 0x78000>;
--- /dev/null
+From 8715d2eeb062f6859c252bb6c87b363230b66e9f Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Mon, 10 Feb 2025 23:45:10 +0100
+Subject: [PATCH] arm64: dts: rockchip: add rk3576 otp node
+
+This adds the otp node to the rk3576 soc devicetree including the
+individual fields we know about.
+
+Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250210224510.1194963-7-heiko@sntech.de
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 39 ++++++++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1260,6 +1260,45 @@
+ status = "disabled";
+ };
+
++ otp: otp@2a580000 {
++ compatible = "rockchip,rk3576-otp";
++ reg = <0x0 0x2a580000 0x0 0x400>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
++ <&cru CLK_OTP_PHY_G>;
++ clock-names = "otp", "apb_pclk", "phy";
++ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>;
++ reset-names = "otp", "apb";
++
++ /* Data cells */
++ cpu_code: cpu-code@2 {
++ reg = <0x02 0x2>;
++ };
++ otp_cpu_version: cpu-version@5 {
++ reg = <0x05 0x1>;
++ bits = <3 3>;
++ };
++ otp_id: id@a {
++ reg = <0x0a 0x10>;
++ };
++ cpub_leakage: cpub-leakage@1e {
++ reg = <0x1e 0x1>;
++ };
++ cpul_leakage: cpul-leakage@1f {
++ reg = <0x1f 0x1>;
++ };
++ npu_leakage: npu-leakage@20 {
++ reg = <0x20 0x1>;
++ };
++ gpu_leakage: gpu-leakage@21 {
++ reg = <0x21 0x1>;
++ };
++ log_leakage: log-leakage@22 {
++ reg = <0x22 0x1>;
++ };
++ };
++
+ gic: interrupt-controller@2a701000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0x2a701000 0 0x10000>,
--- /dev/null
+From c75e5e010fef2a62e6f2fe00ee8584e7b3ec82a6 Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Wed, 5 Feb 2025 14:15:56 +0800
+Subject: [PATCH] scsi: arm64: dts: rockchip: Add UFS support for RK3576 SoC
+
+Add ufshc node to rk3576.dtsi, so the board using UFS could enable it.
+
+Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Link: https://lore.kernel.org/r/1738736156-119203-8-git-send-email-shawn.lin@rock-chips.com
+Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1221,6 +1221,30 @@
+ };
+ };
+
++ ufshc: ufshc@2a2d0000 {
++ compatible = "rockchip,rk3576-ufshc";
++ reg = <0x0 0x2a2d0000 0x0 0x10000>,
++ <0x0 0x2b040000 0x0 0x10000>,
++ <0x0 0x2601f000 0x0 0x1000>,
++ <0x0 0x2603c000 0x0 0x1000>,
++ <0x0 0x2a2e0000 0x0 0x10000>;
++ reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb";
++ clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>,
++ <&cru CLK_REF_UFS_CLKOUT>;
++ clock-names = "core", "pclk", "pclk_mphy", "ref_out";
++ assigned-clocks = <&cru CLK_REF_OSC_MPHY>;
++ assigned-clock-parents = <&cru CLK_REF_MPHY_26M>;
++ interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3576_PD_USB>;
++ pinctrl-0 = <&ufs_refclk>;
++ pinctrl-names = "default";
++ resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>,
++ <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>;
++ reset-names = "biu", "sys", "ufs", "grf";
++ reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>;
++ status = "disabled";
++ };
++
+ sdmmc: mmc@2a310000 {
+ compatible = "rockchip,rk3576-dw-mshc";
+ reg = <0x0 0x2a310000 0x0 0x4000>;
--- /dev/null
+From d74b842cab0860e41a45df0dac41e4e56202c766 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Tue, 31 Dec 2024 17:57:18 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add vop for rk3576
+
+Add VOP and VOP_MMU found on rk3576.
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+Link: https://lore.kernel.org/r/20241231095728.253943-2-andyshrk@163.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 68 ++++++++++++++++++++++++
+ 1 file changed, 68 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -393,6 +393,11 @@
+ };
+ };
+
++ display_subsystem: display-subsystem {
++ compatible = "rockchip,display-subsystem";
++ ports = <&vop_out>;
++ };
++
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+@@ -937,6 +942,69 @@
+ status = "disabled";
+ };
+
++ vop: vop@27d00000 {
++ compatible = "rockchip,rk3576-vop";
++ reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
++ reg-names = "vop", "gamma-lut";
++ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "sys",
++ "vp0",
++ "vp1",
++ "vp2";
++ clocks = <&cru ACLK_VOP>,
++ <&cru HCLK_VOP>,
++ <&cru DCLK_VP0>,
++ <&cru DCLK_VP1>,
++ <&cru DCLK_VP2>;
++ clock-names = "aclk",
++ "hclk",
++ "dclk_vp0",
++ "dclk_vp1",
++ "dclk_vp2";
++ iommus = <&vop_mmu>;
++ power-domains = <&power RK3576_PD_VOP>;
++ rockchip,grf = <&sys_grf>;
++ rockchip,pmu = <&pmu>;
++ status = "disabled";
++
++ vop_out: ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ vp0: port@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++ };
++
++ vp1: port@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++ };
++
++ vp2: port@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++ };
++ };
++ };
++
++ vop_mmu: iommu@27d07e00 {
++ compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
++ reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>;
++ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
++ clock-names = "aclk", "iface";
++ #iommu-cells = <0>;
++ power-domains = <&power RK3576_PD_VOP>;
++ status = "disabled";
++ };
++
+ qos_hdcp1: qos@27f02000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f02000 0x0 0x20>;
--- /dev/null
+From ad0ea230ab2a3535b186f7fb863b4bca7050e06f Mon Sep 17 00:00:00 2001
+From: Andy Yan <andy.yan@rock-chips.com>
+Date: Tue, 31 Dec 2024 17:57:19 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add hdmi for rk3576
+
+Add hdmi and it's phy dt node for rk3576.
+
+Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
+Link: https://lore.kernel.org/r/20241231095728.253943-3-andyshrk@163.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 58 ++++++++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -625,6 +625,11 @@
+ };
+ };
+
++ hdptxphy_grf: syscon@26032000 {
++ compatible = "rockchip,rk3576-hdptxphy-grf", "syscon";
++ reg = <0x0 0x26032000 0x0 0x100>;
++ };
++
+ vo1_grf: syscon@26036000 {
+ compatible = "rockchip,rk3576-vo1-grf", "syscon";
+ reg = <0x0 0x26036000 0x0 0x100>;
+@@ -1005,6 +1010,46 @@
+ status = "disabled";
+ };
+
++ hdmi: hdmi@27da0000 {
++ compatible = "rockchip,rk3576-dw-hdmi-qp";
++ reg = <0x0 0x27da0000 0x0 0x20000>;
++ clocks = <&cru PCLK_HDMITX0>,
++ <&cru CLK_HDMITX0_EARC>,
++ <&cru CLK_HDMITX0_REF>,
++ <&cru MCLK_SAI6_8CH>,
++ <&cru CLK_HDMITXHDP>,
++ <&cru HCLK_VO0_ROOT>;
++ clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
++ interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "avp", "cec", "earc", "main", "hpd";
++ phys = <&hdptxphy>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>;
++ power-domains = <&power RK3576_PD_VO0>;
++ resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>;
++ reset-names = "ref", "hdp";
++ rockchip,grf = <&ioc_grf>;
++ rockchip,vo-grf = <&vo0_grf>;
++ status = "disabled";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ hdmi_in: port@0 {
++ reg = <0>;
++ };
++
++ hdmi_out: port@1 {
++ reg = <1>;
++ };
++ };
++ };
++
+ qos_hdcp1: qos@27f02000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f02000 0x0 0x20>;
+@@ -1887,6 +1932,19 @@
+ status = "disabled";
+ };
+
++ hdptxphy: hdmiphy@2b000000 {
++ compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy";
++ reg = <0x0 0x2b000000 0x0 0x2000>;
++ clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>;
++ clock-names = "ref", "apb";
++ resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
++ <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
++ reset-names = "apb", "init", "cmn", "lane";
++ rockchip,grf = <&hdptxphy_grf>;
++ #phy-cells = <0>;
++ status = "disabled";
++ };
++
+ sram: sram@3ff88000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x3ff88000 0x0 0x78000>;
--- /dev/null
+From 36299757129c897ef8c7ace6981070d367d89f89 Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Fri, 28 Feb 2025 09:50:47 -0500
+Subject: [PATCH] arm64: dts: rockchip: Add SFC nodes for rk3576
+
+The rk3576 SoC has 2 SFC cores that provide FSPI functions.
+
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+Link: https://lore.kernel.org/r/20250228145304.581349-2-detlev.casanova@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1358,6 +1358,17 @@
+ status = "disabled";
+ };
+
++ sfc1: spi@2a300000 {
++ compatible = "rockchip,sfc";
++ reg = <0x0 0x2a300000 0x0 0x4000>;
++ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>;
++ clock-names = "clk_sfc", "hclk_sfc";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
+ sdmmc: mmc@2a310000 {
+ compatible = "rockchip,rk3576-dw-mshc";
+ reg = <0x0 0x2a310000 0x0 0x4000>;
+@@ -1397,6 +1408,17 @@
+ status = "disabled";
+ };
+
++ sfc0: spi@2a340000 {
++ compatible = "rockchip,sfc";
++ reg = <0x0 0x2a340000 0x0 0x4000>;
++ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>;
++ clock-names = "clk_sfc", "hclk_sfc";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
+ otp: otp@2a580000 {
+ compatible = "rockchip,rk3576-otp";
+ reg = <0x0 0x2a580000 0x0 0x400>;
--- /dev/null
+From b5cb721adbe8b6c7a8e3b178fa0feb283f4a660a Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Mon, 10 Mar 2025 10:59:57 +0100
+Subject: [PATCH] arm64: dts: rockchip: fix RK3576 SCMI clock IDs
+
+Downstream Linux, and consequently both downstream and mainline TF-A,
+all use a different set of clock IDs from mainline Linux. If we want to
+fiddle with these clocks through SCMI, we'll need to use the right IDs.
+If we don't do this we'll end up changing unrelated clocks all over the
+place.
+
+Change the clock IDs to the newly added SCMI clock IDs for the CPU and
+GPU nodes, which are currently the only ones using SCMI clocks. This
+fixes the terrible GPU performance, as we weren't reclocking it
+properly.
+
+Fixes: 57b1ce903966 ("arm64: dts: rockchip: Add rk3576 SoC base DT")
+Reported-by: Jonas Karlman <jonas@kwiboo.se>
+Closes: https://libera.irclog.whitequark.org/linux-rockchip/2025-03-09#1741542223-1741542875;
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250310-rk3576-scmi-clocks-v1-2-e165deb034e8@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -111,7 +111,7 @@
+ reg = <0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <485>;
+- clocks = <&scmi_clk ARMCLK_L>;
++ clocks = <&scmi_clk SCMI_ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <120>;
+@@ -124,7 +124,7 @@
+ reg = <0x1>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <485>;
+- clocks = <&scmi_clk ARMCLK_L>;
++ clocks = <&scmi_clk SCMI_ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+@@ -135,7 +135,7 @@
+ reg = <0x2>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <485>;
+- clocks = <&scmi_clk ARMCLK_L>;
++ clocks = <&scmi_clk SCMI_ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+@@ -146,7 +146,7 @@
+ reg = <0x3>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <485>;
+- clocks = <&scmi_clk ARMCLK_L>;
++ clocks = <&scmi_clk SCMI_ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+@@ -157,7 +157,7 @@
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+- clocks = <&scmi_clk ARMCLK_B>;
++ clocks = <&scmi_clk SCMI_ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <320>;
+@@ -170,7 +170,7 @@
+ reg = <0x101>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+- clocks = <&scmi_clk ARMCLK_B>;
++ clocks = <&scmi_clk SCMI_ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+@@ -181,7 +181,7 @@
+ reg = <0x102>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+- clocks = <&scmi_clk ARMCLK_B>;
++ clocks = <&scmi_clk SCMI_ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+@@ -192,7 +192,7 @@
+ reg = <0x103>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+- clocks = <&scmi_clk ARMCLK_B>;
++ clocks = <&scmi_clk SCMI_ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+@@ -932,7 +932,7 @@
+ gpu: gpu@27800000 {
+ compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
+ reg = <0x0 0x27800000 0x0 0x200000>;
+- assigned-clocks = <&scmi_clk CLK_GPU>;
++ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
+ assigned-clock-rates = <198000000>;
+ clocks = <&cru CLK_GPU>;
+ clock-names = "core";
--- /dev/null
+From d4b9fc2af45d2b91b1654c4aaa1edcb4dd8f4918 Mon Sep 17 00:00:00 2001
+From: Kever Yang <kever.yang@rock-chips.com>
+Date: Mon, 14 Apr 2025 22:51:10 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add rk3576 pcie nodes
+
+rk3576 has two pcie controllers, both are pcie2x1 work with
+naneng-combphy.
+
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+Tested-by: Shawn Lin <Shawn.lin@rock-chips.com>
+Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250414145110.11275-3-kever.yang@rock-chips.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 108 +++++++++++++++++++++++
+ 1 file changed, 108 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1240,6 +1240,114 @@
+ reg = <0x0 0x27f22100 0x0 0x20>;
+ };
+
++ pcie0: pcie@2a200000 {
++ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
++ reg = <0x0 0x22000000 0x0 0x00400000>,
++ <0x0 0x2a200000 0x0 0x00010000>,
++ <0x0 0x20000000 0x0 0x00100000>;
++ reg-names = "dbi", "apb", "config";
++ bus-range = <0x0 0xf>;
++ clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
++ <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
++ <&cru CLK_PCIE0_AUX>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk",
++ "aux";
++ device_type = "pci";
++ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
++ <0 0 0 2 &pcie0_intc 1>,
++ <0 0 0 3 &pcie0_intc 2>,
++ <0 0 0 4 &pcie0_intc 3>;
++ linux,pci-domain = <0>;
++ max-link-speed = <2>;
++ num-ib-windows = <8>;
++ num-viewport = <8>;
++ num-ob-windows = <2>;
++ num-lanes = <1>;
++ phys = <&combphy0_ps PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy";
++ power-domains = <&power RK3576_PD_PHP>;
++ ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
++ 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
++ 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
++ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
++ reset-names = "pwr", "pipe";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ status = "disabled";
++
++ pcie0_intc: legacy-interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
++ };
++ };
++
++ pcie1: pcie@2a210000 {
++ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
++ reg = <0x0 0x22400000 0x0 0x00400000>,
++ <0x0 0x2a210000 0x0 0x00010000>,
++ <0x0 0x21000000 0x0 0x00100000>;
++ reg-names = "dbi", "apb", "config";
++ bus-range = <0x20 0x2f>;
++ clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
++ <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
++ <&cru CLK_PCIE1_AUX>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk",
++ "aux";
++ device_type = "pci";
++ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
++ <0 0 0 2 &pcie1_intc 1>,
++ <0 0 0 3 &pcie1_intc 2>,
++ <0 0 0 4 &pcie1_intc 3>;
++ linux,pci-domain = <0>;
++ max-link-speed = <2>;
++ num-ib-windows = <8>;
++ num-viewport = <8>;
++ num-ob-windows = <2>;
++ num-lanes = <1>;
++ phys = <&combphy1_psu PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy";
++ power-domains = <&power RK3576_PD_SUBPHP>;
++ ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
++ 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
++ 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
++ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
++ reset-names = "pwr", "pipe";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ status = "disabled";
++
++ pcie1_intc: legacy-interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
++ };
++ };
++
+ gmac0: ethernet@2a220000 {
+ compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0x2a220000 0x0 0x10000>;
--- /dev/null
+From 24d8127d801560c8fa811d554e8ab5db7e51511c Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Thu, 24 Apr 2025 20:52:23 +0200
+Subject: [PATCH] arm64: dts: rockchip: add SATA nodes to RK3576
+
+The Rockchip RK3576 features two SATA nodes. The first, sata0, is behind
+combphy0, which muxes between pcie0 and sata0.
+
+The second, sata1, is behind combphy1, which muxes between pcie1, sata1
+and usb_drd1_dwc3.
+
+I've only been able to test sata0 on my board, but it appears to work
+just fine.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250424-rk3576-sata-v1-2-23ee89c939fe@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 30 ++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1442,6 +1442,36 @@
+ };
+ };
+
++ sata0: sata@2a240000 {
++ compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
++ reg = <0x0 0x2a240000 0x0 0x1000>;
++ clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
++ <&cru CLK_RXOOB0>;
++ clock-names = "sata", "pmalive", "rxoob";
++ interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3576_PD_SUBPHP>;
++ phys = <&combphy0_ps PHY_TYPE_SATA>;
++ phy-names = "sata-phy";
++ ports-implemented = <0x1>;
++ dma-coherent;
++ status = "disabled";
++ };
++
++ sata1: sata@2a250000 {
++ compatible = "rockchip,rk3576-dwc-ahci", "snps,dwc-ahci";
++ reg = <0x0 0x2a250000 0x0 0x1000>;
++ clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
++ <&cru CLK_RXOOB1>;
++ clock-names = "sata", "pmalive", "rxoob";
++ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3576_PD_SUBPHP>;
++ phys = <&combphy1_psu PHY_TYPE_SATA>;
++ phy-names = "sata-phy";
++ ports-implemented = <0x1>;
++ dma-coherent;
++ status = "disabled";
++ };
++
+ ufshc: ufshc@2a2d0000 {
+ compatible = "rockchip,rk3576-ufshc";
+ reg = <0x0 0x2a2d0000 0x0 0x10000>,
--- /dev/null
+From 5268f3b5d29887480011b44567bcbf0d422cda94 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Wed, 30 Apr 2025 18:16:36 +0200
+Subject: [PATCH] arm64: dts: rockchip: add RK3576 RNG node
+
+The RK3576 has a hardware random number generator IP built into the SoC.
+
+Add it to the SoC's .dtsi, now that there's a binding and driver for it.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250430-rk3576-hwrng-v1-3-480c15b5843e@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1557,6 +1557,14 @@
+ status = "disabled";
+ };
+
++ rng: rng@2a410000 {
++ compatible = "rockchip,rk3576-rng";
++ reg = <0x0 0x2a410000 0x0 0x200>;
++ clocks = <&cru HCLK_TRNG_NS>;
++ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&cru SRST_H_TRNG_NS>;
++ };
++
+ otp: otp@2a580000 {
+ compatible = "rockchip,rk3576-otp";
+ reg = <0x0 0x2a580000 0x0 0x400>;
--- /dev/null
+From 3dfeccdd3cc88792e631539792a1ecc37a9581dc Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 6 May 2025 12:42:40 +0200
+Subject: [PATCH] arm64: dts: rockchip: Add RK3576 SAI nodes
+
+The RK3576 SoC has 10 SAI controllers in total. Five of them are in the
+video output power domains, and are used for digital audio output along
+with the video signal of those, e.g. HDMI audio.
+
+The other five, SAI0 through SAI4, are exposed externally. SAI0 and SAI1
+are capable of 8-channel audio, whereas SAI2, SAI3 and SAI4 are limited
+to two channels. These five are in the audio power domain.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-1-a8b5f5733ceb@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 200 +++++++++++++++++++++++
+ 1 file changed, 200 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1010,6 +1010,41 @@
+ status = "disabled";
+ };
+
++ sai5: sai@27d40000 {
++ compatible = "rockchip,rk3576-sai";
++ reg = <0x0 0x27d40000 0x0 0x1000>;
++ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru MCLK_SAI5_8CH>, <&cru HCLK_SAI5_8CH>;
++ clock-names = "mclk", "hclk";
++ dmas = <&dmac2 3>;
++ dma-names = "rx";
++ power-domains = <&power RK3576_PD_VO0>;
++ resets = <&cru SRST_M_SAI5_8CH>, <&cru SRST_H_SAI5_8CH>;
++ reset-names = "m", "h";
++ rockchip,sai-rx-route = <0 1 2 3>;
++ #sound-dai-cells = <0>;
++ sound-name-prefix = "SAI5";
++ status = "disabled";
++ };
++
++ sai6: sai@27d50000 {
++ compatible = "rockchip,rk3576-sai";
++ reg = <0x0 0x27d50000 0x0 0x1000>;
++ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru MCLK_SAI6_8CH>, <&cru HCLK_SAI6_8CH>;
++ clock-names = "mclk", "hclk";
++ dmas = <&dmac2 4>, <&dmac2 5>;
++ dma-names = "tx", "rx";
++ power-domains = <&power RK3576_PD_VO0>;
++ resets = <&cru SRST_M_SAI6_8CH>, <&cru SRST_H_SAI6_8CH>;
++ reset-names = "m", "h";
++ rockchip,sai-rx-route = <0 1 2 3>;
++ rockchip,sai-tx-route = <0 1 2 3>;
++ #sound-dai-cells = <0>;
++ sound-name-prefix = "SAI6";
++ status = "disabled";
++ };
++
+ hdmi: hdmi@27da0000 {
+ compatible = "rockchip,rk3576-dw-hdmi-qp";
+ reg = <0x0 0x27da0000 0x0 0x20000>;
+@@ -1050,6 +1085,57 @@
+ };
+ };
+
++ sai7: sai@27ed0000 {
++ compatible = "rockchip,rk3576-sai";
++ reg = <0x0 0x27ed0000 0x0 0x1000>;
++ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru MCLK_SAI7_8CH>, <&cru HCLK_SAI7_8CH>;
++ clock-names = "mclk", "hclk";
++ dmas = <&dmac2 19>;
++ dma-names = "tx";
++ power-domains = <&power RK3576_PD_VO1>;
++ resets = <&cru SRST_M_SAI7_8CH>, <&cru SRST_H_SAI7_8CH>;
++ reset-names = "m", "h";
++ rockchip,sai-tx-route = <0 1 2 3>;
++ #sound-dai-cells = <0>;
++ sound-name-prefix = "SAI7";
++ status = "disabled";
++ };
++
++ sai8: sai@27ee0000 {
++ compatible = "rockchip,rk3576-sai";
++ reg = <0x0 0x27ee0000 0x0 0x1000>;
++ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru MCLK_SAI8_8CH>, <&cru HCLK_SAI8_8CH>;
++ clock-names = "mclk", "hclk";
++ dmas = <&dmac1 7>;
++ dma-names = "tx";
++ power-domains = <&power RK3576_PD_VO1>;
++ resets = <&cru SRST_M_SAI8_8CH>, <&cru SRST_H_SAI8_8CH>;
++ reset-names = "m", "h";
++ rockchip,sai-tx-route = <0 1 2 3>;
++ #sound-dai-cells = <0>;
++ sound-name-prefix = "SAI8";
++ status = "disabled";
++ };
++
++ sai9: sai@27ef0000 {
++ compatible = "rockchip,rk3576-sai";
++ reg = <0x0 0x27ef0000 0x0 0x1000>;
++ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru MCLK_SAI9_8CH>, <&cru HCLK_SAI9_8CH>;
++ clock-names = "mclk", "hclk";
++ dmas = <&dmac0 26>;
++ dma-names = "tx";
++ power-domains = <&power RK3576_PD_VO1>;
++ resets = <&cru SRST_M_SAI9_8CH>, <&cru SRST_H_SAI9_8CH>;
++ reset-names = "m", "h";
++ rockchip,sai-tx-route = <0 1 2 3>;
++ #sound-dai-cells = <0>;
++ sound-name-prefix = "SAI9";
++ status = "disabled";
++ };
++
+ qos_hdcp1: qos@27f02000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f02000 0x0 0x20>;
+@@ -1604,6 +1690,120 @@
+ };
+ };
+
++ sai0: sai@2a600000 {
++ compatible = "rockchip,rk3576-sai";
++ reg = <0x0 0x2a600000 0x0 0x1000>;
++ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru MCLK_SAI0_8CH>, <&cru HCLK_SAI0_8CH>;
++ clock-names = "mclk", "hclk";
++ dmas = <&dmac0 0>, <&dmac0 1>;
++ dma-names = "tx", "rx";
++ power-domains = <&power RK3576_PD_AUDIO>;
++ resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>;
++ reset-names = "m", "h";
++ pinctrl-names = "default";
++ pinctrl-0 = <&sai0m0_lrck
++ &sai0m0_sclk
++ &sai0m0_sdi0
++ &sai0m0_sdi1
++ &sai0m0_sdi2
++ &sai0m0_sdi3
++ &sai0m0_sdo0
++ &sai0m0_sdo1
++ &sai0m0_sdo2
++ &sai0m0_sdo3>;
++ #sound-dai-cells = <0>;
++ sound-name-prefix = "SAI0";
++ status = "disabled";
++ };
++
++ sai1: sai@2a610000 {
++ compatible = "rockchip,rk3576-sai";
++ reg = <0x0 0x2a610000 0x0 0x1000>;
++ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru MCLK_SAI1_8CH>, <&cru HCLK_SAI1_8CH>;
++ clock-names = "mclk", "hclk";
++ dmas = <&dmac0 2>, <&dmac0 3>;
++ dma-names = "tx", "rx";
++ power-domains = <&power RK3576_PD_AUDIO>;
++ resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>;
++ reset-names = "m", "h";
++ pinctrl-names = "default";
++ pinctrl-0 = <&sai1m0_lrck
++ &sai1m0_sclk
++ &sai1m0_sdi0
++ &sai1m0_sdo0
++ &sai1m0_sdo1
++ &sai1m0_sdo2
++ &sai1m0_sdo3>;
++ #sound-dai-cells = <0>;
++ sound-name-prefix = "SAI1";
++ status = "disabled";
++ };
++
++ sai2: sai@2a620000 {
++ compatible = "rockchip,rk3576-sai";
++ reg = <0x0 0x2a620000 0x0 0x1000>;
++ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru MCLK_SAI2_2CH>, <&cru HCLK_SAI2_2CH>;
++ clock-names = "mclk", "hclk";
++ dmas = <&dmac1 0>, <&dmac1 1>;
++ dma-names = "tx", "rx";
++ power-domains = <&power RK3576_PD_AUDIO>;
++ resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>;
++ reset-names = "m", "h";
++ pinctrl-names = "default";
++ pinctrl-0 = <&sai2m0_lrck
++ &sai2m0_sclk
++ &sai2m0_sdi
++ &sai2m0_sdo>;
++ #sound-dai-cells = <0>;
++ sound-name-prefix = "SAI2";
++ status = "disabled";
++ };
++
++ sai3: sai@2a630000 {
++ compatible = "rockchip,rk3576-sai";
++ reg = <0x0 0x2a630000 0x0 0x1000>;
++ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru MCLK_SAI3_2CH>, <&cru HCLK_SAI3_2CH>;
++ clock-names = "mclk", "hclk";
++ dmas = <&dmac1 2>, <&dmac1 3>;
++ dma-names = "tx", "rx";
++ power-domains = <&power RK3576_PD_AUDIO>;
++ resets = <&cru SRST_M_SAI3_2CH>, <&cru SRST_H_SAI3_2CH>;
++ reset-names = "m", "h";
++ pinctrl-names = "default";
++ pinctrl-0 = <&sai3m0_lrck
++ &sai3m0_sclk
++ &sai3m0_sdi
++ &sai3m0_sdo>;
++ #sound-dai-cells = <0>;
++ sound-name-prefix = "SAI3";
++ status = "disabled";
++ };
++
++ sai4: sai@2a640000 {
++ compatible = "rockchip,rk3576-sai";
++ reg = <0x0 0x2a640000 0x0 0x1000>;
++ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru MCLK_SAI4_2CH>, <&cru HCLK_SAI4_2CH>;
++ clock-names = "mclk", "hclk";
++ dmas = <&dmac2 0>, <&dmac2 1>;
++ dma-names = "tx", "rx";
++ power-domains = <&power RK3576_PD_AUDIO>;
++ resets = <&cru SRST_M_SAI4_2CH>, <&cru SRST_H_SAI4_2CH>;
++ reset-names = "m", "h";
++ pinctrl-names = "default";
++ pinctrl-0 = <&sai4m0_lrck
++ &sai4m0_sclk
++ &sai4m0_sdi
++ &sai4m0_sdo>;
++ #sound-dai-cells = <0>;
++ sound-name-prefix = "SAI4";
++ status = "disabled";
++ };
++
+ gic: interrupt-controller@2a701000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0x2a701000 0 0x10000>,
--- /dev/null
+From 7f1561d82e3d3589038782f75faa50c65d9cdd42 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 6 May 2025 12:42:41 +0200
+Subject: [PATCH] arm64: dts: rockchip: Add RK3576 HDMI audio
+
+The RK3576 SoC now has upstream support for HDMI.
+
+Add an HDMI audio node, which uses SAI6 as its audio controller
+according to downstream.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250506-rk3576-sai-v4-2-a8b5f5733ceb@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -413,6 +413,22 @@
+ };
+ };
+
++ hdmi_sound: hdmi-sound {
++ compatible = "simple-audio-card";
++ simple-audio-card,name = "HDMI";
++ simple-audio-card,format = "i2s";
++ simple-audio-card,mclk-fs = <256>;
++ status = "disabled";
++
++ simple-audio-card,codec {
++ sound-dai = <&hdmi>;
++ };
++
++ simple-audio-card,cpu {
++ sound-dai = <&sai6>;
++ };
++ };
++
+ pmu_a53: pmu-a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+@@ -1069,6 +1085,7 @@
+ reset-names = "ref", "hdp";
+ rockchip,grf = <&ioc_grf>;
+ rockchip,vo-grf = <&vo0_grf>;
++ #sound-dai-cells = <0>;
+ status = "disabled";
+
+ ports {
--- /dev/null
+From ede1fa1384c230c9823f6bf1849cf50c5fc8a83e Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 20 May 2025 13:14:27 +0200
+Subject: [PATCH] arm64: dts: rockchip: Add missing SFC power-domains to rk3576
+
+Add the power-domains for the RK3576 SFC nodes according to the
+TRM part 1. This fixes potential SErrors when accessing the SFC
+registers without other peripherals (e.g. eMMC) doing a prior
+power-domain enable. For example this is easy to trigger on the
+Rock 4D, which enables the SFC0 interface, but does not enable
+the eMMC interface at the moment.
+
+Cc: stable@vger.kernel.org
+Fixes: 36299757129c8 ("arm64: dts: rockchip: Add SFC nodes for rk3576")
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20250520-rk3576-fix-fspi-pmdomain-v1-1-f07c6e62dadd@kernel.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1605,6 +1605,7 @@
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>;
+ clock-names = "clk_sfc", "hclk_sfc";
++ power-domains = <&power RK3576_PD_SDGMAC>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+@@ -1655,6 +1656,7 @@
+ interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>;
+ clock-names = "clk_sfc", "hclk_sfc";
++ power-domains = <&power RK3576_PD_NVM>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
--- /dev/null
+From 4d2587e0e1ce7145a38802fa281f4f1f411ec56f Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Mon, 19 May 2025 00:04:43 +0200
+Subject: [PATCH] arm64: dts: rockchip: fix rk3576 pcie unit addresses
+
+The rk3576 pcie nodes currently use the apb register as their unit address
+which is the second reg area defined in the binding.
+
+As can be seen by the dtc warnings like
+
+../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1346.24-1398.5: Warning (simple_bus_reg): /soc/pcie@2a200000: simple-bus unit address format error, expected "22000000"
+../arch/arm64/boot/dts/rockchip/rk3576.dtsi:1400.24-1452.5: Warning (simple_bus_reg): /soc/pcie@2a210000: simple-bus unit address format error, expected "22400000"
+
+using the first reg area as the unit address seems to be preferred.
+This is the dbi area per the binding, so adapt the unit address accordingly
+and move the nodes to their new position.
+
+Reported-by: kernel test robot <lkp@intel.com>
+Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250518220449.2722673-2-heiko@sntech.de
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 216 +++++++++++------------
+ 1 file changed, 108 insertions(+), 108 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -466,6 +466,114 @@
+ #size-cells = <2>;
+ ranges;
+
++ pcie0: pcie@22000000 {
++ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
++ reg = <0x0 0x22000000 0x0 0x00400000>,
++ <0x0 0x2a200000 0x0 0x00010000>,
++ <0x0 0x20000000 0x0 0x00100000>;
++ reg-names = "dbi", "apb", "config";
++ bus-range = <0x0 0xf>;
++ clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
++ <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
++ <&cru CLK_PCIE0_AUX>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk",
++ "aux";
++ device_type = "pci";
++ interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
++ <0 0 0 2 &pcie0_intc 1>,
++ <0 0 0 3 &pcie0_intc 2>,
++ <0 0 0 4 &pcie0_intc 3>;
++ linux,pci-domain = <0>;
++ max-link-speed = <2>;
++ num-ib-windows = <8>;
++ num-viewport = <8>;
++ num-ob-windows = <2>;
++ num-lanes = <1>;
++ phys = <&combphy0_ps PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy";
++ power-domains = <&power RK3576_PD_PHP>;
++ ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
++ 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
++ 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
++ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
++ reset-names = "pwr", "pipe";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ status = "disabled";
++
++ pcie0_intc: legacy-interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
++ };
++ };
++
++ pcie1: pcie@22400000 {
++ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
++ reg = <0x0 0x22400000 0x0 0x00400000>,
++ <0x0 0x2a210000 0x0 0x00010000>,
++ <0x0 0x21000000 0x0 0x00100000>;
++ reg-names = "dbi", "apb", "config";
++ bus-range = <0x20 0x2f>;
++ clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
++ <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
++ <&cru CLK_PCIE1_AUX>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk",
++ "aux";
++ device_type = "pci";
++ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
++ <0 0 0 2 &pcie1_intc 1>,
++ <0 0 0 3 &pcie1_intc 2>,
++ <0 0 0 4 &pcie1_intc 3>;
++ linux,pci-domain = <0>;
++ max-link-speed = <2>;
++ num-ib-windows = <8>;
++ num-viewport = <8>;
++ num-ob-windows = <2>;
++ num-lanes = <1>;
++ phys = <&combphy1_psu PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy";
++ power-domains = <&power RK3576_PD_SUBPHP>;
++ ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
++ 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
++ 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
++ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
++ reset-names = "pwr", "pipe";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ status = "disabled";
++
++ pcie1_intc: legacy-interrupt-controller {
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
++ };
++ };
++
+ usb_drd0_dwc3: usb@23000000 {
+ compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
+ reg = <0x0 0x23000000 0x0 0x400000>;
+@@ -1343,114 +1451,6 @@
+ reg = <0x0 0x27f22100 0x0 0x20>;
+ };
+
+- pcie0: pcie@2a200000 {
+- compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+- reg = <0x0 0x22000000 0x0 0x00400000>,
+- <0x0 0x2a200000 0x0 0x00010000>,
+- <0x0 0x20000000 0x0 0x00100000>;
+- reg-names = "dbi", "apb", "config";
+- bus-range = <0x0 0xf>;
+- clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
+- <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
+- <&cru CLK_PCIE0_AUX>;
+- clock-names = "aclk_mst", "aclk_slv",
+- "aclk_dbi", "pclk",
+- "aux";
+- device_type = "pci";
+- interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
+- #interrupt-cells = <1>;
+- interrupt-map-mask = <0 0 0 7>;
+- interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+- <0 0 0 2 &pcie0_intc 1>,
+- <0 0 0 3 &pcie0_intc 2>,
+- <0 0 0 4 &pcie0_intc 3>;
+- linux,pci-domain = <0>;
+- max-link-speed = <2>;
+- num-ib-windows = <8>;
+- num-viewport = <8>;
+- num-ob-windows = <2>;
+- num-lanes = <1>;
+- phys = <&combphy0_ps PHY_TYPE_PCIE>;
+- phy-names = "pcie-phy";
+- power-domains = <&power RK3576_PD_PHP>;
+- ranges = <0x01000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
+- 0x02000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
+- 0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
+- resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+- reset-names = "pwr", "pipe";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- status = "disabled";
+-
+- pcie0_intc: legacy-interrupt-controller {
+- interrupt-controller;
+- #address-cells = <0>;
+- #interrupt-cells = <1>;
+- interrupt-parent = <&gic>;
+- interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
+- };
+- };
+-
+- pcie1: pcie@2a210000 {
+- compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+- reg = <0x0 0x22400000 0x0 0x00400000>,
+- <0x0 0x2a210000 0x0 0x00010000>,
+- <0x0 0x21000000 0x0 0x00100000>;
+- reg-names = "dbi", "apb", "config";
+- bus-range = <0x20 0x2f>;
+- clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
+- <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
+- <&cru CLK_PCIE1_AUX>;
+- clock-names = "aclk_mst", "aclk_slv",
+- "aclk_dbi", "pclk",
+- "aux";
+- device_type = "pci";
+- interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
+- <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-names = "sys", "pmc", "msg", "legacy", "err", "msi";
+- #interrupt-cells = <1>;
+- interrupt-map-mask = <0 0 0 7>;
+- interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+- <0 0 0 2 &pcie1_intc 1>,
+- <0 0 0 3 &pcie1_intc 2>,
+- <0 0 0 4 &pcie1_intc 3>;
+- linux,pci-domain = <0>;
+- max-link-speed = <2>;
+- num-ib-windows = <8>;
+- num-viewport = <8>;
+- num-ob-windows = <2>;
+- num-lanes = <1>;
+- phys = <&combphy1_psu PHY_TYPE_PCIE>;
+- phy-names = "pcie-phy";
+- power-domains = <&power RK3576_PD_SUBPHP>;
+- ranges = <0x01000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
+- 0x02000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
+- 0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
+- resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+- reset-names = "pwr", "pipe";
+- #address-cells = <3>;
+- #size-cells = <2>;
+- status = "disabled";
+-
+- pcie1_intc: legacy-interrupt-controller {
+- interrupt-controller;
+- #address-cells = <0>;
+- #interrupt-cells = <1>;
+- interrupt-parent = <&gic>;
+- interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
+- };
+- };
+-
+ gmac0: ethernet@2a220000 {
+ compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0x2a220000 0x0 0x10000>;
--- /dev/null
+From 8ff721f60257d550daf524fc559c0f0d2176b198 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Mon, 19 May 2025 00:04:44 +0200
+Subject: [PATCH] arm64: dts: rockchip: move rk3576 pinctrl node outside the
+ soc node
+
+The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
+as dtc points out:
+
+../arch/arm64/boot/dts/rockchip/rk3576.dtsi:2351.20-2417.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property
+
+Move the pinctrl node outside and adapt the indentation.
+
+Reported-by: kernel test robot <lkp@intel.com>
+Closes: https://lore.kernel.org/oe-kbuild-all/202505150745.PQT9TLYX-lkp@intel.com/
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250518220449.2722673-3-heiko@sntech.de
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 136 +++++++++++------------
+ 1 file changed, 68 insertions(+), 68 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -429,6 +429,74 @@
+ };
+ };
+
++ pinctrl: pinctrl {
++ compatible = "rockchip,rk3576-pinctrl";
++ rockchip,grf = <&ioc_grf>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ gpio0: gpio@27320000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0x27320000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
++ gpio-controller;
++ gpio-ranges = <&pinctrl 0 0 32>;
++ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-controller;
++ #gpio-cells = <2>;
++ #interrupt-cells = <2>;
++ };
++
++ gpio1: gpio@2ae10000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0x2ae10000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
++ gpio-controller;
++ gpio-ranges = <&pinctrl 0 32 32>;
++ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-controller;
++ #gpio-cells = <2>;
++ #interrupt-cells = <2>;
++ };
++
++ gpio2: gpio@2ae20000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0x2ae20000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
++ gpio-controller;
++ gpio-ranges = <&pinctrl 0 64 32>;
++ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-controller;
++ #gpio-cells = <2>;
++ #interrupt-cells = <2>;
++ };
++
++ gpio3: gpio@2ae30000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0x2ae30000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
++ gpio-controller;
++ gpio-ranges = <&pinctrl 0 96 32>;
++ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-controller;
++ #gpio-cells = <2>;
++ #interrupt-cells = <2>;
++ };
++
++ gpio4: gpio@2ae40000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0x2ae40000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
++ gpio-controller;
++ gpio-ranges = <&pinctrl 0 128 32>;
++ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-controller;
++ #gpio-cells = <2>;
++ #interrupt-cells = <2>;
++ };
++ };
++
+ pmu_a53: pmu-a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+@@ -2349,74 +2417,6 @@
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x4010f000 0x0 0x100>;
+ };
+-
+- pinctrl: pinctrl {
+- compatible = "rockchip,rk3576-pinctrl";
+- rockchip,grf = <&ioc_grf>;
+- #address-cells = <2>;
+- #size-cells = <2>;
+- ranges;
+-
+- gpio0: gpio@27320000 {
+- compatible = "rockchip,gpio-bank";
+- reg = <0x0 0x27320000 0x0 0x200>;
+- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+- gpio-controller;
+- gpio-ranges = <&pinctrl 0 0 32>;
+- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-controller;
+- #gpio-cells = <2>;
+- #interrupt-cells = <2>;
+- };
+-
+- gpio1: gpio@2ae10000 {
+- compatible = "rockchip,gpio-bank";
+- reg = <0x0 0x2ae10000 0x0 0x200>;
+- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+- gpio-controller;
+- gpio-ranges = <&pinctrl 0 32 32>;
+- interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-controller;
+- #gpio-cells = <2>;
+- #interrupt-cells = <2>;
+- };
+-
+- gpio2: gpio@2ae20000 {
+- compatible = "rockchip,gpio-bank";
+- reg = <0x0 0x2ae20000 0x0 0x200>;
+- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+- gpio-controller;
+- gpio-ranges = <&pinctrl 0 64 32>;
+- interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-controller;
+- #gpio-cells = <2>;
+- #interrupt-cells = <2>;
+- };
+-
+- gpio3: gpio@2ae30000 {
+- compatible = "rockchip,gpio-bank";
+- reg = <0x0 0x2ae30000 0x0 0x200>;
+- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+- gpio-controller;
+- gpio-ranges = <&pinctrl 0 96 32>;
+- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-controller;
+- #gpio-cells = <2>;
+- #interrupt-cells = <2>;
+- };
+-
+- gpio4: gpio@2ae40000 {
+- compatible = "rockchip,gpio-bank";
+- reg = <0x0 0x2ae40000 0x0 0x200>;
+- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+- gpio-controller;
+- gpio-ranges = <&pinctrl 0 128 32>;
+- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+- interrupt-controller;
+- #gpio-cells = <2>;
+- #interrupt-cells = <2>;
+- };
+- };
+ };
+ };
+
--- /dev/null
+From f8b11d8cfbfc8a0232c1e7cc6af10583c8bdb3f1 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Mon, 19 May 2025 00:04:45 +0200
+Subject: [PATCH] arm64: dts: rockchip: remove a double-empty line from rk3576
+ core dtsi
+
+Two empty lines between nodes, is one too many.
+
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250518220449.2722673-4-heiko@sntech.de
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -2002,7 +2002,6 @@
+ status = "disabled";
+ };
+
+-
+ i2c6: i2c@2ac90000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x2ac90000 0x0 0x1000>;
--- /dev/null
+From af0f43d5d0d6e486b6a83190000dfa7ad447f825 Mon Sep 17 00:00:00 2001
+From: Shawn Lin <shawn.lin@rock-chips.com>
+Date: Tue, 3 Jun 2025 10:35:40 +0800
+Subject: [PATCH] arm64: dts: rockchip: fix rk3576 pcie1 linux,pci-domain
+
+pcie0 already used 0 as its pci-domain, so pcie1 will fail to
+allocate the same pci-domain if both of them are used.
+
+rk-pcie 2a210000.pcie: PCIe Link up, LTSSM is 0x130011
+rk-pcie 2a210000.pcie: PCIe Gen.2 x1 link up
+rk-pcie 2a210000.pcie: Scanning root bridge failed
+rk-pcie 2a210000.pcie: failed to initialize host
+
+Fixes: d4b9fc2af45d ("arm64: dts: rockchip: Add rk3576 pcie nodes")
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Link: https://lore.kernel.org/r/1748918140-212263-1-git-send-email-shawn.lin@rock-chips.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -615,7 +615,7 @@
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
+- linux,pci-domain = <0>;
++ linux,pci-domain = <1>;
+ max-link-speed = <2>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
--- /dev/null
+From e490f854b46369b096f3d09c0c6a00f340425136 Mon Sep 17 00:00:00 2001
+From: Alexey Charkov <alchark@gmail.com>
+Date: Sat, 14 Jun 2025 22:14:34 +0400
+Subject: [PATCH] arm64: dts: rockchip: add SDIO controller on RK3576
+
+RK3576 has one more SD/MMC controller than are currently listed in its
+.dtsi, with the missing one intended as an SDIO controller. Add the
+missing node (tested with the onboard WiFi module on ArmSoM Sige5 v1.2)
+
+Signed-off-by: Alexey Charkov <alchark@gmail.com>
+Link: https://lore.kernel.org/r/20250614-sige5-updates-v2-2-3bb31b02623c@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1695,6 +1695,22 @@
+ status = "disabled";
+ };
+
++ sdio: mmc@2a320000 {
++ compatible = "rockchip,rk3576-dw-mshc";
++ reg = <0x0 0x2a320000 0x0 0x4000>;
++ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>;
++ clock-names = "biu", "ciu";
++ fifo-depth = <0x100>;
++ interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
++ max-frequency = <200000000>;
++ pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>;
++ pinctrl-names = "default";
++ power-domains = <&power RK3576_PD_SDGMAC>;
++ resets = <&cru SRST_H_SDIO>;
++ reset-names = "reset";
++ status = "disabled";
++ };
++
+ sdhci: mmc@2a330000 {
+ compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
+ reg = <0x0 0x2a330000 0x0 0x10000>;
--- /dev/null
+From aba7987a536cee67fb0cb724099096fd8f8f5350 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Thu, 12 Jun 2025 00:47:48 +0300
+Subject: [PATCH] arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576
+
+As with the RK3588 SoC, the HDMI PHY PLL on RK3576 can be used as a more
+accurate pixel clock source for VOP2, which is actually mandatory to
+ensure proper support for display modes handling.
+
+Add the missing #clock-cells property to allow using the clock provider
+functionality of HDMI PHY.
+
+Fixes: ad0ea230ab2a ("arm64: dts: rockchip: Add hdmi for rk3576")
+Cc: stable@vger.kernel.org
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-2-4b11007d8675@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -2407,6 +2407,7 @@
+ reg = <0x0 0x2b000000 0x0 0x2000>;
+ clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>;
+ clock-names = "ref", "apb";
++ #clock-cells = <0>;
+ resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>,
+ <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>;
+ reset-names = "apb", "init", "cmn", "lane";
--- /dev/null
+From 4ab8b8ac952fb08d03655e1da0cfee07589e428f Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Thu, 12 Jun 2025 00:47:49 +0300
+Subject: [PATCH] arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2
+ on rk3576
+
+Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS
+char rate via phy_configure_opts_hdmi"), the workaround of passing the
+rate from DW HDMI QP bridge driver via phy_set_bus_width() became
+partially broken, as it cannot reliably handle mode switches anymore.
+
+Attempting to fix this up at PHY level would not only introduce
+additional hacks, but it would also fail to adequately resolve the
+display issues that are a consequence of the system CRU limitations.
+
+Instead, proceed with the solution already implemented for RK3588: make
+use of the HDMI PHY PLL as a better suited DCLK source for VOP2. This
+will not only address the aforementioned problem, but it should also
+facilitate the proper operation of display modes up to 4K@60Hz.
+
+It's worth noting that anything above 4K@30Hz still requires high TMDS
+clock ratio and scrambling support, which hasn't been mainlined yet.
+
+Fixes: d74b842cab08 ("arm64: dts: rockchip: Add vop for rk3576")
+Cc: stable@vger.kernel.org
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Tested-By: Detlev Casanova <detlev.casanova@collabora.com>
+Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-3-4b11007d8675@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1155,12 +1155,14 @@
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VP0>,
+ <&cru DCLK_VP1>,
+- <&cru DCLK_VP2>;
++ <&cru DCLK_VP2>,
++ <&hdptxphy>;
+ clock-names = "aclk",
+ "hclk",
+ "dclk_vp0",
+ "dclk_vp1",
+- "dclk_vp2";
++ "dclk_vp2",
++ "pll_hdmiphy0";
+ iommus = <&vop_mmu>;
+ power-domains = <&power RK3576_PD_VOP>;
+ rockchip,grf = <&sys_grf>;
--- /dev/null
+From 15e8ba9d8b14ae6de415186622379f5f4dcfd141 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 10 Jun 2025 14:32:42 +0200
+Subject: [PATCH] arm64: dts: rockchip: Add thermal nodes to RK3576
+
+Add the TSADC node to the RK3576. Additionally, add everything the TSADC
+needs to function, i.e. thermal zones, their trip points and maps, as
+well as adjust the CPU cooling-cells property.
+
+The polling-delay properties are set to 0 as we do have interrupts for
+this TSADC on this particular SoC, though the polling-delay-passive
+properties are set to 100 for the thermal zones that have a passive
+cooling device, as otherwise the thermal throttling behaviour never
+unthrottles.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-6-b6e9efbf1015@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 164 ++++++++++++++++++++++-
+ 1 file changed, 162 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -11,6 +11,7 @@
+ #include <dt-bindings/power/rockchip,rk3576-power.h>
+ #include <dt-bindings/reset/rockchip,rk3576-cru.h>
+ #include <dt-bindings/soc/rockchip,boot-mode.h>
++#include <dt-bindings/thermal/thermal.h>
+
+ / {
+ compatible = "rockchip,rk3576";
+@@ -113,9 +114,9 @@
+ capacity-dmips-mhz = <485>;
+ clocks = <&scmi_clk SCMI_ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+- #cooling-cells = <2>;
+ dynamic-power-coefficient = <120>;
+ cpu-idle-states = <&CPU_SLEEP>;
++ #cooling-cells = <2>;
+ };
+
+ cpu_l1: cpu@1 {
+@@ -127,6 +128,7 @@
+ clocks = <&scmi_clk SCMI_ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
++ #cooling-cells = <2>;
+ };
+
+ cpu_l2: cpu@2 {
+@@ -138,6 +140,7 @@
+ clocks = <&scmi_clk SCMI_ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
++ #cooling-cells = <2>;
+ };
+
+ cpu_l3: cpu@3 {
+@@ -149,6 +152,7 @@
+ clocks = <&scmi_clk SCMI_ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
++ #cooling-cells = <2>;
+ };
+
+ cpu_b0: cpu@100 {
+@@ -159,9 +163,9 @@
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk SCMI_ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+- #cooling-cells = <2>;
+ dynamic-power-coefficient = <320>;
+ cpu-idle-states = <&CPU_SLEEP>;
++ #cooling-cells = <2>;
+ };
+
+ cpu_b1: cpu@101 {
+@@ -173,6 +177,7 @@
+ clocks = <&scmi_clk SCMI_ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
++ #cooling-cells = <2>;
+ };
+
+ cpu_b2: cpu@102 {
+@@ -184,6 +189,7 @@
+ clocks = <&scmi_clk SCMI_ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
++ #cooling-cells = <2>;
+ };
+
+ cpu_b3: cpu@103 {
+@@ -195,6 +201,7 @@
+ clocks = <&scmi_clk SCMI_ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
++ #cooling-cells = <2>;
+ };
+
+ idle-states {
+@@ -520,6 +527,143 @@
+ method = "smc";
+ };
+
++ thermal_zones: thermal-zones {
++ /* sensor near the center of the SoC */
++ package_thermal: package-thermal {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsadc 0>;
++
++ trips {
++ package_crit: package-crit {
++ temperature = <115000>;
++ hysteresis = <0>;
++ type = "critical";
++ };
++ };
++ };
++
++ /* sensor for cluster1 (big Cortex-A72 cores) */
++ bigcore_thermal: bigcore-thermal {
++ polling-delay-passive = <100>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsadc 1>;
++
++ trips {
++ bigcore_alert: bigcore-alert {
++ temperature = <85000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++
++ bigcore_crit: bigcore-crit {
++ temperature = <115000>;
++ hysteresis = <0>;
++ type = "critical";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&bigcore_alert>;
++ cooling-device =
++ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++ };
++ };
++ };
++
++ /* sensor for cluster0 (little Cortex-A53 cores) */
++ littlecore_thermal: littlecore-thermal {
++ polling-delay-passive = <100>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsadc 2>;
++
++ trips {
++ littlecore_alert: littlecore-alert {
++ temperature = <85000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++
++ littlecore_crit: littlecore-crit {
++ temperature = <115000>;
++ hysteresis = <0>;
++ type = "critical";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&littlecore_alert>;
++ cooling-device =
++ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++ };
++ };
++ };
++
++ gpu_thermal: gpu-thermal {
++ polling-delay-passive = <100>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsadc 3>;
++
++ trips {
++ gpu_alert: gpu-alert {
++ temperature = <85000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++
++ gpu_crit: gpu-crit {
++ temperature = <115000>;
++ hysteresis = <0>;
++ type = "critical";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&gpu_alert>;
++ cooling-device =
++ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++ };
++ };
++ };
++
++ npu_thermal: npu-thermal {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsadc 4>;
++
++ trips {
++ npu_crit: npu-crit {
++ temperature = <115000>;
++ hysteresis = <0>;
++ type = "critical";
++ };
++ };
++ };
++
++ ddr_thermal: ddr-thermal {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&tsadc 5>;
++
++ trips {
++ ddr_crit: ddr-crit {
++ temperature = <115000>;
++ hysteresis = <0>;
++ type = "critical";
++ };
++ };
++ };
++ };
++
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+@@ -2303,6 +2447,22 @@
+ status = "disabled";
+ };
+
++ tsadc: tsadc@2ae70000 {
++ compatible = "rockchip,rk3576-tsadc";
++ reg = <0x0 0x2ae70000 0x0 0x400>;
++ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
++ clock-names = "tsadc", "apb_pclk";
++ assigned-clocks = <&cru CLK_TSADC>;
++ assigned-clock-rates = <2000000>;
++ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
++ reset-names = "tsadc-apb", "tsadc";
++ #thermal-sensor-cells = <1>;
++ rockchip,hw-tshut-temp = <120000>;
++ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
++ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
++ };
++
+ i2c9: i2c@2ae80000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x2ae80000 0x0 0x1000>;
--- /dev/null
+From a4053badacf3699023527392c947314b074f5e0e Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Tue, 10 Jun 2025 14:32:43 +0200
+Subject: [PATCH] arm64: dts: rockchip: Add thermal trim OTP and tsadc nodes
+
+Thanks to Heiko's work getting OTP working on the RK3576, we can specify
+the thermal sensor trim values which are stored there now, and with my
+driver addition to rockchip_thermal, we can make use of these.
+
+Add them to the devicetree for the SoC.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250610-rk3576-tsadc-upstream-v6-7-b6e9efbf1015@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 57 ++++++++++++++++++++++++
+ 1 file changed, 57 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1937,6 +1937,30 @@
+ log_leakage: log-leakage@22 {
+ reg = <0x22 0x1>;
+ };
++ bigcore_tsadc_trim: bigcore-tsadc-trim@24 {
++ reg = <0x24 0x2>;
++ bits = <0 10>;
++ };
++ litcore_tsadc_trim: litcore-tsadc-trim@26 {
++ reg = <0x26 0x2>;
++ bits = <0 10>;
++ };
++ ddr_tsadc_trim: ddr-tsadc-trim@28 {
++ reg = <0x28 0x2>;
++ bits = <0 10>;
++ };
++ npu_tsadc_trim: npu-tsadc-trim@2a {
++ reg = <0x2a 0x2>;
++ bits = <0 10>;
++ };
++ gpu_tsadc_trim: gpu-tsadc-trim@2c {
++ reg = <0x2c 0x2>;
++ bits = <0 10>;
++ };
++ soc_tsadc_trim: soc-tsadc-trim@64 {
++ reg = <0x64 0x2>;
++ bits = <0 10>;
++ };
+ };
+
+ sai0: sai@2a600000 {
+@@ -2461,6 +2485,39 @@
+ rockchip,hw-tshut-temp = <120000>;
+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ sensor@0 {
++ reg = <0>;
++ nvmem-cells = <&soc_tsadc_trim>;
++ nvmem-cell-names = "trim";
++ };
++ sensor@1 {
++ reg = <1>;
++ nvmem-cells = <&bigcore_tsadc_trim>;
++ nvmem-cell-names = "trim";
++ };
++ sensor@2 {
++ reg = <2>;
++ nvmem-cells = <&litcore_tsadc_trim>;
++ nvmem-cell-names = "trim";
++ };
++ sensor@3 {
++ reg = <3>;
++ nvmem-cells = <&ddr_tsadc_trim>;
++ nvmem-cell-names = "trim";
++ };
++ sensor@4 {
++ reg = <4>;
++ nvmem-cells = <&npu_tsadc_trim>;
++ nvmem-cell-names = "trim";
++ };
++ sensor@5 {
++ reg = <5>;
++ nvmem-cells = <&gpu_tsadc_trim>;
++ nvmem-cell-names = "trim";
++ };
+ };
+
+ i2c9: i2c@2ae80000 {
--- /dev/null
+From 21bc1a7fcea4635a49f6b2eff3e4c661e80e8f43 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Mon, 7 Jul 2025 18:49:03 +0200
+Subject: [PATCH] arm64: dts: rockchip: add mipi-dcphy to rk3576
+
+Add the MIPI-DC-phy node to the RK3576, that will be used by the one
+DSI2 controller and hopefully in some future also for camera input.
+
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250707164906.1445288-11-heiko@sntech.de
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -966,6 +966,12 @@
+ reg = <0x0 0x26032000 0x0 0x100>;
+ };
+
++ mipidcphy_grf: syscon@26034000 {
++ compatible = "rockchip,rk3576-dcphy-grf", "syscon";
++ reg = <0x0 0x26034000 0x0 0x2000>;
++ clocks = <&cru PCLK_PMUPHY_ROOT>;
++ };
++
+ vo1_grf: syscon@26036000 {
+ compatible = "rockchip,rk3576-vo1-grf", "syscon";
+ reg = <0x0 0x26036000 0x0 0x100>;
+@@ -2563,6 +2569,22 @@
+ status = "disabled";
+ };
+
++ mipidcphy: phy@2b020000 {
++ compatible = "rockchip,rk3576-mipi-dcphy";
++ reg = <0x0 0x2b020000 0x0 0x10000>;
++ clocks = <&cru PCLK_MIPI_DCPHY>,
++ <&cru CLK_PHY_REF_SRC>;
++ clock-names = "pclk", "ref";
++ resets = <&cru SRST_M_MIPI_DCPHY>,
++ <&cru SRST_P_MIPI_DCPHY>,
++ <&cru SRST_P_DCPHY_GRF>,
++ <&cru SRST_S_MIPI_DCPHY>;
++ reset-names = "m_phy", "apb", "grf", "s_phy";
++ rockchip,grf = <&mipidcphy_grf>;
++ #phy-cells = <1>;
++ status = "disabled";
++ };
++
+ combphy0_ps: phy@2b050000 {
+ compatible = "rockchip,rk3576-naneng-combphy";
+ reg = <0x0 0x2b050000 0x0 0x100>;
--- /dev/null
+From e51828f80df99a2899e263b750cada6426f14c92 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Mon, 7 Jul 2025 18:49:04 +0200
+Subject: [PATCH] arm64: dts: rockchip: add the dsi controller to rk3576
+
+The RK3576 comes with one DSI2 controllers based on the same newer
+Synopsis IP as the ones on the RK3588.
+
+Add the necessary node for it.
+
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250707164906.1445288-12-heiko@sntech.de
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 28 ++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -1389,6 +1389,34 @@
+ status = "disabled";
+ };
+
++ dsi: dsi@27d80000 {
++ compatible = "rockchip,rk3576-mipi-dsi2";
++ reg = <0x0 0x27d80000 0x0 0x10000>;
++ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
++ clock-names = "pclk", "sys";
++ power-domains = <&power RK3576_PD_VO0>;
++ resets = <&cru SRST_P_DSIHOST0>;
++ reset-names = "apb";
++ phys = <&mipidcphy PHY_TYPE_DPHY>;
++ phy-names = "dcphy";
++ rockchip,grf = <&vo0_grf>;
++ status = "disabled";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ dsi_in: port@0 {
++ reg = <0>;
++ };
++
++ dsi_out: port@1 {
++ reg = <1>;
++ };
++ };
++ };
++
+ hdmi: hdmi@27da0000 {
+ compatible = "rockchip,rk3576-dw-hdmi-qp";
+ reg = <0x0 0x27da0000 0x0 0x20000>;
--- /dev/null
+From 9c059700fee595142676a9bbaff6e40e3fcd9cbb Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 18 Aug 2025 19:18:40 +0200
+Subject: [PATCH] arm64: dts: rockchip: Enable RK3576 watchdog
+
+The RK3576 watchdog does not need any board specific resources, so
+let's enable it by default just like we do for RK3588.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20250818-rk3576-watchdog-v1-1-28f82e01029c@kernel.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+@@ -2275,7 +2275,6 @@
+ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
+ clock-names = "tclk", "pclk";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+- status = "disabled";
+ };
+
+ spi0: spi@2acf0000 {
--- /dev/null
+From a0fb7eca9c099867596cbd1a44cc740882bdcbbe Mon Sep 17 00:00:00 2001
+From: Stephen Chen <stephen@radxa.com>
+Date: Tue, 18 Feb 2025 11:04:19 -0500
+Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 4D device tree
+
+The Radxa ROCK 4D board is based on the Rockchip rk3576 SoC.
+
+The device tree adds support for basic devices:
+ - UART
+ - SD Card
+ - Ethernet
+ - USB
+ - RTC
+
+It has 4 USB ports but only 3 are usable as the top left one is used
+for maskrom.
+
+It has a USB-C port that is only used for powering the board.
+
+Signed-off-by: Stephen Chen <stephen@radxa.com>
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+Link: https://lore.kernel.org/r/20250218160714.140709-3-detlev.casanova@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../boot/dts/rockchip/rk3576-rock-4d.dts | 689 ++++++++++++++++++
+ 2 files changed, 690 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-rock-4d.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-coolpi-cm5-evb.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+@@ -0,0 +1,689 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd.
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include <dt-bindings/usb/pd.h>
++#include "rk3576.dtsi"
++
++/ {
++ model = "Radxa ROCK 4D";
++ compatible = "radxa,rock-4d", "rockchip,rk3576";
++
++ aliases {
++ ethernet0 = &gmac0;
++ mmc0 = &sdmmc;
++ };
++
++ chosen {
++ stdout-path = "serial0:1500000n8";
++ };
++
++ leds: leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&led_rgb_g &led_rgb_r>;
++
++ power-led {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_STATUS;
++ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-on";
++ };
++
++ user-led {
++ color = <LED_COLOR_ID_BLUE>;
++ function = LED_FUNCTION_HEARTBEAT;
++ gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ vcc_12v0_dcin: regulator-vcc-12v0-dcin {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <12000000>;
++ regulator-max-microvolt = <12000000>;
++ regulator-name = "vcc_12v0_dcin";
++ };
++
++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
++ regulator-name = "vcc_1v1_nldo_s3";
++ vin-supply = <&vcc_5v0_sys>;
++ };
++
++ vcc_1v2_ufs_vccq_s0: regulator-vcc-1v2-ufs-vccq-s0 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-name = "vcc_1v2_ufs_vccq_s0";
++ vin-supply = <&vcc_5v0_sys>;
++ };
++
++ vcc_1v8_s0: regulator-vcc-1v8-s0 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s0";
++ vin-supply = <&vcc_1v8_s3>;
++ };
++
++ vcc_1v8_ufs_vccq2_s0: regulator-vcc-1v8-ufs-vccq2-s0 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_ufs_vccq2_s0";
++ vin-supply = <&vcc_1v8_s3>;
++ };
++
++ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <2000000>;
++ regulator-max-microvolt = <2000000>;
++ regulator-name = "vcc_2v0_pldo_s3";
++ vin-supply = <&vcc_5v0_sys>;
++ };
++
++ vcc_3v3_pcie: regulator-vcc-3v3-pcie {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie_pwren>;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_pcie";
++ startup-delay-us = <5000>;
++ vin-supply = <&vcc_5v0_sys>;
++ };
++
++ vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_rtc_s5";
++ vin-supply = <&vcc_5v0_sys>;
++ };
++
++ vcc_3v3_s0: regulator-vcc-3v3-s0 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_s0";
++ vin-supply = <&vcc_3v3_s3>;
++ };
++
++ vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_ufs_s0";
++ vin-supply = <&vcc_5v0_sys>;
++ };
++
++ vcc_5v0_device: regulator-vcc-5v0-device {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc_5v0_device";
++ vin-supply = <&vcc_12v0_dcin>;
++ };
++
++ vcc_5v0_host: regulator-vcc-5v0-host {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_host_pwren>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v0_host";
++ vin-supply = <&vcc_5v0_device>;
++ };
++
++ vcc_5v0_sys: regulator-vcc-5v0-sys {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc_5v0_sys";
++ vin-supply = <&vcc_12v0_dcin>;
++ };
++};
++
++&combphy1_psu {
++ status = "okay";
++};
++
++&cpu_b0 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_b1 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_b2 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_b3 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_l0 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l1 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l2 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l3 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&gmac0 {
++ clock_in_out = "output";
++ phy-handle = <&rgmii_phy0>;
++ phy-mode = "rgmii-id";
++ pinctrl-names = "default";
++ pinctrl-0 = <ð0m0_miim
++ ð0m0_tx_bus2
++ ð0m0_rx_bus2
++ ð0m0_rgmii_clk
++ ð0m0_rgmii_bus
++ ðm0_clk0_25m_out>;
++ status = "okay";
++};
++
++&gpu {
++ mali-supply = <&vdd_gpu_s0>;
++ status = "okay";
++};
++
++&i2c1 {
++ status = "okay";
++
++ pmic@23 {
++ compatible = "rockchip,rk806";
++ reg = <0x23>;
++ #gpio-cells = <2>;
++ gpio-controller;
++ interrupt-parent = <&gpio0>;
++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_pins
++ &rk806_dvs1_null
++ &rk806_dvs2_null
++ &rk806_dvs3_null>;
++ system-power-controller;
++ vcc1-supply = <&vcc_5v0_sys>;
++ vcc2-supply = <&vcc_5v0_sys>;
++ vcc3-supply = <&vcc_5v0_sys>;
++ vcc4-supply = <&vcc_5v0_sys>;
++ vcc5-supply = <&vcc_5v0_sys>;
++ vcc6-supply = <&vcc_5v0_sys>;
++ vcc7-supply = <&vcc_5v0_sys>;
++ vcc8-supply = <&vcc_5v0_sys>;
++ vcc9-supply = <&vcc_5v0_sys>;
++ vcc10-supply = <&vcc_5v0_sys>;
++ vcc11-supply = <&vcc_2v0_pldo_s3>;
++ vcc12-supply = <&vcc_5v0_sys>;
++ vcc13-supply = <&vcc_1v1_nldo_s3>;
++ vcc14-supply = <&vcc_1v1_nldo_s3>;
++ vcca-supply = <&vcc_5v0_sys>;
++
++ rk806_dvs1_null: dvs1-null-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun2";
++ };
++
++ rk806_dvs1_rst: dvs1-rst-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun3";
++ };
++
++ rk806_dvs1_slp: dvs1-slp-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun1";
++ };
++
++ rk806_dvs2_dvs: dvs2-dvs-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun4";
++ };
++
++ rk806_dvs2_gpio: dvs2-gpio-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun5";
++ };
++
++ rk806_dvs2_null: dvs2-null-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun2";
++ };
++
++ rk806_dvs2_rst: dvs2-rst-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun3";
++ };
++
++ rk806_dvs2_slp: dvs2-slp-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun1";
++ };
++
++ rk806_dvs3_dvs: dvs3-dvs-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun4";
++ };
++
++ rk806_dvs3_gpio: dvs3-gpio-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun5";
++ };
++
++ rk806_dvs3_null: dvs3-null-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun2";
++ };
++
++ rk806_dvs3_rst: dvs3-rst-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun3";
++ };
++
++ rk806_dvs3_slp: dvs3-slp-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun1";
++ };
++
++ regulators {
++ vdd_cpu_big_s0: dcdc-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-enable-ramp-delay = <400>;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-name = "vdd_cpu_big_s0";
++ regulator-ramp-delay = <12500>;
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_npu_s0: dcdc-reg2 {
++ regulator-boot-on;
++ regulator-enable-ramp-delay = <400>;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-name = "vdd_npu_s0";
++ regulator-ramp-delay = <12500>;
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_lit_s0: dcdc-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-name = "vdd_cpu_lit_s0";
++ regulator-ramp-delay = <12500>;
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vcc_3v3_s3: dcdc-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_s3";
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vdd_gpu_s0: dcdc-reg5 {
++ regulator-boot-on;
++ regulator-enable-ramp-delay = <400>;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <900000>;
++ regulator-name = "vdd_gpu_s0";
++ regulator-ramp-delay = <12500>;
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ vddq_ddr_s0: dcdc-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vddq_ddr_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_logic_s0: dcdc-reg7 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <800000>;
++ regulator-name = "vdd_logic_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8_s3: dcdc-reg8 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s3";
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd2_ddr_s3: dcdc-reg9 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vdd2_ddr_s3";
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vdd_ddr_s0: dcdc-reg10 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-name = "vdd_ddr_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca_1v8_s0: pldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcca_1v8_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca1v8_pldo2_s0: pldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcca1v8_pldo2_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_1v2_s0: pldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-name = "vdda_1v2_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca_3v3_s0: pldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcca_3v3_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vccio_sd_s0: pldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vccio_sd_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca1v8_pldo6_s3: pldo-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcca1v8_pldo6_s3";
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_0v75_s3: nldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdd_0v75_s3";
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdda_ddr_pll_s0: nldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "vdda_ddr_pll_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda0v75_hdmi_s0: nldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <837500>;
++ regulator-max-microvolt = <837500>;
++ regulator-name = "vdda0v75_hdmi_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_0v85_s0: nldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "vdda_0v85_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_0v75_s0: nldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdda_0v75_s0";
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++&i2c2 {
++ status = "okay";
++
++ hym8563: rtc@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ #clock-cells = <0>;
++ clock-output-names = "hym8563";
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hym8563_int>;
++ wakeup-source;
++ };
++};
++
++&mdio0 {
++ rgmii_phy0: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0x1>;
++ clocks = <&cru REFCLKO25M_GMAC0_OUT>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtl8211f_rst>;
++ reset-assert-us = <20000>;
++ reset-deassert-us = <100000>;
++ reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
++ };
++};
++
++&pinctrl {
++ hym8563 {
++ hym8563_int: hym8563-int {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ leds {
++ led_rgb_g: led-green-en {
++ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ led_rgb_r: led-red-en {
++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ rtl8211f {
++ rtl8211f_rst: rtl8211f-rst {
++ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie {
++ pcie_pwren: pcie-pwren {
++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ usb {
++ usb_host_pwren: usb-host-pwren {
++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ max-frequency = <200000000>;
++ no-sdio;
++ no-mmc;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3_s3>;
++ vqmmc-supply = <&vccio_sd_s0>;
++ status = "okay";
++};
++
++&u2phy0 {
++ status = "okay";
++};
++
++&u2phy1 {
++ status = "okay";
++};
++
++&uart0 {
++ pinctrl-0 = <&uart0m0_xfer>;
++ status = "okay";
++};
++
++&usb_drd1_dwc3 {
++ dr_mode = "host";
++ status = "okay";
++};
--- /dev/null
+From 4e4f54aaec204a27d51386a9dd0d3a805fea57f4 Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Thu, 6 Mar 2025 13:06:31 -0500
+Subject: [PATCH] arm64: dts: rockchip: Add HDMI support for rock-4d
+
+Enable HDMI and VOP nodes for the rock-4d board.
+
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+Link: https://lore.kernel.org/r/20250306180737.127726-1-detlev.casanova@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3576-rock-4d.dts | 46 +++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+@@ -26,6 +26,17 @@
+ stdout-path = "serial0:1500000n8";
+ };
+
++ hdmi-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
+ leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+@@ -238,6 +249,26 @@
+ status = "okay";
+ };
+
++&hdmi {
++ status = "okay";
++};
++
++&hdmi_in {
++ hdmi_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi>;
++ };
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
++&hdptxphy {
++ status = "okay";
++};
++
+ &i2c1 {
+ status = "okay";
+
+@@ -687,3 +718,18 @@
+ dr_mode = "host";
+ status = "okay";
+ };
++
++&vop {
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi_in_vp0>;
++ };
++};
--- /dev/null
+From ba82f56bbf20e4166c988621cd0507509872848e Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Fri, 28 Feb 2025 09:50:48 -0500
+Subject: [PATCH] arm64: dts: rockchip: Add SPI NOR device on the ROCK 4D
+
+The SPI NOR chip is connected on the FSPI0 core, so enable the sfc0 node
+and add the flash device to it.
+
+The SPI NOR won't work at higher speed than 50 MHz, specify the limit.
+
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+Link: https://lore.kernel.org/r/20250228145304.581349-3-detlev.casanova@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+@@ -701,6 +701,22 @@
+ status = "okay";
+ };
+
++
++&sfc0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&fspi0_pins &fspi0_csn0>;
++ status = "okay";
++
++ flash@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <50000000>;
++ spi-rx-bus-width = <4>;
++ spi-tx-bus-width = <1>;
++ vcc-supply = <&vcc_1v8_s3>;
++ };
++};
++
+ &u2phy0 {
+ status = "okay";
+ };
--- /dev/null
+From 29ff4bbff793334d6aff2238fdc3ccf3859d60da Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Sat, 21 Jun 2025 16:37:55 +0200
+Subject: [PATCH] arm64: dts: rockchip: enable PCIe on ROCK 4D
+
+The RADXA ROCK 4D board has a PCIe controller connected to a flat flex
+connector, compatible with the one the RPi5 uses.
+
+Enable the associated combphy and pcie controller node, as well as add
+the remaining pinctrl definition for the reset.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250621-rk3576-rock4d-pcie-v1-1-2b33c9f12955@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+@@ -194,6 +194,10 @@
+ };
+ };
+
++&combphy0_ps {
++ status = "okay";
++};
++
+ &combphy1_psu {
+ status = "okay";
+ };
+@@ -652,6 +656,14 @@
+ };
+ };
+
++&pcie0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie_reset>;
++ reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3_pcie>;
++ status = "okay";
++};
++
+ &pinctrl {
+ hym8563 {
+ hym8563_int: hym8563-int {
+@@ -678,6 +690,9 @@
+ pcie_pwren: pcie-pwren {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
++ pcie_reset: pcie-reset {
++ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
+ };
+
+ usb {
--- /dev/null
+From 00abee2b18342d6c2f6f37225682fa7ca0d33142 Mon Sep 17 00:00:00 2001
+From: Detlev Casanova <detlev.casanova@collabora.com>
+Date: Tue, 8 Jul 2025 11:50:10 -0400
+Subject: [PATCH] arm64: dts: rockchip: Add UFS support on the ROCK 4D
+
+This device supports removable UFS chips, add support for it.
+
+Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
+Link: https://lore.kernel.org/r/20250708155010.401446-1-detlev.casanova@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+@@ -745,6 +745,10 @@
+ status = "okay";
+ };
+
++&ufshc {
++ status = "okay";
++};
++
+ &usb_drd1_dwc3 {
+ dr_mode = "host";
+ status = "okay";
--- /dev/null
+From cd803da7c033e376a66793a43ee98e136bc6cc25 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Fri, 4 Jul 2025 19:31:59 +0200
+Subject: [PATCH] arm64: dts: rockchip: fix PHY handling for ROCK 4D
+
+Old revisions of the ROCK 4D board have a dedicated crystal to
+supply the RTL8211F PHY's 25MHz clock input. At least some newer
+revisions instead use REFCLKO25M_GMAC0_OUT. The DT already has
+this half-prepared, but there are some issues:
+
+1. The DT relies on auto-selecting the right PHY driver, which
+ requires that it works good enough to read the ID registers.
+ This does not work without the clock, which is handled by
+ the PHY driver. By updating the compatible to contain the
+ RTL8211F IDs, so that the operating system can choose the
+ right PHY driver without relying on a pre-powered PHY.
+
+2. Despite the name REFCLKO25M_GMAC0_OUT could also provide a
+ different frequency, so ensure it is explicitly set to 25
+ MHz as expected by the PHY.
+
+3. While at it switch from deprecated "enable-gpio" to standard
+ "enable-gpios".
+
+Fixes: a0fb7eca9c09 ("arm64: dts: rockchip: Add Radxa ROCK 4D device tree")
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20250704-rk3576-rock4d-phy-handling-fixes-v1-1-1d64130c4139@kernel.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+@@ -645,14 +645,16 @@
+
+ &mdio0 {
+ rgmii_phy0: ethernet-phy@1 {
+- compatible = "ethernet-phy-ieee802.3-c22";
++ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
+ clocks = <&cru REFCLKO25M_GMAC0_OUT>;
++ assigned-clocks = <&cru REFCLKO25M_GMAC0_OUT>;
++ assigned-clock-rates = <25000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtl8211f_rst>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+- reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
++ reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+ };
+ };
+
--- /dev/null
+From 9a625a284bfdb902f27f2949063731d189adda3c Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Mon, 30 Jun 2025 17:36:33 +0200
+Subject: [PATCH] arm64: dts: rockchip: adjust dcin regulator on ROCK 4D
+
+The ROCK 4D's actual DC input is 5V, and the schematic names it as being
+5V as well.
+
+Rename the regulator, and change the voltage it claims to be at.
+Furthermore, fix vcc_1v1_nldo_s3's vin-supply as coming from
+vcc_5v0_sys, and not the DCIN, as per the schematic. This makes no
+functional change; both regulators are always on, and one feeds into the
+other.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250630-rock4d-reg-usb-wifi-v1-1-1057f412d98c@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+@@ -57,13 +57,13 @@
+ };
+ };
+
+- vcc_12v0_dcin: regulator-vcc-12v0-dcin {
++ vcc_5v0_dcin: regulator-vcc-5v0-dcin {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+- regulator-min-microvolt = <12000000>;
+- regulator-max-microvolt = <12000000>;
+- regulator-name = "vcc_12v0_dcin";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc_5v0_dcin";
+ };
+
+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+@@ -166,7 +166,7 @@
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc_5v0_device";
+- vin-supply = <&vcc_12v0_dcin>;
++ vin-supply = <&vcc_5v0_sys>;
+ };
+
+ vcc_5v0_host: regulator-vcc-5v0-host {
+@@ -190,7 +190,7 @@
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc_5v0_sys";
+- vin-supply = <&vcc_12v0_dcin>;
++ vin-supply = <&vcc_5v0_dcin>;
+ };
+ };
+
--- /dev/null
+From 787595b423d855bfcbf724822fd1e663ad368d08 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Mon, 30 Jun 2025 17:36:34 +0200
+Subject: [PATCH] arm64: dts: rockchip: complete USB nodes on ROCK 4D
+
+The ROCK 4D uses both USB controllers, and both of which in host mode.
+However, it still names one of the supplies for them "OTG" in the
+schematic.
+
+Fix the "host" supply's input, and add the "otg" supply. Enable the
+remaining USB PHY nodes, and the first controller node as well.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250630-rock4d-reg-usb-wifi-v1-2-1057f412d98c@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3576-rock-4d.dts | 41 ++++++++++++++++++-
+ 1 file changed, 39 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+@@ -180,7 +180,21 @@
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc5v0_host";
+- vin-supply = <&vcc_5v0_device>;
++ vin-supply = <&vcc_5v0_sys>;
++ };
++
++ vcc_5v0_otg: regulator-vcc-5v0-otg {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_otg_pwren>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v0_otg";
++ vin-supply = <&vcc_5v0_sys>;
+ };
+
+ vcc_5v0_sys: regulator-vcc-5v0-sys {
+@@ -699,7 +713,11 @@
+
+ usb {
+ usb_host_pwren: usb-host-pwren {
+- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++ usb_otg_pwren: usb-otg-pwren {
++ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>;
++
+ };
+ };
+ };
+@@ -738,10 +756,20 @@
+ status = "okay";
+ };
+
++&u2phy0_otg {
++ phy-supply = <&vcc_5v0_otg>;
++ status = "okay";
++};
++
+ &u2phy1 {
+ status = "okay";
+ };
+
++&u2phy1_otg {
++ phy-supply = <&vcc_5v0_host>;
++ status = "okay";
++};
++
+ &uart0 {
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+@@ -751,6 +779,15 @@
+ status = "okay";
+ };
+
++&usbdp_phy {
++ status = "okay";
++};
++
++&usb_drd0_dwc3 {
++ dr_mode = "host";
++ status = "okay";
++};
++
+ &usb_drd1_dwc3 {
+ dr_mode = "host";
+ status = "okay";
--- /dev/null
+From eebf59470a76a38d0c43005a34483e1a52a33de0 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Mon, 30 Jun 2025 17:36:35 +0200
+Subject: [PATCH] arm64: dts: rockchip: theoretically enable Wi-Fi on ROCK 4D
+
+The production version of the ROCK 4D appears to sport a AICSEMI
+AIC8800D80 USB Wi-Fi + BT chipset. This chip does not yet have a
+mainline driver.
+
+Add the necessary rfkill node and wifi regulator node to at least make
+it show up in lsusb output. The regulator is set as always-on, as like 2
+hours deep into debugging why onboard_usb_dev.c wouldn't try enabling
+the regulator the device needs to actually show up and thus bind to
+onboard_usb_dev.c, I decided that it's not worth the effort.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250630-rock4d-reg-usb-wifi-v1-3-1057f412d98c@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3576-rock-4d.dts | 30 +++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+@@ -37,6 +37,14 @@
+ };
+ };
+
++ rfkill {
++ compatible = "rfkill-gpio";
++ pinctrl-names = "default";
++ pinctrl-0 = <&wifi_en_h>;
++ radio-type = "wlan";
++ shutdown-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
++ };
++
+ leds: leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+@@ -159,6 +167,19 @@
+ vin-supply = <&vcc_5v0_sys>;
+ };
+
++ vcc_3v3_wifi: regulator-vcc-3v3-wifi {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_wifi_pwr>;
++ regulator-always-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_wifi";
++ vin-supply = <&vcc_3v3_s3>;
++ };
++
+ vcc_5v0_device: regulator-vcc-5v0-device {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+@@ -720,6 +741,15 @@
+
+ };
+ };
++
++ wifi {
++ usb_wifi_pwr: usb-wifi-pwr {
++ rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++ wifi_en_h: wifi-en-h {
++ rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++ };
+ };
+
+ &sdmmc {
--- /dev/null
+From e6066edc9413191479b05596ba06c40908f44e22 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Date: Mon, 30 Jun 2025 12:19:27 +0200
+Subject: [PATCH] arm64: dts: rockchip: add HDMI audio on ROCK 4D
+
+Much like the Sige5, the ROCK 4D also has an HDMI port, so is capable of
+providing HDMI audio output as well.
+
+Enable the SoC's hdmi_sound card, and also enable the SoC audio
+controller (sai6) that feeds into it.
+
+Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Tested-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20250630-rock4d-audio-v1-4-0b3c8e8fda9c@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+@@ -304,6 +304,10 @@
+ };
+ };
+
++&hdmi_sound {
++ status = "okay";
++};
++
+ &hdptxphy {
+ status = "okay";
+ };
+@@ -752,6 +756,10 @@
+ };
+ };
+
++&sai6 {
++ status = "okay";
++};
++
+ &sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
--- /dev/null
+From 7fee88882704a5ed7657f467ecb44e39b20f42aa Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 27 Sep 2025 17:23:10 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add devicetree for the FriendlyElec
+ NanoPi R76S
+
+The NanoPi R76S (as "R76S") is an open-sourced mini IoT gateway
+device with two 2.5G, designed and developed by FriendlyElec.
+
+Specification:
+- Rockchip RK3576
+- 2/4GB LPDDR4X RAM
+- 2x 2500Base-T (PCIe, rtl8125b)
+- 3x LEDs (Power, LAN, WAN)
+- 32GB eMMC
+- MicroSD Slot
+- MDMI 1.4/2.0 OUT
+- M.2 E-Key SDIO slot
+- USB 3.0 Port
+- USB Type-C 5V Power
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts | 860 +++++++++++++++++++++
+ 2 files changed, 861 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-display-vz.dtbo
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-wolfvision-pf5-io-expander.dtbo
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-rock-4d.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3582-radxa-e52c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-armsom-sige7.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
+@@ -0,0 +1,860 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2025 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyelec.com)
++ *
++ * Copyright (c) 2025 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++
++#include "rk3576.dtsi"
++
++/ {
++ model = "FriendlyElec NanoPi R76S";
++ compatible = "friendlyarm,nanopi-r76s", "rockchip,rk3576";
++
++ aliases {
++ mmc0 = &sdhci;
++ mmc1 = &sdmmc;
++ mmc2 = &sdio;
++ };
++
++ chosen {
++ stdout-path = "serial0:1500000n8";
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&user_but_pin>;
++
++ button-reset {
++ label = "reset";
++ gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
++ debounce-interval = <50>;
++ linux,code = <KEY_RESTART>;
++ wakeup-source;
++ };
++ };
++
++ gpio-leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&led1_h>, <&led_sys_h>, <&led2_h>;
++
++ led-0 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_LAN;
++ gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
++ };
++
++ led-1 {
++ color = <LED_COLOR_ID_RED>;
++ function = LED_FUNCTION_POWER;
++ gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++
++ led-2 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_WAN;
++ gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ hdmi-con {
++ compatible = "hdmi-connector";
++ hdmi-pwr-supply = <&vcc5v_hdmi_tx>;
++ type = "a";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
++ sdio_pwrseq: sdio-pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ clocks = <&hym8563>;
++ clock-names = "ext_clock";
++ pinctrl-names = "default";
++ pinctrl-0 = <&wifi_reg_on_h>;
++ post-power-on-delay-ms = <200>;
++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++ };
++
++ vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc3v3_rtc_s5";
++ vin-supply = <&vcc5v0_sys_s5>;
++ };
++
++ vcc5v_dcin: regulator-vcc5v-dcin {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v_dcin";
++ };
++
++ vcc5v_hdmi_tx: regulator-vcc5v-hdmi-tx {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&hdmi_tx_on_h>;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v_hdmi_tx";
++ vin-supply = <&vcc5v0_sys_s5>;
++ };
++
++ vcc5v0_device_s0: regulator-vcc5v0-device-s0 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v0_device_s0";
++ vin-supply = <&vcc5v_dcin>;
++ };
++
++ vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v0_sys_s5";
++ vin-supply = <&vcc5v_dcin>;
++ };
++
++ vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_otg0_pwren_h>;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc5v0_usb_otg0";
++ vin-supply = <&vcc5v0_sys_s5>;
++ };
++
++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
++ regulator-name = "vcc_1v1_nldo_s3";
++ vin-supply = <&vcc5v0_sys_s5>;
++ };
++
++ vcc_1v8_s0: regulator-vcc-1v8-s0 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s0";
++ vin-supply = <&vcc_1v8_s3>;
++ };
++
++ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <2000000>;
++ regulator-max-microvolt = <2000000>;
++ regulator-name = "vcc_2v0_pldo_s3";
++ vin-supply = <&vcc5v0_sys_s5>;
++ };
++
++ vcc_3v3_s0: regulator-vcc-3v3-s0 {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_s0";
++ vin-supply = <&vcc_3v3_s3>;
++ };
++};
++
++&combphy0_ps {
++ status = "okay";
++};
++
++&combphy1_psu {
++ status = "okay";
++};
++
++&cpu_b0 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_b1 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_b2 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_b3 {
++ cpu-supply = <&vdd_cpu_big_s0>;
++};
++
++&cpu_l0 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l1 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l2 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l3 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&gpu {
++ mali-supply = <&vdd_gpu_s0>;
++ status = "okay";
++};
++
++&hdmi {
++ status = "okay";
++};
++
++&hdmi_in {
++ hdmi_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi>;
++ };
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
++&hdmi_sound {
++ status = "okay";
++};
++
++&hdptxphy {
++ status = "okay";
++};
++
++&i2c1 {
++ status = "okay";
++
++ pmic@23 {
++ compatible = "rockchip,rk806";
++ reg = <0x23>;
++ #gpio-cells = <2>;
++ gpio-controller;
++ interrupt-parent = <&gpio0>;
++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
++ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
++ system-power-controller;
++
++ vcc1-supply = <&vcc5v0_sys_s5>;
++ vcc2-supply = <&vcc5v0_sys_s5>;
++ vcc3-supply = <&vcc5v0_sys_s5>;
++ vcc4-supply = <&vcc5v0_sys_s5>;
++ vcc5-supply = <&vcc5v0_sys_s5>;
++ vcc6-supply = <&vcc5v0_sys_s5>;
++ vcc7-supply = <&vcc5v0_sys_s5>;
++ vcc8-supply = <&vcc5v0_sys_s5>;
++ vcc9-supply = <&vcc5v0_sys_s5>;
++ vcc10-supply = <&vcc5v0_sys_s5>;
++ vcc11-supply = <&vcc_2v0_pldo_s3>;
++ vcc12-supply = <&vcc5v0_sys_s5>;
++ vcc13-supply = <&vcc_1v1_nldo_s3>;
++ vcc14-supply = <&vcc_1v1_nldo_s3>;
++ vcca-supply = <&vcc5v0_sys_s5>;
++
++ rk806_dvs1_null: dvs1-null-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun2";
++ };
++
++ rk806_dvs1_rst: dvs1-rst-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun3";
++ };
++
++ rk806_dvs1_slp: dvs1-slp-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun1";
++ };
++
++ rk806_dvs2_dvs: dvs2-dvs-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun4";
++ };
++
++ rk806_dvs2_gpio: dvs2-gpio-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun5";
++ };
++
++ rk806_dvs2_null: dvs2-null-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun2";
++ };
++
++ rk806_dvs2_rst: dvs2-rst-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun3";
++ };
++
++ rk806_dvs2_slp: dvs2-slp-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun1";
++ };
++
++ rk806_dvs3_dvs: dvs3-dvs-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun4";
++ };
++
++ rk806_dvs3_gpio: dvs3-gpio-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun5";
++ };
++
++ rk806_dvs3_null: dvs3-null-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun2";
++ };
++
++ rk806_dvs3_rst: dvs3-rst-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun3";
++ };
++
++ rk806_dvs3_slp: dvs3-slp-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun1";
++ };
++
++ regulators {
++ vdd_cpu_big_s0: dcdc-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-enable-ramp-delay = <400>;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-name = "vdd_cpu_big_s0";
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_npu_s0: dcdc-reg2 {
++ regulator-boot-on;
++ regulator-enable-ramp-delay = <400>;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-name = "vdd_npu_s0";
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_lit_s0: dcdc-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-name = "vdd_cpu_lit_s0";
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vcc_3v3_s3: dcdc-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vdd_gpu_s0: dcdc-reg5 {
++ regulator-boot-on;
++ regulator-enable-ramp-delay = <400>;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <900000>;
++ regulator-name = "vdd_gpu_s0";
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ vddq_ddr_s0: dcdc-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vddq_ddr_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_logic_s0: dcdc-reg7 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <800000>;
++ regulator-name = "vdd_logic_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8_s3: dcdc-reg8 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd2_ddr_s3: dcdc-reg9 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vdd2_ddr_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vdd_ddr_s0: dcdc-reg10 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-name = "vdd_ddr_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca_1v8_s0: pldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcca_1v8_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca1v8_pldo2_s0: pldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcca1v8_pldo2_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_1v2_s0: pldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-name = "vdda_1v2_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca_3v3_s0: pldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcca_3v3_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vccio_sd_s0: pldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vccio_sd_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca1v8_pldo6_s3: pldo-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcca1v8_pldo6_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_0v75_s3: nldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdd_0v75_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdda_ddr_pll_s0: nldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "vdda_ddr_pll_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda0v75_hdmi_s0: nldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <837500>;
++ regulator-max-microvolt = <837500>;
++ regulator-name = "vdda0v75_hdmi_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_0v85_s0: nldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "vdda_0v85_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_0v75_s0: nldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdda_0v75_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++&i2c2 {
++ status = "okay";
++
++ hym8563: rtc@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ #clock-cells = <0>;
++ clock-output-names = "hym8563";
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PA5 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtc_int_l>;
++ wakeup-source;
++ };
++};
++
++&pcie0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie0_perstn>;
++ reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3_s3>;
++ status = "okay";
++};
++
++&pcie1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie1_perstn>;
++ reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3_s3>;
++ status = "okay";
++};
++
++&pinctrl {
++ bt {
++ bt_reg_on_h: bt-reg-on-h {
++ rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++
++ bt_wake_host_h: bt-wake-host-h {
++ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++
++ host_wake_bt_h: host-wake-bt-h {
++ rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ gpio-keys {
++ user_but_pin: user-but-pin {
++ rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ gpio-leds {
++ led_sys_h: led-sys-h {
++ rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ led1_h: led1-h {
++ rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ led2_h: led2-h {
++ rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ hdmi {
++ hdmi_tx_on_h: hdmi-tx-on-h {
++ rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ hym8563 {
++ rtc_int_l: rtc-int-l {
++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ pcie {
++ pcie0_perstn: pcie0-perstn {
++ rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++
++ pcie1_perstn: pcie1-perstn {
++ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ usb {
++ usb_otg0_pwren_h: usb-otg0-pwren-h {
++ rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ wifi {
++ wifi_wake_host_h: wifi-wake-host-h {
++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++
++ wifi_reg_on_h: wifi-reg-on-h {
++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&sai6 {
++ status = "okay";
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ no-mmc;
++ no-sdio;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3_s3>;
++ vqmmc-supply = <&vccio_sd_s0>;
++ status = "okay";
++};
++
++&sdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ bus-width = <4>;
++ cap-sd-highspeed;
++ cap-sdio-irq;
++ disable-wp;
++ keep-power-in-suspend;
++ mmc-pwrseq = <&sdio_pwrseq>;
++ no-mmc;
++ no-sd;
++ non-removable;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3_s3>;
++ vqmmc-supply = <&vcc_1v8_s3>;
++ wakeup-source;
++ status = "okay";
++
++ rtl8822cs: wifi@1 {
++ reg = <1>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "host-wake";
++ pinctrl-names = "default";
++ pinctrl-0 = <&wifi_wake_host_h>;
++ };
++};
++
++&sdhci {
++ bus-width = <8>;
++ cap-mmc-highspeed;
++ full-pwr-cycle-in-suspend;
++ mmc-hs400-1_8v;
++ mmc-hs400-enhanced-strobe;
++ no-sdio;
++ no-sd;
++ non-removable;
++ status = "okay";
++};
++
++&saradc {
++ vref-supply = <&vcca_1v8_s0>;
++ status = "okay";
++};
++
++&u2phy0 {
++ status = "okay";
++};
++
++&u2phy0_otg {
++ phy-supply = <&vcc5v0_usb_otg0>;
++ status = "okay";
++};
++
++&uart0 {
++ status = "okay";
++};
++
++&uart5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart5m0_xfer &uart5m0_ctsn &uart5m0_rtsn>;
++ uart-has-rtscts;
++ status = "okay";
++
++ bluetooth {
++ compatible = "realtek,rtl8822cs-bt";
++ enable-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
++ device-wake-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>;
++ host-wake-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&bt_wake_host_h &host_wake_bt_h &bt_reg_on_h>;
++ };
++};
++
++&usbdp_phy {
++ status = "okay";
++};
++
++&usb_drd0_dwc3 {
++ dr_mode = "host";
++ extcon = <&u2phy0>;
++ status = "okay";
++};
++
++&vop {
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi_in_vp0>;
++ };
++};
--- /dev/null
+From 7983e6c379a917c500eff31f5f9c646cc408e030 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Thu, 29 Aug 2024 09:27:04 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add base DT for rk3528 SoC
+
+This initial device tree describes CPU, interrupts and UART on the chip
+and is able to boot into basic kernel with only UART. Cache information
+is omitted for now as there is no precise documentation. Support for
+other features will be added later.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20240829092705.6241-4-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 189 +++++++++++++++++++++++
+ 1 file changed, 189 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3528.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -0,0 +1,189 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
++ */
++
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++
++/ {
++ compatible = "rockchip,rk3528";
++
++ interrupt-parent = <&gic>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ aliases {
++ serial0 = &uart0;
++ serial1 = &uart1;
++ serial2 = &uart2;
++ serial3 = &uart3;
++ serial4 = &uart4;
++ serial5 = &uart5;
++ serial6 = &uart6;
++ serial7 = &uart7;
++ };
++
++ cpus {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ cpu-map {
++ cluster0 {
++ core0 {
++ cpu = <&cpu0>;
++ };
++ core1 {
++ cpu = <&cpu1>;
++ };
++ core2 {
++ cpu = <&cpu2>;
++ };
++ core3 {
++ cpu = <&cpu3>;
++ };
++ };
++ };
++
++ cpu0: cpu@0 {
++ compatible = "arm,cortex-a53";
++ reg = <0x0>;
++ device_type = "cpu";
++ enable-method = "psci";
++ };
++
++ cpu1: cpu@1 {
++ compatible = "arm,cortex-a53";
++ reg = <0x1>;
++ device_type = "cpu";
++ enable-method = "psci";
++ };
++
++ cpu2: cpu@2 {
++ compatible = "arm,cortex-a53";
++ reg = <0x2>;
++ device_type = "cpu";
++ enable-method = "psci";
++ };
++
++ cpu3: cpu@3 {
++ compatible = "arm,cortex-a53";
++ reg = <0x3>;
++ device_type = "cpu";
++ enable-method = "psci";
++ };
++ };
++
++ psci {
++ compatible = "arm,psci-1.0", "arm,psci-0.2";
++ method = "smc";
++ };
++
++ timer {
++ compatible = "arm,armv8-timer";
++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
++ };
++
++ xin24m: clock-xin24m {
++ compatible = "fixed-clock";
++ clock-frequency = <24000000>;
++ clock-output-names = "xin24m";
++ #clock-cells = <0>;
++ };
++
++ soc {
++ compatible = "simple-bus";
++ ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ gic: interrupt-controller@fed01000 {
++ compatible = "arm,gic-400";
++ reg = <0x0 0xfed01000 0 0x1000>,
++ <0x0 0xfed02000 0 0x2000>,
++ <0x0 0xfed04000 0 0x2000>,
++ <0x0 0xfed06000 0 0x2000>;
++ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
++ IRQ_TYPE_LEVEL_LOW)>;
++ interrupt-controller;
++ #address-cells = <0>;
++ #interrupt-cells = <3>;
++ };
++
++ uart0: serial@ff9f0000 {
++ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
++ reg = <0x0 0xff9f0000 0x0 0x100>;
++ clock-frequency = <24000000>;
++ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
++ uart1: serial@ff9f8000 {
++ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
++ reg = <0x0 0xff9f8000 0x0 0x100>;
++ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
++ uart2: serial@ffa00000 {
++ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
++ reg = <0x0 0xffa00000 0x0 0x100>;
++ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
++ uart3: serial@ffa08000 {
++ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
++ reg = <0x0 0xffa08000 0x0 0x100>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
++ uart4: serial@ffa10000 {
++ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
++ reg = <0x0 0xffa10000 0x0 0x100>;
++ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
++ uart5: serial@ffa18000 {
++ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
++ reg = <0x0 0xffa18000 0x0 0x100>;
++ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
++ uart6: serial@ffa20000 {
++ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
++ reg = <0x0 0xffa20000 0x0 0x100>;
++ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++
++ uart7: serial@ffa28000 {
++ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
++ reg = <0x0 0xffa28000 0x0 0x100>;
++ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
++ reg-io-width = <4>;
++ reg-shift = <2>;
++ status = "disabled";
++ };
++ };
++};
--- /dev/null
+From 858cdcdd11cf9913756297d3869e4de0f01329ea Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Mon, 17 Feb 2025 06:11:45 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add clock generators for RK3528 SoC
+
+Add dt node for RK3528 clock and reset unit. Clock "gmac0_clk" is
+generated by internal Ethernet phy, a fixed clock node is added as a
+placeholder to avoid orphans.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20250217061142.38480-9-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 51 ++++++++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -6,6 +6,7 @@
+
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/clock/rockchip,rk3528-cru.h>
+
+ / {
+ compatible = "rockchip,rk3528";
+@@ -95,6 +96,13 @@
+ #clock-cells = <0>;
+ };
+
++ gmac0_clk: clock-gmac50m {
++ compatible = "fixed-clock";
++ clock-frequency = <50000000>;
++ clock-output-names = "gmac0";
++ #clock-cells = <0>;
++ };
++
+ soc {
+ compatible = "simple-bus";
+ ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
+@@ -114,6 +122,49 @@
+ #interrupt-cells = <3>;
+ };
+
++ cru: clock-controller@ff4a0000 {
++ compatible = "rockchip,rk3528-cru";
++ reg = <0x0 0xff4a0000 0x0 0x30000>;
++ assigned-clocks =
++ <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>,
++ <&cru PLL_PPLL>, <&cru PLL_CPLL>,
++ <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>,
++ <&cru CLK_MATRIX_500M_SRC>,
++ <&cru CLK_MATRIX_50M_SRC>,
++ <&cru CLK_MATRIX_100M_SRC>,
++ <&cru CLK_MATRIX_150M_SRC>,
++ <&cru CLK_MATRIX_200M_SRC>,
++ <&cru CLK_MATRIX_300M_SRC>,
++ <&cru CLK_MATRIX_339M_SRC>,
++ <&cru CLK_MATRIX_400M_SRC>,
++ <&cru CLK_MATRIX_600M_SRC>,
++ <&cru CLK_PPLL_50M_MATRIX>,
++ <&cru CLK_PPLL_100M_MATRIX>,
++ <&cru CLK_PPLL_125M_MATRIX>,
++ <&cru ACLK_BUS_VOPGL_ROOT>;
++ assigned-clock-rates =
++ <32768>, <1188000000>,
++ <1000000000>, <996000000>,
++ <408000000>, <250000000>,
++ <500000000>,
++ <50000000>,
++ <100000000>,
++ <150000000>,
++ <200000000>,
++ <300000000>,
++ <340000000>,
++ <400000000>,
++ <600000000>,
++ <50000000>,
++ <100000000>,
++ <125000000>,
++ <500000000>;
++ clocks = <&xin24m>, <&gmac0_clk>;
++ clock-names = "xin24m", "gmac0";
++ #clock-cells = <1>;
++ #reset-cells = <1>;
++ };
++
+ uart0: serial@ff9f0000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff9f0000 0x0 0x100>;
--- /dev/null
+From b9454434d0349223418f74fbfa7b902104da9bc5 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Mon, 17 Feb 2025 06:11:46 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add UART clocks for RK3528 SoC
+
+Add missing clocks in UART nodes for RK3528 SoC.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20250217061142.38480-10-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -168,7 +168,8 @@
+ uart0: serial@ff9f0000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff9f0000 0x0 0x100>;
+- clock-frequency = <24000000>;
++ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
++ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+@@ -178,6 +179,8 @@
+ uart1: serial@ff9f8000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff9f8000 0x0 0x100>;
++ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
++ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+@@ -187,6 +190,8 @@
+ uart2: serial@ffa00000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa00000 0x0 0x100>;
++ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
++ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+@@ -195,6 +200,8 @@
+
+ uart3: serial@ffa08000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
++ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
++ clock-names = "baudclk", "apb_pclk";
+ reg = <0x0 0xffa08000 0x0 0x100>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+@@ -204,6 +211,8 @@
+ uart4: serial@ffa10000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa10000 0x0 0x100>;
++ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
++ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+@@ -213,6 +222,8 @@
+ uart5: serial@ffa18000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa18000 0x0 0x100>;
++ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
++ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+@@ -222,6 +233,8 @@
+ uart6: serial@ffa20000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa20000 0x0 0x100>;
++ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
++ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+@@ -231,6 +244,8 @@
+ uart7: serial@ffa28000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa28000 0x0 0x100>;
++ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
++ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
--- /dev/null
+From a31fad19ae39ea27b5068e3b02bcbf30a905339b Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Fri, 28 Feb 2025 06:40:10 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528
+
+Add pinctrl and gpio nodes for RK3528 and import rk3528-pinctrl.dtsi
+from vendor linux-6.1-stan-rkr5 kernel with the hdmi-pins-idle node
+removed due to missing label reference to pcfg_output_low_pull_down.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250228064024.3200000-5-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3528-pinctrl.dtsi | 1397 +++++++++++++++++
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 82 +
+ 2 files changed, 1479 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
+@@ -0,0 +1,1397 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
++ */
++
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rockchip-pinconf.dtsi"
++
++/*
++ * This file is auto generated by pin2dts tool, please keep these code
++ * by adding changes at end of this file.
++ */
++&pinctrl {
++ arm {
++ /omit-if-no-ref/
++ arm_pins: arm-pins {
++ rockchip,pins =
++ /* arm_avs */
++ <4 RK_PC4 3 &pcfg_pull_none>;
++ };
++ };
++
++ clk {
++ /omit-if-no-ref/
++ clkm0_32k_out: clkm0-32k-out {
++ rockchip,pins =
++ /* clkm0_32k_out */
++ <3 RK_PC3 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ clkm1_32k_out: clkm1-32k-out {
++ rockchip,pins =
++ /* clkm1_32k_out */
++ <1 RK_PC3 1 &pcfg_pull_none>;
++ };
++ };
++
++ emmc {
++ /omit-if-no-ref/
++ emmc_rstnout: emmc-rstnout {
++ rockchip,pins =
++ /* emmc_rstn */
++ <1 RK_PD6 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ emmc_bus8: emmc-bus8 {
++ rockchip,pins =
++ /* emmc_d0 */
++ <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d1 */
++ <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d2 */
++ <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d3 */
++ <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d4 */
++ <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d5 */
++ <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d6 */
++ <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
++ /* emmc_d7 */
++ <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ emmc_clk: emmc-clk {
++ rockchip,pins =
++ /* emmc_clk */
++ <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ emmc_cmd: emmc-cmd {
++ rockchip,pins =
++ /* emmc_cmd */
++ <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ emmc_strb: emmc-strb {
++ rockchip,pins =
++ /* emmc_strb */
++ <1 RK_PD7 1 &pcfg_pull_none>;
++ };
++ };
++
++ eth {
++ /omit-if-no-ref/
++ eth_pins: eth-pins {
++ rockchip,pins =
++ /* eth_clk_25m_out */
++ <3 RK_PB5 2 &pcfg_pull_none_drv_level_2>;
++ };
++ };
++
++ fephy {
++ /omit-if-no-ref/
++ fephym0_led_dpx: fephym0-led_dpx {
++ rockchip,pins =
++ /* fephy_led_dpx_m0 */
++ <4 RK_PB5 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ fephym0_led_link: fephym0-led_link {
++ rockchip,pins =
++ /* fephy_led_link_m0 */
++ <4 RK_PC0 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ fephym0_led_spd: fephym0-led_spd {
++ rockchip,pins =
++ /* fephy_led_spd_m0 */
++ <4 RK_PB7 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ fephym1_led_dpx: fephym1-led_dpx {
++ rockchip,pins =
++ /* fephy_led_dpx_m1 */
++ <2 RK_PA4 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ fephym1_led_link: fephym1-led_link {
++ rockchip,pins =
++ /* fephy_led_link_m1 */
++ <2 RK_PA6 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ fephym1_led_spd: fephym1-led_spd {
++ rockchip,pins =
++ /* fephy_led_spd_m1 */
++ <2 RK_PA5 5 &pcfg_pull_none>;
++ };
++ };
++
++ fspi {
++ /omit-if-no-ref/
++ fspi_pins: fspi-pins {
++ rockchip,pins =
++ /* fspi_clk */
++ <1 RK_PD5 2 &pcfg_pull_none>,
++ /* fspi_d0 */
++ <1 RK_PC4 2 &pcfg_pull_none>,
++ /* fspi_d1 */
++ <1 RK_PC5 2 &pcfg_pull_none>,
++ /* fspi_d2 */
++ <1 RK_PC6 2 &pcfg_pull_none>,
++ /* fspi_d3 */
++ <1 RK_PC7 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ fspi_csn0: fspi-csn0 {
++ rockchip,pins =
++ /* fspi_csn0 */
++ <1 RK_PD0 2 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ fspi_csn1: fspi-csn1 {
++ rockchip,pins =
++ /* fspi_csn1 */
++ <1 RK_PD1 2 &pcfg_pull_none>;
++ };
++ };
++
++ gpu {
++ /omit-if-no-ref/
++ gpu_pins: gpu-pins {
++ rockchip,pins =
++ /* gpu_avs */
++ <4 RK_PC3 3 &pcfg_pull_none>;
++ };
++ };
++
++ hdmi {
++ /omit-if-no-ref/
++ hdmi_pins: hdmi-pins {
++ rockchip,pins =
++ /* hdmi_tx_cec */
++ <0 RK_PA3 1 &pcfg_pull_none>,
++ /* hdmi_tx_hpd */
++ <0 RK_PA2 1 &pcfg_pull_none>,
++ /* hdmi_tx_scl */
++ <0 RK_PA4 1 &pcfg_pull_none>,
++ /* hdmi_tx_sda */
++ <0 RK_PA5 1 &pcfg_pull_none>;
++ };
++ };
++
++ hsm {
++ /omit-if-no-ref/
++ hsmm0_pins: hsmm0-pins {
++ rockchip,pins =
++ /* hsm_clk_out_m0 */
++ <2 RK_PA2 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ hsmm1_pins: hsmm1-pins {
++ rockchip,pins =
++ /* hsm_clk_out_m1 */
++ <1 RK_PA4 3 &pcfg_pull_none>;
++ };
++ };
++
++ i2c0 {
++ /omit-if-no-ref/
++ i2c0m0_xfer: i2c0m0-xfer {
++ rockchip,pins =
++ /* i2c0_scl_m0 */
++ <4 RK_PC4 2 &pcfg_pull_none_smt>,
++ /* i2c0_sda_m0 */
++ <4 RK_PC3 2 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c0m1_xfer: i2c0m1-xfer {
++ rockchip,pins =
++ /* i2c0_scl_m1 */
++ <4 RK_PA1 2 &pcfg_pull_none_smt>,
++ /* i2c0_sda_m1 */
++ <4 RK_PA0 2 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c1 {
++ /omit-if-no-ref/
++ i2c1m0_xfer: i2c1m0-xfer {
++ rockchip,pins =
++ /* i2c1_scl_m0 */
++ <4 RK_PA3 2 &pcfg_pull_none_smt>,
++ /* i2c1_sda_m0 */
++ <4 RK_PA2 2 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c1m1_xfer: i2c1m1-xfer {
++ rockchip,pins =
++ /* i2c1_scl_m1 */
++ <4 RK_PC5 4 &pcfg_pull_none_smt>,
++ /* i2c1_sda_m1 */
++ <4 RK_PC6 4 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c2 {
++ /omit-if-no-ref/
++ i2c2m0_xfer: i2c2m0-xfer {
++ rockchip,pins =
++ /* i2c2_scl_m0 */
++ <0 RK_PA4 2 &pcfg_pull_none_smt>,
++ /* i2c2_sda_m0 */
++ <0 RK_PA5 2 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c2m1_xfer: i2c2m1-xfer {
++ rockchip,pins =
++ /* i2c2_scl_m1 */
++ <1 RK_PA5 3 &pcfg_pull_none_smt>,
++ /* i2c2_sda_m1 */
++ <1 RK_PA6 3 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c3 {
++ /omit-if-no-ref/
++ i2c3m0_xfer: i2c3m0-xfer {
++ rockchip,pins =
++ /* i2c3_scl_m0 */
++ <1 RK_PA0 2 &pcfg_pull_none_smt>,
++ /* i2c3_sda_m0 */
++ <1 RK_PA1 2 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c3m1_xfer: i2c3m1-xfer {
++ rockchip,pins =
++ /* i2c3_scl_m1 */
++ <3 RK_PC1 5 &pcfg_pull_none_smt>,
++ /* i2c3_sda_m1 */
++ <3 RK_PC3 5 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c4 {
++ /omit-if-no-ref/
++ i2c4_xfer: i2c4-xfer {
++ rockchip,pins =
++ /* i2c4_scl */
++ <2 RK_PA0 4 &pcfg_pull_none_smt>,
++ /* i2c4_sda */
++ <2 RK_PA1 4 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c5 {
++ /omit-if-no-ref/
++ i2c5m0_xfer: i2c5m0-xfer {
++ rockchip,pins =
++ /* i2c5_scl_m0 */
++ <1 RK_PB2 3 &pcfg_pull_none_smt>,
++ /* i2c5_sda_m0 */
++ <1 RK_PB3 3 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c5m1_xfer: i2c5m1-xfer {
++ rockchip,pins =
++ /* i2c5_scl_m1 */
++ <1 RK_PD2 3 &pcfg_pull_none_smt>,
++ /* i2c5_sda_m1 */
++ <1 RK_PD3 3 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c6 {
++ /omit-if-no-ref/
++ i2c6m0_xfer: i2c6m0-xfer {
++ rockchip,pins =
++ /* i2c6_scl_m0 */
++ <3 RK_PB2 5 &pcfg_pull_none_smt>,
++ /* i2c6_sda_m0 */
++ <3 RK_PB3 5 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2c6m1_xfer: i2c6m1-xfer {
++ rockchip,pins =
++ /* i2c6_scl_m1 */
++ <1 RK_PD4 3 &pcfg_pull_none_smt>,
++ /* i2c6_sda_m1 */
++ <1 RK_PD7 3 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2c7 {
++ /omit-if-no-ref/
++ i2c7_xfer: i2c7-xfer {
++ rockchip,pins =
++ /* i2c7_scl */
++ <2 RK_PA5 4 &pcfg_pull_none_smt>,
++ /* i2c7_sda */
++ <2 RK_PA6 4 &pcfg_pull_none_smt>;
++ };
++ };
++
++ i2s0 {
++ /omit-if-no-ref/
++ i2s0m0_lrck: i2s0m0-lrck {
++ rockchip,pins =
++ /* i2s0_lrck_m0 */
++ <3 RK_PB6 1 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2s0m0_mclk: i2s0m0-mclk {
++ rockchip,pins =
++ /* i2s0_mclk_m0 */
++ <3 RK_PB4 1 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2s0m0_sclk: i2s0m0-sclk {
++ rockchip,pins =
++ /* i2s0_sclk_m0 */
++ <3 RK_PB5 1 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2s0m0_sdi: i2s0m0-sdi {
++ rockchip,pins =
++ /* i2s0m0_sdi */
++ <3 RK_PB7 1 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ i2s0m0_sdo: i2s0m0-sdo {
++ rockchip,pins =
++ /* i2s0m0_sdo */
++ <3 RK_PC0 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ i2s0m1_lrck: i2s0m1-lrck {
++ rockchip,pins =
++ /* i2s0_lrck_m1 */
++ <1 RK_PB6 1 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2s0m1_mclk: i2s0m1-mclk {
++ rockchip,pins =
++ /* i2s0_mclk_m1 */
++ <1 RK_PB4 1 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2s0m1_sclk: i2s0m1-sclk {
++ rockchip,pins =
++ /* i2s0_sclk_m1 */
++ <1 RK_PB5 1 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2s0m1_sdi: i2s0m1-sdi {
++ rockchip,pins =
++ /* i2s0m1_sdi */
++ <1 RK_PB7 1 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ i2s0m1_sdo: i2s0m1-sdo {
++ rockchip,pins =
++ /* i2s0m1_sdo */
++ <1 RK_PC0 1 &pcfg_pull_none>;
++ };
++ };
++
++ i2s1 {
++ /omit-if-no-ref/
++ i2s1_lrck: i2s1-lrck {
++ rockchip,pins =
++ /* i2s1_lrck */
++ <4 RK_PA6 1 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2s1_mclk: i2s1-mclk {
++ rockchip,pins =
++ /* i2s1_mclk */
++ <4 RK_PA4 1 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2s1_sclk: i2s1-sclk {
++ rockchip,pins =
++ /* i2s1_sclk */
++ <4 RK_PA5 1 &pcfg_pull_none_smt>;
++ };
++
++ /omit-if-no-ref/
++ i2s1_sdi0: i2s1-sdi0 {
++ rockchip,pins =
++ /* i2s1_sdi0 */
++ <4 RK_PB4 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ i2s1_sdi1: i2s1-sdi1 {
++ rockchip,pins =
++ /* i2s1_sdi1 */
++ <4 RK_PB3 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ i2s1_sdi2: i2s1-sdi2 {
++ rockchip,pins =
++ /* i2s1_sdi2 */
++ <4 RK_PA3 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ i2s1_sdi3: i2s1-sdi3 {
++ rockchip,pins =
++ /* i2s1_sdi3 */
++ <4 RK_PA2 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ i2s1_sdo0: i2s1-sdo0 {
++ rockchip,pins =
++ /* i2s1_sdo0 */
++ <4 RK_PA7 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ i2s1_sdo1: i2s1-sdo1 {
++ rockchip,pins =
++ /* i2s1_sdo1 */
++ <4 RK_PB0 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ i2s1_sdo2: i2s1-sdo2 {
++ rockchip,pins =
++ /* i2s1_sdo2 */
++ <4 RK_PB1 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ i2s1_sdo3: i2s1-sdo3 {
++ rockchip,pins =
++ /* i2s1_sdo3 */
++ <4 RK_PB2 1 &pcfg_pull_none>;
++ };
++ };
++
++ jtag {
++ /omit-if-no-ref/
++ jtagm0_pins: jtagm0-pins {
++ rockchip,pins =
++ /* jtag_cpu_tck_m0 */
++ <2 RK_PA2 2 &pcfg_pull_none>,
++ /* jtag_cpu_tms_m0 */
++ <2 RK_PA3 2 &pcfg_pull_none>,
++ /* jtag_mcu_tck_m0 */
++ <2 RK_PA4 2 &pcfg_pull_none>,
++ /* jtag_mcu_tms_m0 */
++ <2 RK_PA5 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ jtagm1_pins: jtagm1-pins {
++ rockchip,pins =
++ /* jtag_cpu_tck_m1 */
++ <4 RK_PD0 2 &pcfg_pull_none>,
++ /* jtag_cpu_tms_m1 */
++ <4 RK_PC7 2 &pcfg_pull_none>,
++ /* jtag_mcu_tck_m1 */
++ <4 RK_PD0 3 &pcfg_pull_none>,
++ /* jtag_mcu_tms_m1 */
++ <4 RK_PC7 3 &pcfg_pull_none>;
++ };
++ };
++
++ pcie {
++ /omit-if-no-ref/
++ pciem0_pins: pciem0-pins {
++ rockchip,pins =
++ /* pcie_clkreqn_m0 */
++ <3 RK_PA6 5 &pcfg_pull_none>,
++ /* pcie_perstn_m0 */
++ <3 RK_PB0 5 &pcfg_pull_none>,
++ /* pcie_waken_m0 */
++ <3 RK_PA7 5 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pciem1_pins: pciem1-pins {
++ rockchip,pins =
++ /* pcie_clkreqn_m1 */
++ <1 RK_PA0 4 &pcfg_pull_none>,
++ /* pcie_perstn_m1 */
++ <1 RK_PA2 4 &pcfg_pull_none>,
++ /* pcie_waken_m1 */
++ <1 RK_PA1 4 &pcfg_pull_none>;
++ };
++ };
++
++ pdm {
++ /omit-if-no-ref/
++ pdm_clk0: pdm-clk0 {
++ rockchip,pins =
++ /* pdm_clk0 */
++ <4 RK_PB5 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm_clk1: pdm-clk1 {
++ rockchip,pins =
++ /* pdm_clk1 */
++ <4 RK_PA4 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm_sdi0: pdm-sdi0 {
++ rockchip,pins =
++ /* pdm_sdi0 */
++ <4 RK_PB2 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm_sdi1: pdm-sdi1 {
++ rockchip,pins =
++ /* pdm_sdi1 */
++ <4 RK_PB1 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm_sdi2: pdm-sdi2 {
++ rockchip,pins =
++ /* pdm_sdi2 */
++ <4 RK_PB3 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ pdm_sdi3: pdm-sdi3 {
++ rockchip,pins =
++ /* pdm_sdi3 */
++ <4 RK_PC1 3 &pcfg_pull_none>;
++ };
++ };
++
++ pmu {
++ /omit-if-no-ref/
++ pmu_pins: pmu-pins {
++ rockchip,pins =
++ /* pmu_debug */
++ <4 RK_PA0 4 &pcfg_pull_none>;
++ };
++ };
++
++ pwm0 {
++ /omit-if-no-ref/
++ pwm0m0_pins: pwm0m0-pins {
++ rockchip,pins =
++ /* pwm0_m0 */
++ <4 RK_PC3 1 &pcfg_pull_none_drv_level_0>;
++ };
++
++ /omit-if-no-ref/
++ pwm0m1_pins: pwm0m1-pins {
++ rockchip,pins =
++ /* pwm0_m1 */
++ <1 RK_PA2 5 &pcfg_pull_none_drv_level_0>;
++ };
++ };
++
++ pwm1 {
++ /omit-if-no-ref/
++ pwm1m0_pins: pwm1m0-pins {
++ rockchip,pins =
++ /* pwm1_m0 */
++ <4 RK_PC4 1 &pcfg_pull_none_drv_level_0>;
++ };
++
++ /omit-if-no-ref/
++ pwm1m1_pins: pwm1m1-pins {
++ rockchip,pins =
++ /* pwm1_m1 */
++ <1 RK_PA3 4 &pcfg_pull_none_drv_level_0>;
++ };
++ };
++
++ pwm2 {
++ /omit-if-no-ref/
++ pwm2m0_pins: pwm2m0-pins {
++ rockchip,pins =
++ /* pwm2_m0 */
++ <4 RK_PC5 1 &pcfg_pull_none_drv_level_0>;
++ };
++
++ /omit-if-no-ref/
++ pwm2m1_pins: pwm2m1-pins {
++ rockchip,pins =
++ /* pwm2_m1 */
++ <1 RK_PA7 2 &pcfg_pull_none_drv_level_0>;
++ };
++ };
++
++ pwm3 {
++ /omit-if-no-ref/
++ pwm3m0_pins: pwm3m0-pins {
++ rockchip,pins =
++ /* pwm3_m0 */
++ <4 RK_PC6 1 &pcfg_pull_none_drv_level_0>;
++ };
++
++ /omit-if-no-ref/
++ pwm3m1_pins: pwm3m1-pins {
++ rockchip,pins =
++ /* pwm3_m1 */
++ <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>;
++ };
++ };
++
++ pwm4 {
++ /omit-if-no-ref/
++ pwm4m0_pins: pwm4m0-pins {
++ rockchip,pins =
++ /* pwm4_m0 */
++ <4 RK_PB7 1 &pcfg_pull_none_drv_level_0>;
++ };
++
++ /omit-if-no-ref/
++ pwm4m1_pins: pwm4m1-pins {
++ rockchip,pins =
++ /* pwm4_m1 */
++ <1 RK_PA4 2 &pcfg_pull_none_drv_level_0>;
++ };
++ };
++
++ pwm5 {
++ /omit-if-no-ref/
++ pwm5m0_pins: pwm5m0-pins {
++ rockchip,pins =
++ /* pwm5_m0 */
++ <4 RK_PC0 1 &pcfg_pull_none_drv_level_0>;
++ };
++
++ /omit-if-no-ref/
++ pwm5m1_pins: pwm5m1-pins {
++ rockchip,pins =
++ /* pwm5_m1 */
++ <3 RK_PC3 1 &pcfg_pull_none_drv_level_0>;
++ };
++ };
++
++ pwm6 {
++ /omit-if-no-ref/
++ pwm6m0_pins: pwm6m0-pins {
++ rockchip,pins =
++ /* pwm6_m0 */
++ <4 RK_PC1 1 &pcfg_pull_none_drv_level_0>;
++ };
++
++ /omit-if-no-ref/
++ pwm6m1_pins: pwm6m1-pins {
++ rockchip,pins =
++ /* pwm6_m1 */
++ <1 RK_PC3 3 &pcfg_pull_none_drv_level_0>;
++ };
++
++ /omit-if-no-ref/
++ pwm6m2_pins: pwm6m2-pins {
++ rockchip,pins =
++ /* pwm6_m2 */
++ <3 RK_PC1 1 &pcfg_pull_none_drv_level_0>;
++ };
++ };
++
++ pwm7 {
++ /omit-if-no-ref/
++ pwm7m0_pins: pwm7m0-pins {
++ rockchip,pins =
++ /* pwm7_m0 */
++ <4 RK_PC2 1 &pcfg_pull_none_drv_level_0>;
++ };
++
++ /omit-if-no-ref/
++ pwm7m1_pins: pwm7m1-pins {
++ rockchip,pins =
++ /* pwm7_m1 */
++ <1 RK_PC2 2 &pcfg_pull_none_drv_level_0>;
++ };
++ };
++
++ pwr {
++ /omit-if-no-ref/
++ pwr_pins: pwr-pins {
++ rockchip,pins =
++ /* pwr_ctrl0 */
++ <4 RK_PC2 2 &pcfg_pull_none>,
++ /* pwr_ctrl1 */
++ <4 RK_PB6 1 &pcfg_pull_none>;
++ };
++ };
++
++ ref {
++ /omit-if-no-ref/
++ refm0_pins: refm0-pins {
++ rockchip,pins =
++ /* ref_clk_out_m0 */
++ <0 RK_PA1 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ refm1_pins: refm1-pins {
++ rockchip,pins =
++ /* ref_clk_out_m1 */
++ <3 RK_PC3 6 &pcfg_pull_none>;
++ };
++ };
++
++ rgmii {
++ /omit-if-no-ref/
++ rgmii_miim: rgmii-miim {
++ rockchip,pins =
++ /* rgmii_mdc */
++ <3 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
++ /* rgmii_mdio */
++ <3 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ rgmii_rx_bus2: rgmii-rx_bus2 {
++ rockchip,pins =
++ /* rgmii_rxd0 */
++ <3 RK_PA3 2 &pcfg_pull_none>,
++ /* rgmii_rxd1 */
++ <3 RK_PA2 2 &pcfg_pull_none>,
++ /* rgmii_rxdv_crs */
++ <3 RK_PC2 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ rgmii_tx_bus2: rgmii-tx_bus2 {
++ rockchip,pins =
++ /* rgmii_txd0 */
++ <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
++ /* rgmii_txd1 */
++ <3 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
++ /* rgmii_txen */
++ <3 RK_PC0 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ rgmii_rgmii_clk: rgmii-rgmii_clk {
++ rockchip,pins =
++ /* rgmii_rxclk */
++ <3 RK_PA5 2 &pcfg_pull_none>,
++ /* rgmii_txclk */
++ <3 RK_PA4 2 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ rgmii_rgmii_bus: rgmii-rgmii_bus {
++ rockchip,pins =
++ /* rgmii_rxd2 */
++ <3 RK_PA7 2 &pcfg_pull_none>,
++ /* rgmii_rxd3 */
++ <3 RK_PA6 2 &pcfg_pull_none>,
++ /* rgmii_txd2 */
++ <3 RK_PB1 2 &pcfg_pull_none_drv_level_2>,
++ /* rgmii_txd3 */
++ <3 RK_PB0 2 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ rgmii_clk: rgmii-clk {
++ rockchip,pins =
++ /* rgmii_clk */
++ <3 RK_PB4 2 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ rgmii_txer: rgmii-txer {
++ rockchip,pins =
++ /* rgmii_txer */
++ <3 RK_PC1 2 &pcfg_pull_none>;
++ };
++ };
++
++ scr {
++ /omit-if-no-ref/
++ scrm0_pins: scrm0-pins {
++ rockchip,pins =
++ /* scr_clk_m0 */
++ <1 RK_PA2 3 &pcfg_pull_none>,
++ /* scr_data_m0 */
++ <1 RK_PA1 3 &pcfg_pull_none>,
++ /* scr_detn_m0 */
++ <1 RK_PA0 3 &pcfg_pull_none>,
++ /* scr_rstn_m0 */
++ <1 RK_PA3 3 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ scrm1_pins: scrm1-pins {
++ rockchip,pins =
++ /* scr_clk_m1 */
++ <2 RK_PA5 3 &pcfg_pull_none>,
++ /* scr_data_m1 */
++ <2 RK_PA3 4 &pcfg_pull_none>,
++ /* scr_detn_m1 */
++ <2 RK_PA6 3 &pcfg_pull_none>,
++ /* scr_rstn_m1 */
++ <2 RK_PA4 4 &pcfg_pull_none>;
++ };
++ };
++
++ sdio0 {
++ /omit-if-no-ref/
++ sdio0_bus4: sdio0-bus4 {
++ rockchip,pins =
++ /* sdio0_d0 */
++ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
++ /* sdio0_d1 */
++ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
++ /* sdio0_d2 */
++ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
++ /* sdio0_d3 */
++ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdio0_clk: sdio0-clk {
++ rockchip,pins =
++ /* sdio0_clk */
++ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdio0_cmd: sdio0-cmd {
++ rockchip,pins =
++ /* sdio0_cmd */
++ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdio0_det: sdio0-det {
++ rockchip,pins =
++ /* sdio0_det */
++ <1 RK_PA6 1 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ sdio0_pwren: sdio0-pwren {
++ rockchip,pins =
++ /* sdio0_pwren */
++ <1 RK_PA7 1 &pcfg_pull_none>;
++ };
++ };
++
++ sdio1 {
++ /omit-if-no-ref/
++ sdio1_bus4: sdio1-bus4 {
++ rockchip,pins =
++ /* sdio1_d0 */
++ <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
++ /* sdio1_d1 */
++ <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
++ /* sdio1_d2 */
++ <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
++ /* sdio1_d3 */
++ <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdio1_clk: sdio1-clk {
++ rockchip,pins =
++ /* sdio1_clk */
++ <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdio1_cmd: sdio1-cmd {
++ rockchip,pins =
++ /* sdio1_cmd */
++ <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdio1_det: sdio1-det {
++ rockchip,pins =
++ /* sdio1_det */
++ <3 RK_PB3 1 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ sdio1_pwren: sdio1-pwren {
++ rockchip,pins =
++ /* sdio1_pwren */
++ <3 RK_PB2 1 &pcfg_pull_none>;
++ };
++ };
++
++ sdmmc {
++ /omit-if-no-ref/
++ sdmmc_bus4: sdmmc-bus4 {
++ rockchip,pins =
++ /* sdmmc_d0 */
++ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
++ /* sdmmc_d1 */
++ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
++ /* sdmmc_d2 */
++ <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
++ /* sdmmc_d3 */
++ <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc_clk: sdmmc-clk {
++ rockchip,pins =
++ /* sdmmc_clk */
++ <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc_cmd: sdmmc-cmd {
++ rockchip,pins =
++ /* sdmmc_cmd */
++ <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc_det: sdmmc-det {
++ rockchip,pins =
++ /* sdmmc_detn */
++ <2 RK_PA6 1 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ sdmmc_pwren: sdmmc-pwren {
++ rockchip,pins =
++ /* sdmmc_pwren */
++ <4 RK_PA1 1 &pcfg_pull_none>;
++ };
++ };
++
++ spdif {
++ /omit-if-no-ref/
++ spdifm0_pins: spdifm0-pins {
++ rockchip,pins =
++ /* spdif_tx_m0 */
++ <4 RK_PA0 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm1_pins: spdifm1-pins {
++ rockchip,pins =
++ /* spdif_tx_m1 */
++ <1 RK_PC3 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ spdifm2_pins: spdifm2-pins {
++ rockchip,pins =
++ /* spdif_tx_m2 */
++ <3 RK_PC3 2 &pcfg_pull_none>;
++ };
++ };
++
++ spi0 {
++ /omit-if-no-ref/
++ spi0_pins: spi0-pins {
++ rockchip,pins =
++ /* spi0_clk */
++ <4 RK_PB4 2 &pcfg_pull_none_drv_level_2>,
++ /* spi0_miso */
++ <4 RK_PB3 2 &pcfg_pull_none_drv_level_2>,
++ /* spi0_mosi */
++ <4 RK_PB2 2 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ spi0_csn0: spi0-csn0 {
++ rockchip,pins =
++ /* spi0_csn0 */
++ <4 RK_PB6 2 &pcfg_pull_none_drv_level_2>;
++ };
++ /omit-if-no-ref/
++ spi0_csn1: spi0-csn1 {
++ rockchip,pins =
++ /* spi0_csn1 */
++ <4 RK_PC1 2 &pcfg_pull_none_drv_level_2>;
++ };
++ };
++
++ spi1 {
++ /omit-if-no-ref/
++ spi1_pins: spi1-pins {
++ rockchip,pins =
++ /* spi1_clk */
++ <1 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
++ /* spi1_miso */
++ <1 RK_PC0 2 &pcfg_pull_none_drv_level_2>,
++ /* spi1_mosi */
++ <1 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
++ };
++
++ /omit-if-no-ref/
++ spi1_csn0: spi1-csn0 {
++ rockchip,pins =
++ /* spi1_csn0 */
++ <1 RK_PC1 1 &pcfg_pull_none_drv_level_2>;
++ };
++ /omit-if-no-ref/
++ spi1_csn1: spi1-csn1 {
++ rockchip,pins =
++ /* spi1_csn1 */
++ <1 RK_PC2 1 &pcfg_pull_none_drv_level_2>;
++ };
++ };
++
++ tsi0 {
++ /omit-if-no-ref/
++ tsi0_pins: tsi0-pins {
++ rockchip,pins =
++ /* tsi0_clkin */
++ <3 RK_PB2 3 &pcfg_pull_none>,
++ /* tsi0_d0 */
++ <3 RK_PB1 3 &pcfg_pull_none>,
++ /* tsi0_d1 */
++ <3 RK_PB5 3 &pcfg_pull_none>,
++ /* tsi0_d2 */
++ <3 RK_PB6 3 &pcfg_pull_none>,
++ /* tsi0_d3 */
++ <3 RK_PB7 3 &pcfg_pull_none>,
++ /* tsi0_d4 */
++ <3 RK_PA3 3 &pcfg_pull_none>,
++ /* tsi0_d5 */
++ <3 RK_PA2 3 &pcfg_pull_none>,
++ /* tsi0_d6 */
++ <3 RK_PA1 3 &pcfg_pull_none>,
++ /* tsi0_d7 */
++ <3 RK_PA0 3 &pcfg_pull_none>,
++ /* tsi0_fail */
++ <3 RK_PC0 3 &pcfg_pull_none>,
++ /* tsi0_sync */
++ <3 RK_PB4 3 &pcfg_pull_none>,
++ /* tsi0_valid */
++ <3 RK_PB3 3 &pcfg_pull_none>;
++ };
++ };
++
++ tsi1 {
++ /omit-if-no-ref/
++ tsi1_pins: tsi1-pins {
++ rockchip,pins =
++ /* tsi1_clkin */
++ <3 RK_PA5 3 &pcfg_pull_none>,
++ /* tsi1_d0 */
++ <3 RK_PA4 3 &pcfg_pull_none>,
++ /* tsi1_sync */
++ <3 RK_PA7 3 &pcfg_pull_none>,
++ /* tsi1_valid */
++ <3 RK_PA6 3 &pcfg_pull_none>;
++ };
++ };
++
++ uart0 {
++ /omit-if-no-ref/
++ uart0m0_xfer: uart0m0-xfer {
++ rockchip,pins =
++ /* uart0_rx_m0 */
++ <4 RK_PC7 1 &pcfg_pull_up>,
++ /* uart0_tx_m0 */
++ <4 RK_PD0 1 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart0m1_xfer: uart0m1-xfer {
++ rockchip,pins =
++ /* uart0_rx_m1 */
++ <2 RK_PA0 2 &pcfg_pull_up>,
++ /* uart0_tx_m1 */
++ <2 RK_PA1 2 &pcfg_pull_up>;
++ };
++ };
++
++ uart1 {
++ /omit-if-no-ref/
++ uart1m0_xfer: uart1m0-xfer {
++ rockchip,pins =
++ /* uart1_rx_m0 */
++ <4 RK_PA7 2 &pcfg_pull_up>,
++ /* uart1_tx_m0 */
++ <4 RK_PA6 2 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart1m1_xfer: uart1m1-xfer {
++ rockchip,pins =
++ /* uart1_rx_m1 */
++ <4 RK_PC6 2 &pcfg_pull_up>,
++ /* uart1_tx_m1 */
++ <4 RK_PC5 2 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart1_ctsn: uart1-ctsn {
++ rockchip,pins =
++ /* uart1_ctsn */
++ <4 RK_PA4 2 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart1_rtsn: uart1-rtsn {
++ rockchip,pins =
++ /* uart1_rtsn */
++ <4 RK_PA5 2 &pcfg_pull_none>;
++ };
++ };
++
++ uart2 {
++ /omit-if-no-ref/
++ uart2m0_xfer: uart2m0-xfer {
++ rockchip,pins =
++ /* uart2_rx_m0 */
++ <3 RK_PA0 1 &pcfg_pull_up>,
++ /* uart2_tx_m0 */
++ <3 RK_PA1 1 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart2m0_ctsn: uart2m0-ctsn {
++ rockchip,pins =
++ /* uart2m0_ctsn */
++ <3 RK_PA3 1 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart2m0_rtsn: uart2m0-rtsn {
++ rockchip,pins =
++ /* uart2m0_rtsn */
++ <3 RK_PA2 1 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart2m1_xfer: uart2m1-xfer {
++ rockchip,pins =
++ /* uart2_rx_m1 */
++ <1 RK_PB0 1 &pcfg_pull_up>,
++ /* uart2_tx_m1 */
++ <1 RK_PB1 1 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart2m1_ctsn: uart2m1-ctsn {
++ rockchip,pins =
++ /* uart2m1_ctsn */
++ <1 RK_PB3 1 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart2m1_rtsn: uart2m1-rtsn {
++ rockchip,pins =
++ /* uart2m1_rtsn */
++ <1 RK_PB2 1 &pcfg_pull_none>;
++ };
++ };
++
++ uart3 {
++ /omit-if-no-ref/
++ uart3m0_xfer: uart3m0-xfer {
++ rockchip,pins =
++ /* uart3_rx_m0 */
++ <4 RK_PB0 2 &pcfg_pull_up>,
++ /* uart3_tx_m0 */
++ <4 RK_PB1 2 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart3m1_xfer: uart3m1-xfer {
++ rockchip,pins =
++ /* uart3_rx_m1 */
++ <4 RK_PB7 3 &pcfg_pull_up>,
++ /* uart3_tx_m1 */
++ <4 RK_PC0 3 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart3_ctsn: uart3-ctsn {
++ rockchip,pins =
++ /* uart3_ctsn */
++ <4 RK_PA3 3 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart3_rtsn: uart3-rtsn {
++ rockchip,pins =
++ /* uart3_rtsn */
++ <4 RK_PA2 3 &pcfg_pull_none>;
++ };
++ };
++
++ uart4 {
++ /omit-if-no-ref/
++ uart4_xfer: uart4-xfer {
++ rockchip,pins =
++ /* uart4_rx */
++ <2 RK_PA2 3 &pcfg_pull_up>,
++ /* uart4_tx */
++ <2 RK_PA3 3 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart4_ctsn: uart4-ctsn {
++ rockchip,pins =
++ /* uart4_ctsn */
++ <2 RK_PA1 3 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart4_rtsn: uart4-rtsn {
++ rockchip,pins =
++ /* uart4_rtsn */
++ <2 RK_PA0 3 &pcfg_pull_none>;
++ };
++ };
++
++ uart5 {
++ /omit-if-no-ref/
++ uart5m0_xfer: uart5m0-xfer {
++ rockchip,pins =
++ /* uart5_rx_m0 */
++ <1 RK_PA2 2 &pcfg_pull_up>,
++ /* uart5_tx_m0 */
++ <1 RK_PA3 2 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart5m0_ctsn: uart5m0-ctsn {
++ rockchip,pins =
++ /* uart5m0_ctsn */
++ <1 RK_PA6 2 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart5m0_rtsn: uart5m0-rtsn {
++ rockchip,pins =
++ /* uart5m0_rtsn */
++ <1 RK_PA5 2 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart5m1_xfer: uart5m1-xfer {
++ rockchip,pins =
++ /* uart5_rx_m1 */
++ <1 RK_PD4 2 &pcfg_pull_up>,
++ /* uart5_tx_m1 */
++ <1 RK_PD7 2 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart5m1_ctsn: uart5m1-ctsn {
++ rockchip,pins =
++ /* uart5m1_ctsn */
++ <1 RK_PD3 2 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart5m1_rtsn: uart5m1-rtsn {
++ rockchip,pins =
++ /* uart5m1_rtsn */
++ <1 RK_PD2 2 &pcfg_pull_none>;
++ };
++ };
++
++ uart6 {
++ /omit-if-no-ref/
++ uart6m0_xfer: uart6m0-xfer {
++ rockchip,pins =
++ /* uart6_rx_m0 */
++ <3 RK_PA7 4 &pcfg_pull_up>,
++ /* uart6_tx_m0 */
++ <3 RK_PA6 4 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart6m1_xfer: uart6m1-xfer {
++ rockchip,pins =
++ /* uart6_rx_m1 */
++ <3 RK_PC3 4 &pcfg_pull_up>,
++ /* uart6_tx_m1 */
++ <3 RK_PC1 4 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart6_ctsn: uart6-ctsn {
++ rockchip,pins =
++ /* uart6_ctsn */
++ <3 RK_PA4 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart6_rtsn: uart6-rtsn {
++ rockchip,pins =
++ /* uart6_rtsn */
++ <3 RK_PA5 4 &pcfg_pull_none>;
++ };
++ };
++
++ uart7 {
++ /omit-if-no-ref/
++ uart7m0_xfer: uart7m0-xfer {
++ rockchip,pins =
++ /* uart7_rx_m0 */
++ <3 RK_PB3 4 &pcfg_pull_up>,
++ /* uart7_tx_m0 */
++ <3 RK_PB2 4 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart7m0_ctsn: uart7m0-ctsn {
++ rockchip,pins =
++ /* uart7m0_ctsn */
++ <3 RK_PB0 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart7m0_rtsn: uart7m0-rtsn {
++ rockchip,pins =
++ /* uart7m0_rtsn */
++ <3 RK_PB1 4 &pcfg_pull_none>;
++ };
++
++ /omit-if-no-ref/
++ uart7m1_xfer: uart7m1-xfer {
++ rockchip,pins =
++ /* uart7_rx_m1 */
++ <1 RK_PB3 4 &pcfg_pull_up>,
++ /* uart7_tx_m1 */
++ <1 RK_PB2 4 &pcfg_pull_up>;
++ };
++
++ /omit-if-no-ref/
++ uart7m1_ctsn: uart7m1-ctsn {
++ rockchip,pins =
++ /* uart7m1_ctsn */
++ <1 RK_PB0 4 &pcfg_pull_none>;
++ };
++ /omit-if-no-ref/
++ uart7m1_rtsn: uart7m1-rtsn {
++ rockchip,pins =
++ /* uart7m1_rtsn */
++ <1 RK_PB1 4 &pcfg_pull_none>;
++ };
++ };
++};
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -4,8 +4,10 @@
+ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
+ */
+
++#include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/clock/rockchip,rk3528-cru.h>
+
+ / {
+@@ -16,6 +18,11 @@
+ #size-cells = <2>;
+
+ aliases {
++ gpio0 = &gpio0;
++ gpio1 = &gpio1;
++ gpio2 = &gpio2;
++ gpio3 = &gpio3;
++ gpio4 = &gpio4;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+@@ -165,6 +172,11 @@
+ #reset-cells = <1>;
+ };
+
++ ioc_grf: syscon@ff540000 {
++ compatible = "rockchip,rk3528-ioc-grf", "syscon";
++ reg = <0x0 0xff540000 0x0 0x40000>;
++ };
++
+ uart0: serial@ff9f0000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff9f0000 0x0 0x100>;
+@@ -251,5 +263,75 @@
+ reg-shift = <2>;
+ status = "disabled";
+ };
++
++ pinctrl: pinctrl {
++ compatible = "rockchip,rk3528-pinctrl";
++ rockchip,grf = <&ioc_grf>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ gpio0: gpio@ff610000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0xff610000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
++ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pinctrl 0 0 32>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio1: gpio@ffaf0000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0xffaf0000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
++ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pinctrl 0 32 32>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio2: gpio@ffb00000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0xffb00000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
++ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pinctrl 0 64 32>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio3: gpio@ffb10000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0xffb10000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
++ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pinctrl 0 96 32>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio4: gpio@ffb20000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0xffb20000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
++ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pinctrl 0 128 32>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++ };
+ };
+ };
++
++#include "rk3528-pinctrl.dtsi"
--- /dev/null
+From 61a05d8ca3030a544175671f5fab7a8f29c24085 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Thu, 6 Mar 2025 20:38:09 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add rk3528 QoS register node
+
+The Quality-of-Service (QsS) node stores/restores specific
+register contents when the power domains is turned off/on.
+Add QoS node so that they can connect to the power domain.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20250306123809.273655-3-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 160 +++++++++++++++++++++++
+ 1 file changed, 160 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -129,6 +129,166 @@
+ #interrupt-cells = <3>;
+ };
+
++ qos_crypto_a: qos@ff200000 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff200000 0x0 0x20>;
++ };
++
++ qos_crypto_p: qos@ff200080 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff200080 0x0 0x20>;
++ };
++
++ qos_dcf: qos@ff200100 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff200100 0x0 0x20>;
++ };
++
++ qos_dft2apb: qos@ff200200 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff200200 0x0 0x20>;
++ };
++
++ qos_dma2ddr: qos@ff200280 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff200280 0x0 0x20>;
++ };
++
++ qos_dmac: qos@ff200300 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff200300 0x0 0x20>;
++ };
++
++ qos_keyreader: qos@ff200380 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff200380 0x0 0x20>;
++ };
++
++ qos_cpu: qos@ff210000 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff210000 0x0 0x20>;
++ };
++
++ qos_debug: qos@ff210080 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff210080 0x0 0x20>;
++ };
++
++ qos_gpu_m0: qos@ff220000 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff220000 0x0 0x20>;
++ };
++
++ qos_gpu_m1: qos@ff220080 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff220080 0x0 0x20>;
++ };
++
++ qos_pmu_mcu: qos@ff240000 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff240000 0x0 0x20>;
++ };
++
++ qos_rkvdec: qos@ff250000 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff250000 0x0 0x20>;
++ };
++
++ qos_rkvenc: qos@ff260000 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff260000 0x0 0x20>;
++ };
++
++ qos_gmac0: qos@ff270000 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff270000 0x0 0x20>;
++ };
++
++ qos_hdcp: qos@ff270080 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff270080 0x0 0x20>;
++ };
++
++ qos_jpegdec: qos@ff270100 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff270100 0x0 0x20>;
++ };
++
++ qos_rga2_m0ro: qos@ff270200 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff270200 0x0 0x20>;
++ };
++
++ qos_rga2_m0wo: qos@ff270280 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff270280 0x0 0x20>;
++ };
++
++ qos_sdmmc0: qos@ff270300 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff270300 0x0 0x20>;
++ };
++
++ qos_usb2host: qos@ff270380 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff270380 0x0 0x20>;
++ };
++
++ qos_vdpp: qos@ff270480 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff270480 0x0 0x20>;
++ };
++
++ qos_vop: qos@ff270500 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff270500 0x0 0x20>;
++ };
++
++ qos_emmc: qos@ff280000 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff280000 0x0 0x20>;
++ };
++
++ qos_fspi: qos@ff280080 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff280080 0x0 0x20>;
++ };
++
++ qos_gmac1: qos@ff280100 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff280100 0x0 0x20>;
++ };
++
++ qos_pcie: qos@ff280180 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff280180 0x0 0x20>;
++ };
++
++ qos_sdio0: qos@ff280200 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff280200 0x0 0x20>;
++ };
++
++ qos_sdio1: qos@ff280280 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff280280 0x0 0x20>;
++ };
++
++ qos_tsp: qos@ff280300 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff280300 0x0 0x20>;
++ };
++
++ qos_usb3otg: qos@ff280380 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff280380 0x0 0x20>;
++ };
++
++ qos_vpu: qos@ff280400 {
++ compatible = "rockchip,rk3528-qos", "syscon";
++ reg = <0x0 0xff280400 0x0 0x20>;
++ };
++
+ cru: clock-controller@ff4a0000 {
+ compatible = "rockchip,rk3528-cru";
+ reg = <0x0 0xff4a0000 0x0 0x30000>;
--- /dev/null
+From fbcbc1fb93e14729bd87ab386b7f62694dcc8b51 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Fri, 7 Mar 2025 18:00:08 +0800
+Subject: [PATCH] arm64: dts: rockchip: enable SCMI clk for RK3528 SoC
+
+Same as RK3568, RK3528 uses SCMI clk instead of ARMCLK.
+Add SCMI clk for CPU, GPU and RNG will also use it.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20250307100008.789129-2-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 31 ++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -59,6 +59,7 @@
+ reg = <0x0>;
+ device_type = "cpu";
+ enable-method = "psci";
++ clocks = <&scmi_clk SCMI_CLK_CPU>;
+ };
+
+ cpu1: cpu@1 {
+@@ -66,6 +67,7 @@
+ reg = <0x1>;
+ device_type = "cpu";
+ enable-method = "psci";
++ clocks = <&scmi_clk SCMI_CLK_CPU>;
+ };
+
+ cpu2: cpu@2 {
+@@ -73,6 +75,7 @@
+ reg = <0x2>;
+ device_type = "cpu";
+ enable-method = "psci";
++ clocks = <&scmi_clk SCMI_CLK_CPU>;
+ };
+
+ cpu3: cpu@3 {
+@@ -80,6 +83,22 @@
+ reg = <0x3>;
+ device_type = "cpu";
+ enable-method = "psci";
++ clocks = <&scmi_clk SCMI_CLK_CPU>;
++ };
++ };
++
++ firmware {
++ scmi: scmi {
++ compatible = "arm,scmi-smc";
++ arm,smc-id = <0x82000010>;
++ shmem = <&scmi_shmem>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ scmi_clk: protocol@14 {
++ reg = <0x14>;
++ #clock-cells = <1>;
++ };
+ };
+ };
+
+@@ -88,6 +107,18 @@
+ method = "smc";
+ };
+
++ reserved-memory {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ scmi_shmem: shmem@10f000 {
++ compatible = "arm,scmi-shmem";
++ reg = <0x0 0x0010f000 0x0 0x100>;
++ no-map;
++ };
++ };
++
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
--- /dev/null
+From 6e58302c84ce90aadbecd41efe1f69098a6f91e5 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 4 Mar 2025 20:16:36 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add SARADC node for RK3528
+
+Add a device tree node for the SARADC controller used by RK3528.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250304201642.831218-4-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/clock/rockchip,rk3528-cru.h>
++#include <dt-bindings/reset/rockchip,rk3528-cru.h>
+
+ / {
+ compatible = "rockchip,rk3528";
+@@ -455,6 +456,18 @@
+ status = "disabled";
+ };
+
++ saradc: adc@ffae0000 {
++ compatible = "rockchip,rk3528-saradc";
++ reg = <0x0 0xffae0000 0x0 0x10000>;
++ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
++ clock-names = "saradc", "apb_pclk";
++ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
++ resets = <&cru SRST_P_SARADC>;
++ reset-names = "saradc-apb";
++ #io-channel-cells = <1>;
++ status = "disabled";
++ };
++
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3528-pinctrl";
+ rockchip,grf = <&ioc_grf>;
--- /dev/null
+From a98cc47f79ab5b8059b748bf0bd59335edfff7d9 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 5 Mar 2025 21:41:03 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add SDHCI controller for RK3528
+
+The SDHCI controller in Rockchip RK3528 is similar to the one included
+in RK3588.
+
+Add device tree node for the SDHCI controller in RK3528.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250305214108.1327208-3-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -468,6 +468,30 @@
+ status = "disabled";
+ };
+
++ sdhci: mmc@ffbf0000 {
++ compatible = "rockchip,rk3528-dwcmshc",
++ "rockchip,rk3588-dwcmshc";
++ reg = <0x0 0xffbf0000 0x0 0x10000>;
++ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
++ <&cru CCLK_SRC_EMMC>;
++ assigned-clock-rates = <200000000>, <24000000>,
++ <200000000>;
++ clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
++ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
++ <&cru TCLK_EMMC>;
++ clock-names = "core", "bus", "axi", "block", "timer";
++ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
++ max-frequency = <200000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
++ <&emmc_strb>;
++ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
++ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
++ <&cru SRST_T_EMMC>;
++ reset-names = "core", "bus", "axi", "block", "timer";
++ status = "disabled";
++ };
++
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3528-pinctrl";
+ rockchip,grf = <&ioc_grf>;
--- /dev/null
+From a37d21a9b45e47ed6bc1f94e738096c07db78a07 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Tue, 1 Apr 2025 18:00:18 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add missing uart3 interrupt for RK3528
+
+The interrupt of uart3 node on rk3528 is missing, fix it.
+
+Fixes: 7983e6c379a9 ("arm64: dts: rockchip: Add base DT for rk3528 SoC")
+Reviewed-by: Yao Zi <ziyao@disroot.org>
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20250401100020.944658-2-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -404,9 +404,10 @@
+
+ uart3: serial@ffa08000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
++ reg = <0x0 0xffa08000 0x0 0x100>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+- reg = <0x0 0xffa08000 0x0 0x100>;
++ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
--- /dev/null
+From 762b1f6503340b4729bc8a5fa6a5780712012cd8 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Tue, 1 Apr 2025 18:00:19 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add DMA controller for RK3528
+
+Add DMA controller dt node for RK3528 SoC.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20250401100020.944658-3-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -493,6 +493,24 @@
+ status = "disabled";
+ };
+
++ dmac: dma-controller@ffd60000 {
++ compatible = "arm,pl330", "arm,primecell";
++ reg = <0x0 0xffd60000 0x0 0x4000>;
++ clocks = <&cru ACLK_DMAC>;
++ clock-names = "apb_pclk";
++ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
++ #dma-cells = <1>;
++ arm,pl330-periph-burst;
++ };
++
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3528-pinctrl";
+ rockchip,grf = <&ioc_grf>;
--- /dev/null
+From ab6fcb58aedf7df1d146b47d5fedd844a7c346e2 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Tue, 1 Apr 2025 18:00:20 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add UART DMA support for RK3528
+
+The UART ports on RK3528 have DMA capability, describe it.
+Flow control is optional, so dma-names are not added.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20250401100020.944658-4-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -375,6 +375,7 @@
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmac 8>, <&dmac 9>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -386,6 +387,7 @@
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmac 10>, <&dmac 11>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -397,6 +399,7 @@
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmac 12>, <&dmac 13>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -408,6 +411,7 @@
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmac 14>, <&dmac 15>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -419,6 +423,7 @@
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmac 16>, <&dmac 17>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -430,6 +435,7 @@
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmac 18>, <&dmac 19>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -441,6 +447,7 @@
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmac 20>, <&dmac 21>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -452,6 +459,7 @@
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmac 22>, <&dmac 23>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
--- /dev/null
+From d3a05f490d048808968df1e0d3240ab01fe82211 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Thu, 17 Apr 2025 12:01:18 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add I2C controllers for RK3528
+
+Describe I2C controllers shipped by RK3528 in devicetree. For I2C-2,
+I2C-4 and I2C-7 which come with only a set of possible pins, a default
+pin configuration is included.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250417120118.17610-5-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 110 +++++++++++++++++++++++
+ 1 file changed, 110 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -24,6 +24,14 @@
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
++ i2c0 = &i2c0;
++ i2c1 = &i2c1;
++ i2c2 = &i2c2;
++ i2c3 = &i2c3;
++ i2c4 = &i2c4;
++ i2c5 = &i2c5;
++ i2c6 = &i2c6;
++ i2c7 = &i2c7;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+@@ -465,6 +473,108 @@
+ status = "disabled";
+ };
+
++ i2c0: i2c@ffa50000 {
++ compatible = "rockchip,rk3528-i2c",
++ "rockchip,rk3399-i2c";
++ reg = <0x0 0xffa50000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c1: i2c@ffa58000 {
++ compatible = "rockchip,rk3528-i2c",
++ "rockchip,rk3399-i2c";
++ reg = <0x0 0xffa58000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c2: i2c@ffa60000 {
++ compatible = "rockchip,rk3528-i2c",
++ "rockchip,rk3399-i2c";
++ reg = <0x0 0xffa60000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c2m1_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c3: i2c@ffa68000 {
++ compatible = "rockchip,rk3528-i2c",
++ "rockchip,rk3399-i2c";
++ reg = <0x0 0xffa68000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c4: i2c@ffa70000 {
++ compatible = "rockchip,rk3528-i2c",
++ "rockchip,rk3399-i2c";
++ reg = <0x0 0xffa70000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c4_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c5: i2c@ffa78000 {
++ compatible = "rockchip,rk3528-i2c",
++ "rockchip,rk3399-i2c";
++ reg = <0x0 0xffa78000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c6: i2c@ffa80000 {
++ compatible = "rockchip,rk3528-i2c",
++ "rockchip,rk3399-i2c";
++ reg = <0x0 0xffa80000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ i2c7: i2c@ffa88000 {
++ compatible = "rockchip,rk3528-i2c",
++ "rockchip,rk3399-i2c";
++ reg = <0x0 0xffa88000 0x0 0x1000>;
++ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
++ clock-names = "i2c", "pclk";
++ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c7_xfer>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
+ saradc: adc@ffae0000 {
+ compatible = "rockchip,rk3528-saradc";
+ reg = <0x0 0xffae0000 0x0 0x10000>;
--- /dev/null
+From 9e701ad7c3551b3ab87ed5fa439569696ddf42e4 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Tue, 1 Apr 2025 20:00:19 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add pwm nodes for RK3528
+
+Add pwm nodes for RK3528. The PWM core on RK3528 is the same as
+RK3328, but the driver does not support interrupts yet.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250401120020.976343-2-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 80 ++++++++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -575,6 +575,86 @@
+ status = "disabled";
+ };
+
++ pwm0: pwm@ffa90000 {
++ compatible = "rockchip,rk3528-pwm",
++ "rockchip,rk3328-pwm";
++ reg = <0x0 0xffa90000 0x0 0x10>;
++ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
++ clock-names = "pwm", "pclk";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ pwm1: pwm@ffa90010 {
++ compatible = "rockchip,rk3528-pwm",
++ "rockchip,rk3328-pwm";
++ reg = <0x0 0xffa90010 0x0 0x10>;
++ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
++ clock-names = "pwm", "pclk";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ pwm2: pwm@ffa90020 {
++ compatible = "rockchip,rk3528-pwm",
++ "rockchip,rk3328-pwm";
++ reg = <0x0 0xffa90020 0x0 0x10>;
++ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
++ clock-names = "pwm", "pclk";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ pwm3: pwm@ffa90030 {
++ compatible = "rockchip,rk3528-pwm",
++ "rockchip,rk3328-pwm";
++ reg = <0x0 0xffa90030 0x0 0x10>;
++ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
++ clock-names = "pwm", "pclk";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ pwm4: pwm@ffa98000 {
++ compatible = "rockchip,rk3528-pwm",
++ "rockchip,rk3328-pwm";
++ reg = <0x0 0xffa98000 0x0 0x10>;
++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
++ clock-names = "pwm", "pclk";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ pwm5: pwm@ffa98010 {
++ compatible = "rockchip,rk3528-pwm",
++ "rockchip,rk3328-pwm";
++ reg = <0x0 0xffa98010 0x0 0x10>;
++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
++ clock-names = "pwm", "pclk";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ pwm6: pwm@ffa98020 {
++ compatible = "rockchip,rk3528-pwm",
++ "rockchip,rk3328-pwm";
++ reg = <0x0 0xffa98020 0x0 0x10>;
++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
++ clock-names = "pwm", "pclk";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ pwm7: pwm@ffa98030 {
++ compatible = "rockchip,rk3528-pwm",
++ "rockchip,rk3328-pwm";
++ reg = <0x0 0xffa98030 0x0 0x10>;
++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
++ clock-names = "pwm", "pclk";
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
+ saradc: adc@ffae0000 {
+ compatible = "rockchip,rk3528-saradc";
+ reg = <0x0 0xffae0000 0x0 0x10000>;
--- /dev/null
+From 894a2640422208b1d3e4c238f126220d406e5fb1 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Thu, 8 May 2025 23:48:29 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add SDMMC/SDIO controllers for RK3528
+
+RK3528 features two SDIO controllers and one SD/MMC controller, describe
+them in devicetree. Since their sample and drive clocks are located in
+the VO and VPU GRFs, corresponding syscons are added to make these
+clocks available.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250508234829.27111-3-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 69 ++++++++++++++++++++++++
+ 1 file changed, 69 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -329,6 +329,16 @@
+ reg = <0x0 0xff280400 0x0 0x20>;
+ };
+
++ vpu_grf: syscon@ff340000 {
++ compatible = "rockchip,rk3528-vpu-grf", "syscon";
++ reg = <0x0 0xff340000 0x0 0x8000>;
++ };
++
++ vo_grf: syscon@ff360000 {
++ compatible = "rockchip,rk3528-vo-grf", "syscon";
++ reg = <0x0 0xff360000 0x0 0x10000>;
++ };
++
+ cru: clock-controller@ff4a0000 {
+ compatible = "rockchip,rk3528-cru";
+ reg = <0x0 0xff4a0000 0x0 0x30000>;
+@@ -691,6 +701,65 @@
+ status = "disabled";
+ };
+
++ sdio0: mmc@ffc10000 {
++ compatible = "rockchip,rk3528-dw-mshc",
++ "rockchip,rk3288-dw-mshc";
++ reg = <0x0 0xffc10000 0x0 0x4000>;
++ clocks = <&cru HCLK_SDIO0>,
++ <&cru CCLK_SRC_SDIO0>,
++ <&cru SCLK_SDIO0_DRV>,
++ <&cru SCLK_SDIO0_SAMPLE>;
++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++ fifo-depth = <0x100>;
++ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
++ max-frequency = <200000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;
++ resets = <&cru SRST_H_SDIO0>;
++ reset-names = "reset";
++ status = "disabled";
++ };
++
++ sdio1: mmc@ffc20000 {
++ compatible = "rockchip,rk3528-dw-mshc",
++ "rockchip,rk3288-dw-mshc";
++ reg = <0x0 0xffc20000 0x0 0x4000>;
++ clocks = <&cru HCLK_SDIO1>,
++ <&cru CCLK_SRC_SDIO1>,
++ <&cru SCLK_SDIO1_DRV>,
++ <&cru SCLK_SDIO1_SAMPLE>;
++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++ fifo-depth = <0x100>;
++ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
++ max-frequency = <200000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>;
++ resets = <&cru SRST_H_SDIO1>;
++ reset-names = "reset";
++ status = "disabled";
++ };
++
++ sdmmc: mmc@ffc30000 {
++ compatible = "rockchip,rk3528-dw-mshc",
++ "rockchip,rk3288-dw-mshc";
++ reg = <0x0 0xffc30000 0x0 0x4000>;
++ clocks = <&cru HCLK_SDMMC0>,
++ <&cru CCLK_SRC_SDMMC0>,
++ <&cru SCLK_SDMMC_DRV>,
++ <&cru SCLK_SDMMC_SAMPLE>;
++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++ fifo-depth = <0x100>;
++ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
++ max-frequency = <150000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
++ <&sdmmc_det>;
++ resets = <&cru SRST_H_SDMMC0>;
++ reset-names = "reset";
++ rockchip,default-sample-phase = <90>;
++ status = "disabled";
++ };
++
+ dmac: dma-controller@ffd60000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xffd60000 0x0 0x4000>;
--- /dev/null
+From 5eb28f461a1b368a57994cc3b3f2ba3154c00bb8 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Fri, 9 May 2025 20:23:57 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add GMAC nodes for RK3528
+
+Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC
+Ethernet QoS IP.
+
+Add device tree nodes for the two Ethernet controllers in RK3528.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Tested-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20250509202402.260038-2-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 105 +++++++++++++++++++++++
+ 1 file changed, 105 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -677,6 +677,111 @@
+ status = "disabled";
+ };
+
++ gmac0: ethernet@ffbd0000 {
++ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
++ reg = <0x0 0xffbd0000 0x0 0x10000>;
++ clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
++ <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
++ <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
++ clock-names = "stmmaceth", "clk_mac_ref",
++ "mac_clk_rx", "mac_clk_tx",
++ "pclk_mac", "aclk_mac";
++ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq", "eth_wake_irq";
++ phy-handle = <&rmii0_phy>;
++ phy-mode = "rmii";
++ resets = <&cru SRST_A_MAC_VO>;
++ reset-names = "stmmaceth";
++ rockchip,grf = <&vo_grf>;
++ snps,axi-config = <&gmac0_stmmac_axi_setup>;
++ snps,mixed-burst;
++ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
++ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
++ snps,tso;
++ status = "disabled";
++
++ mdio0: mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++
++ rmii0_phy: ethernet-phy@2 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0x2>;
++ clocks = <&cru CLK_MACPHY>;
++ phy-is-integrated;
++ pinctrl-names = "default";
++ pinctrl-0 = <&fephym0_led_link>,
++ <&fephym0_led_spd>;
++ resets = <&cru SRST_MACPHY>;
++ };
++ };
++
++ gmac0_stmmac_axi_setup: stmmac-axi-config {
++ snps,blen = <0 0 0 0 16 8 4>;
++ snps,rd_osr_lmt = <8>;
++ snps,wr_osr_lmt = <4>;
++ };
++
++ gmac0_mtl_rx_setup: rx-queues-config {
++ snps,rx-queues-to-use = <1>;
++ queue0 {};
++ };
++
++ gmac0_mtl_tx_setup: tx-queues-config {
++ snps,tx-queues-to-use = <1>;
++ queue0 {};
++ };
++ };
++
++ gmac1: ethernet@ffbe0000 {
++ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
++ reg = <0x0 0xffbe0000 0x0 0x10000>;
++ clocks = <&cru CLK_GMAC1_SRC_VPU>,
++ <&cru CLK_GMAC1_RMII_VPU>,
++ <&cru PCLK_MAC_VPU>,
++ <&cru ACLK_MAC_VPU>;
++ clock-names = "stmmaceth",
++ "clk_mac_ref",
++ "pclk_mac",
++ "aclk_mac";
++ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq", "eth_wake_irq";
++ resets = <&cru SRST_A_MAC>;
++ reset-names = "stmmaceth";
++ rockchip,grf = <&vpu_grf>;
++ snps,axi-config = <&gmac1_stmmac_axi_setup>;
++ snps,mixed-burst;
++ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
++ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
++ snps,tso;
++ status = "disabled";
++
++ mdio1: mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <0x1>;
++ #size-cells = <0x0>;
++ };
++
++ gmac1_stmmac_axi_setup: stmmac-axi-config {
++ snps,blen = <0 0 0 0 16 8 4>;
++ snps,rd_osr_lmt = <8>;
++ snps,wr_osr_lmt = <4>;
++ };
++
++ gmac1_mtl_rx_setup: rx-queues-config {
++ snps,rx-queues-to-use = <1>;
++ queue0 {};
++ };
++
++ gmac1_mtl_tx_setup: tx-queues-config {
++ snps,tx-queues-to-use = <1>;
++ queue0 {};
++ };
++ };
++
+ sdhci: mmc@ffbf0000 {
+ compatible = "rockchip,rk3528-dwcmshc",
+ "rockchip,rk3588-dwcmshc";
--- /dev/null
+From 7d086f78fe09fb94eb3b2e12436f2feed21d9c1e Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Mon, 19 May 2025 00:04:46 +0200
+Subject: [PATCH] arm64: dts: rockchip: move rk3528 pinctrl node outside the
+ soc node
+
+The non-mmio pinctrl node is not supposed to be inside the soc simple-bus
+as dtc points out:
+
+../arch/arm64/boot/dts/rockchip/rk3528.dtsi:870.20-936.5: Warning (simple_bus_reg): /soc/pinctrl: missing or empty reg/ranges property
+
+Move the pinctrl node outside and adapt the indentation.
+
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250518220449.2722673-5-heiko@sntech.de
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 136 +++++++++++------------
+ 1 file changed, 68 insertions(+), 68 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -111,6 +111,74 @@
+ };
+ };
+
++ pinctrl: pinctrl {
++ compatible = "rockchip,rk3528-pinctrl";
++ rockchip,grf = <&ioc_grf>;
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ gpio0: gpio@ff610000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0xff610000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
++ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pinctrl 0 0 32>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio1: gpio@ffaf0000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0xffaf0000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
++ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pinctrl 0 32 32>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio2: gpio@ffb00000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0xffb00000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
++ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pinctrl 0 64 32>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio3: gpio@ffb10000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0xffb10000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
++ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pinctrl 0 96 32>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++
++ gpio4: gpio@ffb20000 {
++ compatible = "rockchip,gpio-bank";
++ reg = <0x0 0xffb20000 0x0 0x200>;
++ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
++ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ gpio-ranges = <&pinctrl 0 128 32>;
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ };
++ };
++
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+@@ -882,74 +950,6 @@
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ };
+-
+- pinctrl: pinctrl {
+- compatible = "rockchip,rk3528-pinctrl";
+- rockchip,grf = <&ioc_grf>;
+- #address-cells = <2>;
+- #size-cells = <2>;
+- ranges;
+-
+- gpio0: gpio@ff610000 {
+- compatible = "rockchip,gpio-bank";
+- reg = <0x0 0xff610000 0x0 0x200>;
+- clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- gpio-ranges = <&pinctrl 0 0 32>;
+- interrupt-controller;
+- #interrupt-cells = <2>;
+- };
+-
+- gpio1: gpio@ffaf0000 {
+- compatible = "rockchip,gpio-bank";
+- reg = <0x0 0xffaf0000 0x0 0x200>;
+- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- gpio-ranges = <&pinctrl 0 32 32>;
+- interrupt-controller;
+- #interrupt-cells = <2>;
+- };
+-
+- gpio2: gpio@ffb00000 {
+- compatible = "rockchip,gpio-bank";
+- reg = <0x0 0xffb00000 0x0 0x200>;
+- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+- interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- gpio-ranges = <&pinctrl 0 64 32>;
+- interrupt-controller;
+- #interrupt-cells = <2>;
+- };
+-
+- gpio3: gpio@ffb10000 {
+- compatible = "rockchip,gpio-bank";
+- reg = <0x0 0xffb10000 0x0 0x200>;
+- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- gpio-ranges = <&pinctrl 0 96 32>;
+- interrupt-controller;
+- #interrupt-cells = <2>;
+- };
+-
+- gpio4: gpio@ffb20000 {
+- compatible = "rockchip,gpio-bank";
+- reg = <0x0 0xffb20000 0x0 0x200>;
+- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+- gpio-controller;
+- #gpio-cells = <2>;
+- gpio-ranges = <&pinctrl 0 128 32>;
+- interrupt-controller;
+- #interrupt-cells = <2>;
+- };
+- };
+ };
+ };
+
--- /dev/null
+From 2783335329e5762deb0dc5b6d634225d8613af16 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Tue, 20 May 2025 18:01:02 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add spi nodes for RK3528
+
+There are 2 SPI controllers on the RK3528 SoC, describe it.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20250520100102.1226725-3-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 28 ++++++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -455,6 +455,34 @@
+ reg = <0x0 0xff540000 0x0 0x40000>;
+ };
+
++ spi0: spi@ff9c0000 {
++ compatible = "rockchip,rk3528-spi",
++ "rockchip,rk3066-spi";
++ reg = <0x0 0xff9c0000 0x0 0x1000>;
++ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
++ clock-names = "spiclk", "apb_pclk";
++ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmac 25>, <&dmac 24>;
++ dma-names = "tx", "rx";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
++ spi1: spi@ff9d0000 {
++ compatible = "rockchip,rk3528-spi",
++ "rockchip,rk3066-spi";
++ reg = <0x0 0xff9d0000 0x0 0x1000>;
++ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
++ clock-names = "spiclk", "apb_pclk";
++ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
++ dmas = <&dmac 31>, <&dmac 30>;
++ dma-names = "tx", "rx";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ status = "disabled";
++ };
++
+ uart0: serial@ff9f0000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff9f0000 0x0 0x100>;
--- /dev/null
+From 654df8e74dbc19ba0625051079e6889e6999d16e Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 18 May 2025 22:06:51 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add power controller for RK3528
+
+Add power-domain nodes for the power controller on RK3528.
+
+Only PD_GPU can fully be powered down. PD_RKVDEC, PD_RKVENC, PD_VO and
+PD_VPU are idle only power domains used by miscellaneous devices.
+
+Because multiple of the miscellaneous device types currently complain
+about the use of a power-domains prop, only PD_GPU is enabled.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250518220707.669515-5-jonas@kwiboo.se
+[changed to using numeric values, until the next merge-window]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 64 ++++++++++++++++++++++++
+ 1 file changed, 64 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -455,6 +455,70 @@
+ reg = <0x0 0xff540000 0x0 0x40000>;
+ };
+
++ pmu: power-management@ff600000 {
++ compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd";
++ reg = <0x0 0xff600000 0x0 0x2000>;
++
++ power: power-controller {
++ compatible = "rockchip,rk3528-power-controller";
++ #power-domain-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ /* These power domains are grouped by VD_GPU */
++ power-domain@4 {
++ reg = <4>;
++ clocks = <&cru ACLK_GPU_MALI>,
++ <&cru PCLK_GPU_ROOT>;
++ pm_qos = <&qos_gpu_m0>,
++ <&qos_gpu_m1>;
++ #power-domain-cells = <0>;
++ };
++
++ /* These power domains are grouped by VD_LOGIC */
++ power-domain@5 {
++ reg = <5>;
++ pm_qos = <&qos_rkvdec>;
++ #power-domain-cells = <0>;
++ status = "disabled";
++ };
++ power-domain@6 {
++ reg = <6>;
++ pm_qos = <&qos_rkvenc>;
++ #power-domain-cells = <0>;
++ status = "disabled";
++ };
++ power-domain@7 {
++ reg = <7>;
++ pm_qos = <&qos_gmac0>,
++ <&qos_hdcp>,
++ <&qos_jpegdec>,
++ <&qos_rga2_m0ro>,
++ <&qos_rga2_m0wo>,
++ <&qos_sdmmc0>,
++ <&qos_usb2host>,
++ <&qos_vdpp>,
++ <&qos_vop>;
++ #power-domain-cells = <0>;
++ status = "disabled";
++ };
++ power-domain@8 {
++ reg = <8>;
++ pm_qos = <&qos_emmc>,
++ <&qos_fspi>,
++ <&qos_gmac1>,
++ <&qos_pcie>,
++ <&qos_sdio0>,
++ <&qos_sdio1>,
++ <&qos_tsp>,
++ <&qos_usb3otg>,
++ <&qos_vpu>;
++ #power-domain-cells = <0>;
++ status = "disabled";
++ };
++ };
++ };
++
+ spi0: spi@ff9c0000 {
+ compatible = "rockchip,rk3528-spi",
+ "rockchip,rk3066-spi";
--- /dev/null
+From 06601cc45b5ba0c3bcd371b9c499d9fe5dabd11d Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 18 May 2025 22:54:12 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add GPU node for RK3528
+
+Add a GPU node and a opp-table for the Mali-450 MP2 in the RK3528 SoC.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250518225418.682182-3-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 58 ++++++++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -111,6 +111,36 @@
+ };
+ };
+
++ gpu_opp_table: opp-table-gpu {
++ compatible = "operating-points-v2";
++
++ opp-300000000 {
++ opp-hz = /bits/ 64 <300000000>;
++ opp-microvolt = <875000 875000 1000000>;
++ opp-suspend;
++ };
++
++ opp-500000000 {
++ opp-hz = /bits/ 64 <500000000>;
++ opp-microvolt = <875000 875000 1000000>;
++ };
++
++ opp-600000000 {
++ opp-hz = /bits/ 64 <600000000>;
++ opp-microvolt = <875000 875000 1000000>;
++ };
++
++ opp-700000000 {
++ opp-hz = /bits/ 64 <700000000>;
++ opp-microvolt = <900000 900000 1000000>;
++ };
++
++ opp-800000000 {
++ opp-hz = /bits/ 64 <800000000>;
++ opp-microvolt = <950000 950000 1000000>;
++ };
++ };
++
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3528-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+@@ -519,6 +549,34 @@
+ };
+ };
+
++ gpu: gpu@ff700000 {
++ compatible = "rockchip,rk3528-mali", "arm,mali-450";
++ reg = <0x0 0xff700000 0x0 0x40000>;
++ assigned-clocks = <&cru ACLK_GPU_MALI>,
++ <&scmi_clk SCMI_CLK_GPU>;
++ assigned-clock-rates = <297000000>, <300000000>;
++ clocks = <&cru ACLK_GPU_MALI>, <&scmi_clk SCMI_CLK_GPU>;
++ clock-names = "bus", "core";
++ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "gp",
++ "gpmmu",
++ "pp",
++ "pp0",
++ "ppmmu0",
++ "pp1",
++ "ppmmu1";
++ operating-points-v2 = <&gpu_opp_table>;
++ power-domains = <&power 4>;
++ resets = <&cru SRST_A_GPU>;
++ status = "disabled";
++ };
++
+ spi0: spi@ff9c0000 {
+ compatible = "rockchip,rk3528-spi",
+ "rockchip,rk3066-spi";
--- /dev/null
+From f2792bf1c7a54ef23fb3a84286b66f427bfc4853 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 21 Jun 2025 11:38:57 +0000
+Subject: [PATCH] arm64: dts: rockchip: Fix pinctrl node names for RK3528
+
+Following warnings can be observed with CHECK_DTBS=y for the RK3528:
+
+ rk3528-pinctrl.dtsi:101.36-105.5: Warning (node_name_chars_strict):
+ /pinctrl/fephy/fephym0-led_dpx: Character '_' not recommended in node name
+ rk3528-pinctrl.dtsi:108.38-112.5: Warning (node_name_chars_strict):
+ /pinctrl/fephy/fephym0-led_link: Character '_' not recommended in node name
+ rk3528-pinctrl.dtsi:115.36-119.5: Warning (node_name_chars_strict):
+ /pinctrl/fephy/fephym0-led_spd: Character '_' not recommended in node name
+ rk3528-pinctrl.dtsi:122.36-126.5: Warning (node_name_chars_strict):
+ /pinctrl/fephy/fephym1-led_dpx: Character '_' not recommended in node name
+ rk3528-pinctrl.dtsi:129.38-133.5: Warning (node_name_chars_strict):
+ /pinctrl/fephy/fephym1-led_link: Character '_' not recommended in node name
+ rk3528-pinctrl.dtsi:136.36-140.5: Warning (node_name_chars_strict):
+ /pinctrl/fephy/fephym1-led_spd: Character '_' not recommended in node name
+ rk3528-pinctrl.dtsi:782.32-790.5: Warning (node_name_chars_strict):
+ /pinctrl/rgmii/rgmii-rx_bus2: Character '_' not recommended in node name
+ rk3528-pinctrl.dtsi:793.32-801.5: Warning (node_name_chars_strict):
+ /pinctrl/rgmii/rgmii-tx_bus2: Character '_' not recommended in node name
+ rk3528-pinctrl.dtsi:804.36-810.5: Warning (node_name_chars_strict):
+ /pinctrl/rgmii/rgmii-rgmii_clk: Character '_' not recommended in node name
+ rk3528-pinctrl.dtsi:813.36-823.5: Warning (node_name_chars_strict):
+ /pinctrl/rgmii/rgmii-rgmii_bus: Character '_' not recommended in node name
+
+Rename the affected nodes to fix these warnings.
+
+Fixes: a31fad19ae39 ("arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528")
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250621113859.2146400-1-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3528-pinctrl.dtsi | 20 +++++++++----------
+ 1 file changed, 10 insertions(+), 10 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
+@@ -98,42 +98,42 @@
+
+ fephy {
+ /omit-if-no-ref/
+- fephym0_led_dpx: fephym0-led_dpx {
++ fephym0_led_dpx: fephym0-led-dpx {
+ rockchip,pins =
+ /* fephy_led_dpx_m0 */
+ <4 RK_PB5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- fephym0_led_link: fephym0-led_link {
++ fephym0_led_link: fephym0-led-link {
+ rockchip,pins =
+ /* fephy_led_link_m0 */
+ <4 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- fephym0_led_spd: fephym0-led_spd {
++ fephym0_led_spd: fephym0-led-spd {
+ rockchip,pins =
+ /* fephy_led_spd_m0 */
+ <4 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- fephym1_led_dpx: fephym1-led_dpx {
++ fephym1_led_dpx: fephym1-led-dpx {
+ rockchip,pins =
+ /* fephy_led_dpx_m1 */
+ <2 RK_PA4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- fephym1_led_link: fephym1-led_link {
++ fephym1_led_link: fephym1-led-link {
+ rockchip,pins =
+ /* fephy_led_link_m1 */
+ <2 RK_PA6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+- fephym1_led_spd: fephym1-led_spd {
++ fephym1_led_spd: fephym1-led-spd {
+ rockchip,pins =
+ /* fephy_led_spd_m1 */
+ <2 RK_PA5 5 &pcfg_pull_none>;
+@@ -779,7 +779,7 @@
+ };
+
+ /omit-if-no-ref/
+- rgmii_rx_bus2: rgmii-rx_bus2 {
++ rgmii_rx_bus2: rgmii-rx-bus2 {
+ rockchip,pins =
+ /* rgmii_rxd0 */
+ <3 RK_PA3 2 &pcfg_pull_none>,
+@@ -790,7 +790,7 @@
+ };
+
+ /omit-if-no-ref/
+- rgmii_tx_bus2: rgmii-tx_bus2 {
++ rgmii_tx_bus2: rgmii-tx-bus2 {
+ rockchip,pins =
+ /* rgmii_txd0 */
+ <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
+@@ -801,7 +801,7 @@
+ };
+
+ /omit-if-no-ref/
+- rgmii_rgmii_clk: rgmii-rgmii_clk {
++ rgmii_rgmii_clk: rgmii-rgmii-clk {
+ rockchip,pins =
+ /* rgmii_rxclk */
+ <3 RK_PA5 2 &pcfg_pull_none>,
+@@ -810,7 +810,7 @@
+ };
+
+ /omit-if-no-ref/
+- rgmii_rgmii_bus: rgmii-rgmii_bus {
++ rgmii_rgmii_bus: rgmii-rgmii-bus {
+ rockchip,pins =
+ /* rgmii_rxd2 */
+ <3 RK_PA7 2 &pcfg_pull_none>,
--- /dev/null
+From ae019f0bdfbef3e0671e7b954321e92fc24c7e54 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 9 Jul 2025 21:08:28 +0000
+Subject: [PATCH] arm64: dts: rockchip: Fix UART DMA support for RK3528
+
+Trying to use UART2 DMA for Bluetooth on ArmSoM Sige1 result in tx
+timeout when using dma-names = "tx", "rx" as required by the dt-binding:
+
+ Bluetooth: hci0: command 0x0c03 tx timeout
+ Bluetooth: hci0: BCM: Reset failed (-110)
+
+Change the dmas order to fix UART DMA support on RK3528.
+
+With this fixed Bluetooth can be loaded using DMA on ArmSoM Sige1:
+
+ Bluetooth: hci0: BCM: chip id 159
+ Bluetooth: hci0: BCM: features 0x0f
+ Bluetooth: hci0: BCM4362A2
+ Bluetooth: hci0: BCM4362A2 (000.017.017) build 0000
+ Bluetooth: hci0: BCM4362A2 'brcm/BCM4362A2.hcd' Patch
+ Bluetooth: hci0: BCM: features 0x0f
+ Bluetooth: hci0: BCM43752A2 UART 37.4MHz Ampak AP6398 sLNA iLNA CL1 [Version: 1091.1173]
+ Bluetooth: hci0: BCM4362A2 (000.017.017) build 1173
+
+Fixes: ab6fcb58aedf ("arm64: dts: rockchip: Add UART DMA support for RK3528")
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250709210831.3170458-1-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -611,7 +611,7 @@
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmac 8>, <&dmac 9>;
++ dmas = <&dmac 9>, <&dmac 8>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -623,7 +623,7 @@
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmac 10>, <&dmac 11>;
++ dmas = <&dmac 11>, <&dmac 10>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -635,7 +635,7 @@
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmac 12>, <&dmac 13>;
++ dmas = <&dmac 13>, <&dmac 12>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -647,7 +647,7 @@
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmac 14>, <&dmac 15>;
++ dmas = <&dmac 15>, <&dmac 14>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -659,7 +659,7 @@
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmac 16>, <&dmac 17>;
++ dmas = <&dmac 17>, <&dmac 16>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -671,7 +671,7 @@
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmac 18>, <&dmac 19>;
++ dmas = <&dmac 19>, <&dmac 18>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -683,7 +683,7 @@
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmac 20>, <&dmac 21>;
++ dmas = <&dmac 21>, <&dmac 20>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -695,7 +695,7 @@
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+- dmas = <&dmac 22>, <&dmac 23>;
++ dmas = <&dmac 23>, <&dmac 22>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
--- /dev/null
+From 1bce3444df79910512587a1f18022c396e9430b5 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Fri, 20 Jun 2025 22:17:15 +0200
+Subject: [PATCH] arm64: dts: rockchip: convert rk3528 power-domains to
+ dt-binding constants
+
+Now that the binding head has been merged, convert the power-domain ids
+back to these constants for easier handling.
+
+Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250620201715.1572609-1-heiko@sntech.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 23 ++++++++++++-----------
+ 1 file changed, 12 insertions(+), 11 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/clock/rockchip,rk3528-cru.h>
++#include <dt-bindings/power/rockchip,rk3528-power.h>
+ #include <dt-bindings/reset/rockchip,rk3528-cru.h>
+
+ / {
+@@ -496,8 +497,8 @@
+ #size-cells = <0>;
+
+ /* These power domains are grouped by VD_GPU */
+- power-domain@4 {
+- reg = <4>;
++ power-domain@RK3528_PD_GPU {
++ reg = <RK3528_PD_GPU>;
+ clocks = <&cru ACLK_GPU_MALI>,
+ <&cru PCLK_GPU_ROOT>;
+ pm_qos = <&qos_gpu_m0>,
+@@ -506,20 +507,20 @@
+ };
+
+ /* These power domains are grouped by VD_LOGIC */
+- power-domain@5 {
+- reg = <5>;
++ power-domain@RK3528_PD_RKVDEC {
++ reg = <RK3528_PD_RKVDEC>;
+ pm_qos = <&qos_rkvdec>;
+ #power-domain-cells = <0>;
+ status = "disabled";
+ };
+- power-domain@6 {
+- reg = <6>;
++ power-domain@RK3528_PD_RKVENC {
++ reg = <RK3528_PD_RKVENC>;
+ pm_qos = <&qos_rkvenc>;
+ #power-domain-cells = <0>;
+ status = "disabled";
+ };
+- power-domain@7 {
+- reg = <7>;
++ power-domain@RK3528_PD_VO {
++ reg = <RK3528_PD_VO>;
+ pm_qos = <&qos_gmac0>,
+ <&qos_hdcp>,
+ <&qos_jpegdec>,
+@@ -532,8 +533,8 @@
+ #power-domain-cells = <0>;
+ status = "disabled";
+ };
+- power-domain@8 {
+- reg = <8>;
++ power-domain@RK3528_PD_VPU {
++ reg = <RK3528_PD_VPU>;
+ pm_qos = <&qos_emmc>,
+ <&qos_fspi>,
+ <&qos_gmac1>,
+@@ -572,7 +573,7 @@
+ "pp1",
+ "ppmmu1";
+ operating-points-v2 = <&gpu_opp_table>;
+- power-domains = <&power 4>;
++ power-domains = <&power RK3528_PD_GPU>;
+ resets = <&cru SRST_A_GPU>;
+ status = "disabled";
+ };
--- /dev/null
+From 70bb21cbc8c704c664b5d3ea417f3e35376fc229 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Mon, 28 Jul 2025 10:29:48 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add naneng-combphy for RK3528
+
+Rockchip RK3528 ships a naneng-combphy that is shared by PCIe and USB
+3.0 controllers. Describe it and the pipe-phy grf which it depends on.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20250728102947.38984-8-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -433,6 +433,11 @@
+ reg = <0x0 0xff340000 0x0 0x8000>;
+ };
+
++ pipe_phy_grf: syscon@ff348000 {
++ compatible = "rockchip,rk3528-pipe-phy-grf", "syscon";
++ reg = <0x0 0xff348000 0x0 0x8000>;
++ };
++
+ vo_grf: syscon@ff360000 {
+ compatible = "rockchip,rk3528-vo-grf", "syscon";
+ reg = <0x0 0xff360000 0x0 0x10000>;
+@@ -1101,6 +1106,25 @@
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ };
++
++ combphy: phy@ffdc0000 {
++ compatible = "rockchip,rk3528-naneng-combphy";
++ reg = <0x0 0xffdc0000 0x0 0x10000>;
++ assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
++ assigned-clock-rates = <100000000>;
++ clocks = <&cru CLK_REF_PCIE_INNER_PHY>,
++ <&cru PCLK_PCIE_PHY>,
++ <&cru PCLK_PIPE_GRF>;
++ clock-names = "ref", "apb", "pipe";
++ power-domains = <&power RK3528_PD_VPU>;
++ resets = <&cru SRST_PCIE_PIPE_PHY>,
++ <&cru SRST_P_PCIE_PHY>;
++ reset-names = "phy", "apb";
++ #phy-cells = <1>;
++ rockchip,pipe-grf = <&vpu_grf>;
++ rockchip,pipe-phy-grf = <&pipe_phy_grf>;
++ status = "disabled";
++ };
+ };
+ };
+
--- /dev/null
+From 178879625f0f10ff708728087d91a5fe79990ce2 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Thu, 21 Aug 2025 21:18:41 +0000
+Subject: [PATCH] arm64: dts: rockchip: Enable more power domains for RK3528
+
+Describe device power-domains and enable the PD_RKVENC, PD_VO and PD_VPU
+power-domains on RK3528.
+
+The PD_RKVDEC is used by RKVDEC and DDRPHY CRU, and is kept disabled to
+prevent a full system reset trying to read the rate of the SCMI_CLK_DDR
+clock.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250821211843.3051349-2-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 30 +++++++++++++++++++++---
+ 1 file changed, 27 insertions(+), 3 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -171,6 +171,7 @@
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
++ power-domains = <&power RK3528_PD_VPU>;
+ };
+
+ gpio2: gpio@ffb00000 {
+@@ -183,6 +184,7 @@
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
++ power-domains = <&power RK3528_PD_VO>;
+ };
+
+ gpio3: gpio@ffb10000 {
+@@ -195,6 +197,7 @@
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
++ power-domains = <&power RK3528_PD_VPU>;
+ };
+
+ gpio4: gpio@ffb20000 {
+@@ -207,6 +210,7 @@
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
++ power-domains = <&power RK3528_PD_RKVENC>;
+ };
+ };
+
+@@ -522,7 +526,6 @@
+ reg = <RK3528_PD_RKVENC>;
+ pm_qos = <&qos_rkvenc>;
+ #power-domain-cells = <0>;
+- status = "disabled";
+ };
+ power-domain@RK3528_PD_VO {
+ reg = <RK3528_PD_VO>;
+@@ -536,7 +539,6 @@
+ <&qos_vdpp>,
+ <&qos_vop>;
+ #power-domain-cells = <0>;
+- status = "disabled";
+ };
+ power-domain@RK3528_PD_VPU {
+ reg = <RK3528_PD_VPU>;
+@@ -550,7 +552,6 @@
+ <&qos_usb3otg>,
+ <&qos_vpu>;
+ #power-domain-cells = <0>;
+- status = "disabled";
+ };
+ };
+ };
+@@ -592,6 +593,7 @@
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 25>, <&dmac 24>;
+ dma-names = "tx", "rx";
++ power-domains = <&power RK3528_PD_RKVENC>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+@@ -606,6 +608,7 @@
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 31>, <&dmac 30>;
+ dma-names = "tx", "rx";
++ power-domains = <&power RK3528_PD_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+@@ -630,6 +633,7 @@
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 11>, <&dmac 10>;
++ power-domains = <&power RK3528_PD_RKVENC>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -642,6 +646,7 @@
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 13>, <&dmac 12>;
++ power-domains = <&power RK3528_PD_VPU>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -654,6 +659,7 @@
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 15>, <&dmac 14>;
++ power-domains = <&power RK3528_PD_RKVENC>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -666,6 +672,7 @@
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 17>, <&dmac 16>;
++ power-domains = <&power RK3528_PD_VO>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -678,6 +685,7 @@
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 19>, <&dmac 18>;
++ power-domains = <&power RK3528_PD_VPU>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -690,6 +698,7 @@
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 21>, <&dmac 20>;
++ power-domains = <&power RK3528_PD_VPU>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -702,6 +711,7 @@
+ clock-names = "baudclk", "apb_pclk";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 23>, <&dmac 22>;
++ power-domains = <&power RK3528_PD_VPU>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+@@ -714,6 +724,7 @@
+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3528_PD_RKVENC>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+@@ -726,6 +737,7 @@
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3528_PD_RKVENC>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+@@ -752,6 +764,7 @@
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3528_PD_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+@@ -766,6 +779,7 @@
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_xfer>;
++ power-domains = <&power RK3528_PD_VO>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+@@ -778,6 +792,7 @@
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3528_PD_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+@@ -790,6 +805,7 @@
+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3528_PD_VPU>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+@@ -804,6 +820,7 @@
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_xfer>;
++ power-domains = <&power RK3528_PD_VO>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+@@ -895,6 +912,7 @@
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3528_PD_VPU>;
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ #io-channel-cells = <1>;
+@@ -915,6 +933,7 @@
+ interrupt-names = "macirq", "eth_wake_irq";
+ phy-handle = <&rmii0_phy>;
+ phy-mode = "rmii";
++ power-domains = <&power RK3528_PD_VO>;
+ resets = <&cru SRST_A_MAC_VO>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&vo_grf>;
+@@ -973,6 +992,7 @@
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
++ power-domains = <&power RK3528_PD_VPU>;
+ resets = <&cru SRST_A_MAC>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&vpu_grf>;
+@@ -1023,6 +1043,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
+ <&emmc_strb>;
++ power-domains = <&power RK3528_PD_VPU>;
+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+@@ -1044,6 +1065,7 @@
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;
++ power-domains = <&power RK3528_PD_VPU>;
+ resets = <&cru SRST_H_SDIO0>;
+ reset-names = "reset";
+ status = "disabled";
+@@ -1063,6 +1085,7 @@
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>;
++ power-domains = <&power RK3528_PD_VPU>;
+ resets = <&cru SRST_H_SDIO1>;
+ reset-names = "reset";
+ status = "disabled";
+@@ -1083,6 +1106,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
+ <&sdmmc_det>;
++ power-domains = <&power RK3528_PD_VO>;
+ resets = <&cru SRST_H_SDMMC0>;
+ reset-names = "reset";
+ rockchip,default-sample-phase = <90>;
--- /dev/null
+From 42bbc32c7e9e974ae4eb830ae1381cb016133e5c Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Fri, 1 Aug 2025 16:00:25 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add rk3528 CPU frequency scaling
+ support
+
+By default, the CPUs on RK3528 operates at 1.5GHz. Add CPU frequency and
+voltage mapping to the device tree to enable dynamic scaling via cpufreq.
+
+The OPP values come from downstream kernel[1], using a voltage close to
+the actual frequency. Frequencies below 1.2GHz have been removed due to
+the same voltage.
+
+[1] https://github.com/rockchip-linux/kernel/blob/develop-5.10/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20250801080025.558935-2-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 39 ++++++++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -70,6 +70,7 @@
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
++ operating-points-v2 = <&cpu_opp_table>;
+ };
+
+ cpu1: cpu@1 {
+@@ -78,6 +79,7 @@
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
++ operating-points-v2 = <&cpu_opp_table>;
+ };
+
+ cpu2: cpu@2 {
+@@ -86,6 +88,7 @@
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
++ operating-points-v2 = <&cpu_opp_table>;
+ };
+
+ cpu3: cpu@3 {
+@@ -94,6 +97,7 @@
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
++ operating-points-v2 = <&cpu_opp_table>;
+ };
+ };
+
+@@ -112,6 +116,41 @@
+ };
+ };
+
++ cpu_opp_table: opp-table-cpu {
++ compatible = "operating-points-v2";
++ opp-shared;
++
++ opp-1200000000 {
++ opp-hz = /bits/ 64 <1200000000>;
++ opp-microvolt = <875000 875000 1100000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1416000000 {
++ opp-hz = /bits/ 64 <1416000000>;
++ opp-microvolt = <925000 925000 1100000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1608000000 {
++ opp-hz = /bits/ 64 <1608000000>;
++ opp-microvolt = <975000 975000 1100000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-1800000000 {
++ opp-hz = /bits/ 64 <1800000000>;
++ opp-microvolt = <1037500 1037500 1100000>;
++ clock-latency-ns = <40000>;
++ };
++
++ opp-2016000000 {
++ opp-hz = /bits/ 64 <2016000000>;
++ opp-microvolt = <1100000 1100000 1100000>;
++ clock-latency-ns = <40000>;
++ };
++ };
++
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+
--- /dev/null
+From 263fac6b09b42a1b077c21354370d38758237ab0 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Thu, 18 Sep 2025 15:30:56 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add PCIe Gen2x1 controller for RK3528
+
+Describes the PCIe Gen2x1 controller integrated in RK3528 SoC. The SoC
+doesn't provide a separate MSI controller, thus the one integrated in
+designware PCIe IP must be used.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://patch.msgid.link/20250918153057.56023-3-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 56 +++++++++++++++++++++++++++++++-
+ 1 file changed, 55 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -7,6 +7,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/clock/rockchip,rk3528-cru.h>
+ #include <dt-bindings/power/rockchip,rk3528-power.h>
+@@ -294,10 +295,63 @@
+
+ soc {
+ compatible = "simple-bus";
+- ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
++ ranges = <0x0 0xfc000000 0x0 0xfc000000 0x0 0x44000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
++ pcie: pcie@fe000000 {
++ compatible = "rockchip,rk3528-pcie",
++ "rockchip,rk3568-pcie";
++ reg = <0x0 0xfe000000 0x0 0x400000>,
++ <0x0 0xfe4f0000 0x0 0x010000>,
++ <0x0 0xfc000000 0x0 0x100000>;
++ reg-names = "dbi", "apb", "config";
++ bus-range = <0x0 0xff>;
++ clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
++ <&cru HCLK_PCIE_DBI>, <&cru PCLK_PCIE>,
++ <&cru CLK_PCIE_AUX>;
++ clock-names = "aclk_mst", "aclk_slv",
++ "aclk_dbi", "pclk",
++ "aux";
++ device_type = "pci";
++ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "sys", "pmc", "msg", "legacy", "err",
++ "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 7>;
++ interrupt-map = <0 0 0 1 &pcie_intc 0>,
++ <0 0 0 2 &pcie_intc 1>,
++ <0 0 0 3 &pcie_intc 2>,
++ <0 0 0 4 &pcie_intc 3>;
++ linux,pci-domain = <0>;
++ max-link-speed = <2>;
++ num-lanes = <1>;
++ phys = <&combphy PHY_TYPE_PCIE>;
++ phy-names = "pcie-phy";
++ power-domains = <&power RK3528_PD_VPU>;
++ ranges = <0x01000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x00100000>,
++ <0x02000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x01e00000>,
++ <0x03000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
++ resets = <&cru SRST_PCIE_POWER_UP>, <&cru SRST_P_PCIE>;
++ reset-names = "pwr", "pipe";
++ #address-cells = <3>;
++ #size-cells = <2>;
++ status = "disabled";
++
++ pcie_intc: legacy-interrupt-controller {
++ interrupt-controller;
++ interrupt-parent = <&gic>;
++ interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
++ #address-cells = <0>;
++ #interrupt-cells = <1>;
++ };
++ };
++
+ gic: interrupt-controller@fed01000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xfed01000 0 0x1000>,
--- /dev/null
+From 05910d497f903ea44d794de7155d0a3eeceb60e9 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Thu, 29 Aug 2024 09:27:05 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add Radxa e20c board
+
+Add board-level device tree for Radxa e20c board[1]. This basic
+implementation supports boot into a kernel with only UART console.
+Other features will be added later.
+
+[1]: https://docs.radxa.com/en/e/e20c
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20240829092705.6241-5-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 22 +++++++++++++++++++
+ 2 files changed, 23 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -76,6 +76,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-d.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -0,0 +1,22 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (c) 2020 Rockchip Electronics Co., Ltd
++ * Copyright (c) 2024 Radxa Limited
++ * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
++ */
++
++/dts-v1/;
++#include "rk3528.dtsi"
++
++/ {
++ model = "Radxa E20C";
++ compatible = "radxa,e20c", "rockchip,rk3528";
++
++ chosen {
++ stdout-path = "serial0:1500000n8";
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
--- /dev/null
+From 0d2312f0d3e4ce74af0977c1519a07dfc71a82ac Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Fri, 28 Feb 2025 06:40:11 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C
+
+Radxa E20C route UART0 M0 pins (GPIO4_C7 and GPIO4_D0) to the onboard
+CH340B for debug console use.
+
+Add pinctrl for UART0 M0 pins used for serial console.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250228064024.3200000-6-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -18,5 +18,7 @@
+ };
+
+ &uart0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+ };
--- /dev/null
+From 6a709e003492e9878d5f1357be0b2e1162e1e6a6 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 4 Mar 2025 20:16:34 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add leds node to Radxa E20C
+
+Radxa E20C has three gpio controlled leds (sys, wan and lan).
+
+Add led nodes and set default trigger to heartbeat for the sys led and
+netdev for the lan and wan leds.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250304201642.831218-2-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 48 +++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -6,6 +6,8 @@
+ */
+
+ /dts-v1/;
++
++#include <dt-bindings/leds/common.h>
+ #include "rk3528.dtsi"
+
+ / {
+@@ -15,6 +17,52 @@
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&lan_led_g>, <&sys_led_g>, <&wan_led_g>;
++
++ led-lan {
++ color = <LED_COLOR_ID_GREEN>;
++ default-state = "off";
++ function = LED_FUNCTION_LAN;
++ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "netdev";
++ };
++
++ led-sys {
++ color = <LED_COLOR_ID_GREEN>;
++ default-state = "on";
++ function = LED_FUNCTION_HEARTBEAT;
++ gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "heartbeat";
++ };
++
++ led-wan {
++ color = <LED_COLOR_ID_GREEN>;
++ default-state = "off";
++ function = LED_FUNCTION_WAN;
++ gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "netdev";
++ };
++ };
++};
++
++&pinctrl {
++ leds {
++ lan_led_g: lan-led-g {
++ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ sys_led_g: sys-led-g {
++ rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ wan_led_g: wan-led-g {
++ rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
+ };
+
+ &uart0 {
--- /dev/null
+From ad8afc8813567994164f2720189c819da8c22b99 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 4 Mar 2025 20:16:35 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add user button to Radxa E20C
+
+Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
+button.
+
+Add support for the user button using a gpio-keys node.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250304201642.831218-3-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 20 +++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -7,6 +7,7 @@
+
+ /dts-v1/;
+
++#include <dt-bindings/input/input.h>
+ #include <dt-bindings/leds/common.h>
+ #include "rk3528.dtsi"
+
+@@ -18,6 +19,19 @@
+ stdout-path = "serial0:1500000n8";
+ };
+
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&user_key>;
++
++ button-user {
++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
++ label = "USER";
++ linux,code = <BTN_1>;
++ wakeup-source;
++ };
++ };
++
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+@@ -50,6 +64,12 @@
+ };
+
+ &pinctrl {
++ gpio-keys {
++ user_key: user-key {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
+ leds {
+ lan_led_g: lan-led-g {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
--- /dev/null
+From 3a2819ee9c71d1c6388e456cc4eb042914d15d7e Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 4 Mar 2025 20:16:37 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add maskrom button to Radxa E20C
+
+Radxa E20C has two buttons, one SARADC maskrom button and one GPIO user
+button.
+
+Add support for the maskrom button using a adc-keys node, also add the
+regulators used by SARADC controller.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250304201642.831218-5-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 48 +++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -19,6 +19,20 @@
+ stdout-path = "serial0:1500000n8";
+ };
+
++ adc-keys {
++ compatible = "adc-keys";
++ io-channels = <&saradc 0>;
++ io-channel-names = "buttons";
++ keyup-threshold-microvolt = <1800000>;
++ poll-interval = <100>;
++
++ button-maskrom {
++ label = "MASKROM";
++ linux,code = <KEY_SETUP>;
++ press-threshold-microvolt = <0>;
++ };
++ };
++
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+@@ -61,6 +75,35 @@
+ linux,default-trigger = "netdev";
+ };
+ };
++
++ vcc_1v8: regulator-1v8-vcc {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ vin-supply = <&vcc_3v3>;
++ };
++
++ vcc_3v3: regulator-3v3-vcc {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_3v3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc5v0_sys: regulator-5v0-vcc-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
+ };
+
+ &pinctrl {
+@@ -85,6 +128,11 @@
+ };
+ };
+
++&saradc {
++ vref-supply = <&vcc_1v8>;
++ status = "okay";
++};
++
+ &uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
--- /dev/null
+From 3a01b5f14a8ae2d45aea5aeed30001ac1655de86 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 5 Mar 2025 21:41:04 +0000
+Subject: [PATCH] arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C
+
+The Radxa E20C may come with an onboard eMMC (8GB / 16GB / 32GB / 64GB).
+
+Enable support for the onboard eMMC on Radxa E20C.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250305214108.1327208-4-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -15,6 +15,10 @@
+ model = "Radxa E20C";
+ compatible = "radxa,e20c", "rockchip,rk3528";
+
++ aliases {
++ mmc0 = &sdhci;
++ };
++
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+@@ -133,6 +137,17 @@
+ status = "okay";
+ };
+
++&sdhci {
++ bus-width = <8>;
++ cap-mmc-highspeed;
++ no-sd;
++ no-sdio;
++ non-removable;
++ vmmc-supply = <&vcc_3v3>;
++ vqmmc-supply = <&vcc_1v8>;
++ status = "okay";
++};
++
+ &uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
--- /dev/null
+From 101fe8b5627c68b3f2f941266e26ac355131e2fe Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Thu, 17 Apr 2025 12:01:19 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add onboard EEPROM for Radxa E20C
+
+Radxa E20C ships an onboard I2C EEPROM for storing production
+information. Enable it in devicetree.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250417120118.17610-6-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -110,6 +110,20 @@
+ };
+ };
+
++&i2c1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1m0_xfer>;
++ status = "okay";
++
++ eeprom@50 {
++ compatible = "belling,bl24c16a", "atmel,24c16";
++ reg = <0x50>;
++ pagesize = <16>;
++ read-only;
++ vcc-supply = <&vcc_3v3>;
++ };
++};
++
+ &pinctrl {
+ gpio-keys {
+ user_key: user-key {
--- /dev/null
+From c6599944af5a09029259ff8c533d22754f2b1ba4 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Tue, 1 Apr 2025 20:00:20 +0800
+Subject: [PATCH] arm64: dts: rockchip: Enable regulators for Radxa E20C
+
+Enable pwm and fixed regulators for Radxa E20C. The pwm regulator is
+used to power the CPU and GPU. Note that the LPDDR4 voltage is 1.1V.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250401120020.976343-3-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 73 +++++++++++++++++++
+ 1 file changed, 73 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -9,6 +9,7 @@
+
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/leds/common.h>
++#include <dt-bindings/pwm/pwm.h>
+ #include "rk3528.dtsi"
+
+ / {
+@@ -80,6 +81,26 @@
+ };
+ };
+
++ vdd_0v9: regulator-0v9-vdd {
++ compatible = "regulator-fixed";
++ regulator-name = "vdd_0v9";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc_ddr: regulator-1v1-vcc-ddr {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
+ vcc_1v8: regulator-1v8-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8";
+@@ -108,6 +129,46 @@
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
++
++ vdd_arm: regulator-vdd-arm {
++ compatible = "pwm-regulator";
++ pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
++ pwm-supply = <&vcc5v0_sys>;
++ regulator-name = "vdd_arm";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <746000>;
++ regulator-max-microvolt = <1201000>;
++ regulator-settling-time-up-us = <250>;
++ };
++
++ vdd_logic: regulator-vdd-logic {
++ compatible = "pwm-regulator";
++ pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
++ pwm-supply = <&vcc5v0_sys>;
++ regulator-name = "vdd_logic";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <705000>;
++ regulator-max-microvolt = <1006000>;
++ regulator-settling-time-up-us = <250>;
++ };
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_arm>;
+ };
+
+ &i2c1 {
+@@ -146,6 +207,18 @@
+ };
+ };
+
++&pwm1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm1m0_pins>;
++ status = "okay";
++};
++
++&pwm2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm2m0_pins>;
++ status = "okay";
++};
++
+ &saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
--- /dev/null
+From a2130d9123b23d74a717f52240fa3cb92bf8113c Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Thu, 8 May 2025 23:48:30 +0000
+Subject: [PATCH] arm64: dts: rockchip: Enable SD-card interface on Radxa E20C
+
+SD-card is available on Radxa E20C board.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250508234829.27111-4-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 30 +++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -18,6 +18,7 @@
+
+ aliases {
+ mmc0 = &sdhci;
++ mmc1 = &sdmmc;
+ };
+
+ chosen {
+@@ -130,6 +131,18 @@
+ regulator-max-microvolt = <5000000>;
+ };
+
++ vccio_sd: regulator-vccio-sd {
++ compatible = "regulator-gpio";
++ gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc_vol_ctrl_h>;
++ regulator-name = "vccio_sd";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ states = <1800000 0x0>, <3300000 0x1>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
+ vdd_arm: regulator-vdd-arm {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
+@@ -205,6 +218,12 @@
+ rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
++
++ sdmmc {
++ sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h {
++ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
+ };
+
+ &pwm1 {
+@@ -235,6 +254,17 @@
+ status = "okay";
+ };
+
++&sdmmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3>;
++ vqmmc-supply = <&vccio_sd>;
++ status = "okay";
++};
++
+ &uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0m0_xfer>;
--- /dev/null
+From 10b9ef4a514b25dea6eac24f25e3027866526800 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Fri, 9 May 2025 20:23:58 +0000
+Subject: [PATCH] arm64: dts: rockchip: Enable Ethernet controller on Radxa
+ E20C
+
+The Radxa E20C has two GbE ports, LAN and WAN. The LAN port is provided
+using a GMAC controller and a YT8531C PHY and the WAN port is provided
+by an RTL8111H PCIe Ethernet controller.
+
+Enable support for the LAN port on Radxa E20C.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Tested-by: Yao Zi <ziyao@disroot.org>
+Link: https://lore.kernel.org/r/20250509202402.260038-3-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 30 +++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -17,6 +17,7 @@
+ compatible = "radxa,e20c", "rockchip,rk3528";
+
+ aliases {
++ ethernet0 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+@@ -184,6 +185,17 @@
+ cpu-supply = <&vdd_arm>;
+ };
+
++&gmac1 {
++ clock_in_out = "output";
++ phy-handle = <&rgmii_phy>;
++ phy-mode = "rgmii-id";
++ phy-supply = <&vcc_3v3>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>,
++ <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>;
++ status = "okay";
++};
++
+ &i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m0_xfer>;
+@@ -198,7 +210,25 @@
+ };
+ };
+
++&mdio1 {
++ rgmii_phy: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0x1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac1_rstn_l>;
++ reset-assert-us = <20000>;
++ reset-deassert-us = <100000>;
++ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
++ };
++};
++
+ &pinctrl {
++ ethernet {
++ gmac1_rstn_l: gmac1-rstn-l {
++ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ gpio-keys {
+ user_key: user-key {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
--- /dev/null
+From 34d2730fbbddfdffd656d36a13f8fdb886a3b5e1 Mon Sep 17 00:00:00 2001
+From: Heiko Stuebner <heiko@sntech.de>
+Date: Sun, 11 May 2025 00:01:06 +0200
+Subject: [PATCH] arm64: dts: rockchip: move rk3528 i2c+uart aliases to board
+ files
+
+Even though they will be the same for all boards, i2c and uart aliases
+are supposed to live in the individual board files, to not create
+aliases for disabled nodes.
+
+So move the newly added aliases for rk3528 over to the Radxa E20C board,
+which is the only rk3528 board right now.
+
+Fixes: d3a05f490d04 ("arm64: dts: rockchip: Add I2C controllers for RK3528")
+Suggested-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Yao Zi <ziyao@disroot.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20250510220106.2108414-1-heiko@sntech.de
+---
+ .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 2 ++
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 16 ----------------
+ 2 files changed, 2 insertions(+), 16 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -18,8 +18,10 @@
+
+ aliases {
+ ethernet0 = &gmac1;
++ i2c1 = &i2c1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
++ serial0 = &uart0;
+ };
+
+ chosen {
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -26,22 +26,6 @@
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+- i2c0 = &i2c0;
+- i2c1 = &i2c1;
+- i2c2 = &i2c2;
+- i2c3 = &i2c3;
+- i2c4 = &i2c4;
+- i2c5 = &i2c5;
+- i2c6 = &i2c6;
+- i2c7 = &i2c7;
+- serial0 = &uart0;
+- serial1 = &uart1;
+- serial2 = &uart2;
+- serial3 = &uart3;
+- serial4 = &uart4;
+- serial5 = &uart5;
+- serial6 = &uart6;
+- serial7 = &uart7;
+ };
+
+ cpus {
--- /dev/null
+From f4db84780427270dd20ec0e7079b0ae26dc88dd3 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 18 May 2025 22:54:13 +0000
+Subject: [PATCH] arm64: dts: rockchip: Enable GPU on Radxa E20C
+
+Enable the Mali-450 MP2 GPU on the Radxa E20C.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250518225418.682182-4-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -198,6 +198,11 @@
+ status = "okay";
+ };
+
++&gpu {
++ mali-supply = <&vdd_logic>;
++ status = "okay";
++};
++
+ &i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m0_xfer>;
--- /dev/null
+From 6e3071f4e03997ca0e4388ca61aa06df2802dcd1 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sat, 21 Jun 2025 16:58:30 +0000
+Subject: [PATCH] arm64: dts: rockchip: Enable eMMC HS200 mode on Radxa E20C
+
+eMMC HS200 mode (1.8V I/O) is supported by the MMC host controller on
+RK3528 and works with the optional on-board eMMC module on Radxa E20C.
+
+Be explicit about HS200 support in the device tree for Radxa E20C.
+
+Fixes: 3a01b5f14a8a ("arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C")
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20250621165832.2226160-1-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -283,6 +283,7 @@
+ &sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
++ mmc-hs200-1_8v;
+ no-sd;
+ no-sdio;
+ non-removable;
--- /dev/null
+From 047bac0be317e68b89d0deed4f659f8e080df6e8 Mon Sep 17 00:00:00 2001
+From: Yao Zi <ziyao@disroot.org>
+Date: Thu, 18 Sep 2025 15:30:57 +0000
+Subject: [PATCH] arm64: dts: rockchip: Enable PCIe controller on Radxa E20C
+
+Radxa E20C provides one of its GbE ports through RTL8111H connected to
+SoC's PCIe controller. Let's enable the controller and the PHY used by
+it to allow usage of the port.
+
+Signed-off-by: Yao Zi <ziyao@disroot.org>
+Link: https://patch.msgid.link/20250918153057.56023-4-ziyao@disroot.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -171,6 +171,10 @@
+ };
+ };
+
++&combphy {
++ status = "okay";
++};
++
+ &cpu0 {
+ cpu-supply = <&vdd_arm>;
+ };
+@@ -229,6 +233,14 @@
+ };
+ };
+
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pciem1_pins>;
++ reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3>;
++ status = "okay";
++};
++
+ &pinctrl {
+ ethernet {
+ gmac1_rstn_l: gmac1-rstn-l {
--- /dev/null
+From 5b71b3d9aa61626d6a93ed2f761a748aa2ecfa95 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Thu, 17 Jul 2025 10:37:04 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add Radxa ROCK 2A/2F
+
+The ROCK 2A and ROCK 2F is a high-performance single board computer
+developed by Radxa, based on the Rockchip RK3528A SoC.
+
+Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Tested-by: Yao Zi <ziyao@disroot.org>
+Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
+Link: https://lore.kernel.org/r/20250717103720.2853031-3-jonas@kwiboo.se
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 2 +
+ .../boot/dts/rockchip/rk3528-rock-2.dtsi | 293 ++++++++++++++++++
+ .../boot/dts/rockchip/rk3528-rock-2a.dts | 82 +++++
+ .../boot/dts/rockchip/rk3528-rock-2f.dts | 10 +
+ 4 files changed, 387 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -77,6 +77,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2a.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2f.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-d.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg-arc-s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
+@@ -0,0 +1,293 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pwm/pwm.h>
++#include "rk3528.dtsi"
++
++/ {
++ aliases {
++ i2c1 = &i2c1;
++ mmc0 = &sdhci;
++ mmc1 = &sdmmc;
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:1500000n8";
++ };
++
++ adc-keys {
++ compatible = "adc-keys";
++ io-channels = <&saradc 0>;
++ io-channel-names = "buttons";
++ keyup-threshold-microvolt = <1800000>;
++ poll-interval = <100>;
++
++ button-maskrom {
++ label = "MASKROM";
++ linux,code = <KEY_SETUP>;
++ press-threshold-microvolt = <0>;
++ };
++ };
++
++ leds: leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&state_led_b>;
++
++ led-0 {
++ color = <LED_COLOR_ID_BLUE>;
++ default-state = "on";
++ function = LED_FUNCTION_HEARTBEAT;
++ gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ vdd_0v9: regulator-0v9-vdd {
++ compatible = "regulator-fixed";
++ regulator-name = "vdd_0v9";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc_ddr: regulator-1v1-vcc-ddr {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc_1v8: regulator-1v8-vcc {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ vin-supply = <&vcc_3v3>;
++ };
++
++ vcc_3v3: regulator-3v3-vcc {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_3v3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc_wifi: regulator-3v3-vcc-wifi {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_wifi_pwr>;
++ regulator-name = "vcc_wifi";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_3v3>;
++ };
++
++ vcc5v0_sys: regulator-5v0-vcc-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vcc5v0_usb20: regulator-5v0-vcc-usb20 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_host_en>;
++ regulator-name = "vcc5v0_usb20";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vccio_sd: regulator-vccio-sd {
++ compatible = "regulator-gpio";
++ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc_vol_ctrl_h>;
++ regulator-name = "vccio_sd";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ states = <1800000 0x0>, <3300000 0x1>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vdd_arm: regulator-vdd-arm {
++ compatible = "pwm-regulator";
++ pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
++ pwm-supply = <&vcc5v0_sys>;
++ regulator-name = "vdd_arm";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <746000>;
++ regulator-max-microvolt = <1201000>;
++ regulator-settling-time-up-us = <250>;
++ };
++
++ vdd_logic: regulator-vdd-logic {
++ compatible = "pwm-regulator";
++ pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
++ pwm-supply = <&vcc5v0_sys>;
++ regulator-name = "vdd_logic";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <705000>;
++ regulator-max-microvolt = <1006000>;
++ regulator-settling-time-up-us = <250>;
++ };
++
++ rfkill {
++ compatible = "rfkill-gpio";
++ label = "rfkill-wlan";
++ pinctrl-names = "default";
++ pinctrl-0 = <&wifi_reg_on_h>;
++ radio-type = "wlan";
++ shutdown-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
++ };
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&gpu {
++ mali-supply = <&vdd_logic>;
++ status = "okay";
++};
++
++&i2c1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c1m0_xfer>;
++ status = "okay";
++
++ eeprom@50 {
++ compatible = "belling,bl24c16a", "atmel,24c16";
++ reg = <0x50>;
++ pagesize = <16>;
++ read-only;
++ vcc-supply = <&vcc_3v3>;
++ };
++};
++
++&pinctrl {
++ bluetooth {
++ bt_wake_host_h: bt-wake-host-h {
++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++
++ host_wake_bt_h: host-wake-bt-h {
++ rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ leds {
++ state_led_b: state-led-b {
++ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ sdmmc {
++ sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h {
++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ usb {
++ usb_host_en: usb-host-en {
++ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ wifi {
++ usb_wifi_pwr: usb-wifi-pwr {
++ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ wifi_reg_on_h: wifi-reg-on-h {
++ rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ wifi_wake_host_h: wifi-wake-host-h {
++ rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++ };
++};
++
++&pwm1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm1m0_pins>;
++ status = "okay";
++};
++
++&pwm2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm2m0_pins>;
++ status = "okay";
++};
++
++&saradc {
++ vref-supply = <&vcc_1v8>;
++ status = "okay";
++};
++
++&sdhci {
++ bus-width = <8>;
++ cap-mmc-highspeed;
++ mmc-hs200-1_8v;
++ no-sd;
++ no-sdio;
++ non-removable;
++ vmmc-supply = <&vcc_3v3>;
++ vqmmc-supply = <&vcc_1v8>;
++ status = "okay";
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ max-frequency = <100000000>;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3>;
++ vqmmc-supply = <&vccio_sd>;
++ status = "okay";
++};
++
++&uart0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0m0_xfer>;
++ status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk3528-rock-2.dtsi"
++
++/ {
++ model = "Radxa ROCK 2A";
++ compatible = "radxa,rock-2a", "rockchip,rk3528";
++
++ aliases {
++ ethernet0 = &gmac1;
++ };
++
++ vcc5v0_usb30_otg: regulator-5v0-vcc-usb30-otg {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_otg_en>;
++ regulator-name = "vcc5v0_usb30_otg";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++};
++
++&gmac1 {
++ clock_in_out = "output";
++ phy-handle = <&rgmii_phy>;
++ phy-mode = "rgmii-id";
++ phy-supply = <&vcc_3v3>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>,
++ <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>;
++ status = "okay";
++};
++
++&leds {
++ pinctrl-names = "default";
++ pinctrl-0 = <&state_led_b>, <&sys_led_g>;
++
++ led-1 {
++ color = <LED_COLOR_ID_GREEN>;
++ default-state = "on";
++ function = LED_FUNCTION_STATUS;
++ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-on";
++ };
++};
++
++&mdio1 {
++ rgmii_phy: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0x1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac1_rstn_l>;
++ reset-assert-us = <20000>;
++ reset-deassert-us = <100000>;
++ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
++ };
++};
++
++&pinctrl {
++ ethernet {
++ gmac1_rstn_l: gmac1-rstn-l {
++ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ leds {
++ sys_led_g: sys-led-g {
++ rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ usb {
++ usb_otg_en: usb-otg-en {
++ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts
+@@ -0,0 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk3528-rock-2.dtsi"
++
++/ {
++ model = "Radxa ROCK 2F";
++ compatible = "radxa,rock-2f", "rockchip,rk3528";
++};
--- /dev/null
+From 86a504b82f8d0e34f99ab9607712e7942c919fa3 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Mon, 18 Aug 2025 18:00:08 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add HINLINK H68K
+
+The HINLINK H68K is a development board with the
+Rockchip RK3568 SoC. It has the following features:
+
+- 2/4GB LPDDR4
+- 1x HDMI Type A
+- 3.5mm jack with mic
+- 1x PCIE 2.0 WiFi slot
+- 1x USB 3.0, 2x USB 2.0
+- 2x 1GbE RTL8211F Ethernet
+- 2x 2.5GbE RTL8125B Ethernet
+- MicroSD card slot / eMMC 32GB
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20250818100009.170202-4-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../boot/dts/rockchip/rk3568-hinlink-h68k.dts | 83 +++
+ .../boot/dts/rockchip/rk3568-hinlink-opc.dtsi | 666 ++++++++++++++++++
+ 3 files changed, 750 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -116,6 +116,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ea
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mecsbc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h68k.dts
+@@ -0,0 +1,83 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk3568-hinlink-opc.dtsi"
++
++/ {
++ model = "HINLINK H68K";
++ compatible = "hinlink,h68k", "rockchip,rk3568";
++
++ aliases {
++ ethernet0 = &gmac0;
++ ethernet1 = &gmac1;
++ };
++};
++
++&gmac0 {
++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
++ assigned-clock-rates = <0>, <125000000>;
++ clock_in_out = "output";
++ phy-handle = <&rgmii_phy0>;
++ phy-mode = "rgmii-id";
++ phy-supply = <&vcc3v3_sys>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac0_miim
++ &gmac0_tx_bus2
++ &gmac0_rx_bus2
++ &gmac0_rgmii_clk
++ &gmac0_rgmii_bus
++ &gmac0_rstn>;
++ status = "okay";
++};
++
++&gmac1 {
++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
++ assigned-clock-rates = <0>, <125000000>;
++ clock_in_out = "output";
++ phy-handle = <&rgmii_phy1>;
++ phy-mode = "rgmii-id";
++ phy-supply = <&vcc3v3_sys>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac1m1_miim
++ &gmac1m1_tx_bus2
++ &gmac1m1_rx_bus2
++ &gmac1m1_rgmii_clk
++ &gmac1m1_rgmii_bus
++ &gmac1_rstn>;
++ status = "okay";
++};
++
++&mdio0 {
++ rgmii_phy0: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0x1>;
++ reset-assert-us = <20000>;
++ reset-deassert-us = <100000>;
++ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
++ };
++};
++
++&mdio1 {
++ rgmii_phy1: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0x1>;
++ reset-assert-us = <20000>;
++ reset-deassert-us = <100000>;
++ reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
++ };
++};
++
++&pinctrl {
++ gmac {
++ gmac0_rstn: gmac0-rstn {
++ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ gmac1_rstn: gmac1-rstn {
++ rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi
+@@ -0,0 +1,666 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3568.dtsi"
++
++/ {
++ aliases {
++ mmc0 = &sdhci;
++ mmc1 = &sdmmc0;
++ };
++
++ chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ hdmi-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
++ ir-receiver {
++ compatible = "gpio-ir-receiver";
++ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm3_ir_m0>;
++ };
++
++ keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&factory>;
++
++ button-factory {
++ label = "factory";
++ linux,code = <KEY_RESTART>;
++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
++ debounce-interval = <50>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&green_led>, <&red_led>, <&work_led>;
++
++ led-0 {
++ color = <LED_COLOR_ID_BLUE>;
++ function = LED_FUNCTION_WAN;
++ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "netdev";
++ };
++
++ led-1 {
++ color = <LED_COLOR_ID_AMBER>;
++ function = LED_FUNCTION_DISK;
++ gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
++ };
++
++ led-2 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_STATUS;
++ gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "default-on";
++ };
++ };
++
++ vcc0v9_2g5: regulator-0v9-vcc-2g5 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc0v9_2g5";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc12v_dcinp: regulator-12v-vcc-dcinp {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc12v_dcinp";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <12000000>;
++ regulator-max-microvolt = <12000000>;
++ };
++
++ vcc3v3_pi6c_05: regulator-3v3-vcc-pi6c-05 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&lan_power_en>;
++ regulator-name = "vcc3v3_pi6c_05";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc3v3_sd: regulator-3v3-vcc-sd {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sd_pwren>;
++ regulator-name = "vcc3v3_sd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ vcc3v3_sys: regulator-3v3-vcc-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc5v0_sys: regulator-5v0-vcc-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc12v_dcinp>;
++ };
++
++ vcc5v0_usb30_otg0: regulator-5v0-vcc-usb30-otg0 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_power_en>;
++ regulator-name = "vcc5v0_usb30_otg0";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++};
++
++&combphy0 {
++ status = "okay";
++};
++
++&combphy1 {
++ status = "okay";
++};
++
++&combphy2 {
++ status = "okay";
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_cpu>;
++};
++
++&gpu {
++ mali-supply = <&vdd_gpu>;
++ status = "okay";
++};
++
++&hdmi {
++ avdd-0v9-supply = <&vdda0v9_image>;
++ avdd-1v8-supply = <&vcca1v8_image>;
++ status = "okay";
++};
++
++&hdmi_in {
++ hdmi_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi>;
++ };
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
++&hdmi_sound {
++ status = "okay";
++};
++
++&i2c0 {
++ status = "okay";
++
++ vdd_cpu: regulator@1c {
++ compatible = "tcs,tcs4525";
++ reg = <0x1c>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <800000>;
++ regulator-max-microvolt = <1150000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ rk809: pmic@20 {
++ compatible = "rockchip,rk809";
++ reg = <0x20>;
++ #clock-cells = <1>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_int>;
++ system-power-controller;
++ wakeup-source;
++
++ vcc1-supply = <&vcc3v3_sys>;
++ vcc2-supply = <&vcc3v3_sys>;
++ vcc3-supply = <&vcc3v3_sys>;
++ vcc4-supply = <&vcc3v3_sys>;
++ vcc5-supply = <&vcc3v3_sys>;
++ vcc6-supply = <&vcc3v3_sys>;
++ vcc7-supply = <&vcc3v3_sys>;
++ vcc8-supply = <&vcc3v3_sys>;
++ vcc9-supply = <&vcc3v3_sys>;
++
++ regulators {
++ vdd_logic: DCDC_REG1 {
++ regulator-name = "vdd_logic";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_gpu: DCDC_REG2 {
++ regulator-name = "vdd_gpu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-initial-mode = <0x2>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vdd_npu: DCDC_REG4 {
++ regulator-name = "vdd_npu";
++ regulator-initial-mode = <0x2>;
++ regulator-min-microvolt = <500000>;
++ regulator-max-microvolt = <1350000>;
++ regulator-ramp-delay = <6001>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8: DCDC_REG5 {
++ regulator-name = "vcc_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda0v9_image: LDO_REG1 {
++ regulator-name = "vdda0v9_image";
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda_0v9: LDO_REG2 {
++ regulator-name = "vdda_0v9";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdda0v9_pmu: LDO_REG3 {
++ regulator-name = "vdda0v9_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <900000>;
++ };
++ };
++
++ vccio_acodec: LDO_REG4 {
++ regulator-name = "vccio_acodec";
++ regulator-always-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vccio_sd: LDO_REG5 {
++ regulator-name = "vccio_sd";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc3v3_pmu: LDO_REG6 {
++ regulator-name = "vcc3v3_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcca_1v8: LDO_REG7 {
++ regulator-name = "vcca_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcca1v8_pmu: LDO_REG8 {
++ regulator-name = "vcca1v8_pmu";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcca1v8_image: LDO_REG9 {
++ regulator-name = "vcca1v8_image";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_3v3: SWITCH_REG1 {
++ regulator-name = "vcc_3v3";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc3v3: SWITCH_REG2 {
++ regulator-name = "vcc3v3";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++&i2c2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c2m1_xfer>;
++ status = "okay";
++};
++
++&i2s0_8ch {
++ status = "okay";
++};
++
++&pcie2x1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&wifi_perstn>;
++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
++ status = "okay";
++};
++
++&pcie30phy {
++ data-lanes = <1 2>;
++ status = "okay";
++};
++
++&pcie3x1 {
++ num-lanes = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&lan_resetb>;
++ reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
++ status = "okay";
++};
++
++&pcie3x2 {
++ num-lanes = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&lan_reseta>;
++ reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
++ status = "okay";
++};
++
++&pinctrl {
++ keys {
++ factory: factory {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ leds {
++ green_led: green-led {
++ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ red_led: red-led {
++ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ work_led: work-led {
++ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ ir {
++ pwm3_ir_m0: pwm3-ir-m0 {
++ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ mmc {
++ sd_pwren: sd-pwren {
++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie {
++ lan_power_en: lan-power-en {
++ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ lan_reseta: lan-reseta {
++ rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ lan_resetb: lan-resetb {
++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ wifi_perstn: wifi-perstn {
++ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pmic {
++ pmic_int: pmic-int {
++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ usb {
++ usb_power_en: usb-power-en {
++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&pmu_io_domains {
++ pmuio1-supply = <&vcc3v3_pmu>;
++ pmuio2-supply = <&vcc3v3_pmu>;
++ vccio1-supply = <&vccio_acodec>;
++ vccio2-supply = <&vcc_1v8>;
++ vccio3-supply = <&vccio_sd>;
++ vccio4-supply = <&vcc_1v8>;
++ vccio5-supply = <&vcc_3v3>;
++ vccio6-supply = <&vcc_1v8>;
++ vccio7-supply = <&vcc_3v3>;
++ status = "okay";
++};
++
++&pwm0 {
++ status = "okay";
++};
++
++&saradc {
++ vref-supply = <&vcca_1v8>;
++ status = "okay";
++};
++
++/* Via Type-C adapter */
++&sata0 {
++ status = "okay";
++};
++
++&sdhci {
++ bus-width = <8>;
++ cap-mmc-highspeed;
++ max-frequency = <200000000>;
++ mmc-hs200-1_8v;
++ non-removable;
++ pinctrl-names = "default";
++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
++ vmmc-supply = <&vcc_3v3>;
++ vqmmc-supply = <&vcc_1v8>;
++ status = "okay";
++};
++
++&sdmmc0 {
++ bus-width = <4>;
++ cap-sd-highspeed;
++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
++ disable-wp;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++ sd-uhs-sdr50;
++ vmmc-supply = <&vcc3v3_sd>;
++ vqmmc-supply = <&vccio_sd>;
++ status = "okay";
++};
++
++&tsadc {
++ rockchip,hw-tshut-mode = <1>;
++ rockchip,hw-tshut-polarity = <0>;
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
++
++&usb_host1_ehci {
++ status = "okay";
++};
++
++&usb_host1_ohci {
++ status = "okay";
++};
++
++&usb_host1_xhci {
++ status = "okay";
++};
++
++&usb2phy0 {
++ status = "okay";
++};
++
++&usb2phy0_host {
++ phy-supply = <&vcc5v0_usb30_otg0>;
++ status = "okay";
++};
++
++&usb2phy1 {
++ status = "okay";
++};
++
++&usb2phy1_host {
++ phy-supply = <&vcc5v0_usb30_otg0>;
++ status = "okay";
++};
++
++&usb2phy1_otg {
++ phy-supply = <&vcc5v0_usb30_otg0>;
++ status = "okay";
++};
++
++&vop {
++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi_in_vp0>;
++ };
++};
--- /dev/null
+From bb9ef44f05c9558d58e3c9da141e93af1aa11c1f Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Mon, 18 Aug 2025 18:00:09 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add HINLINK H66K
+
+The HINLINK H66K is a development board with the
+Rockchip RK3568 SoC. It has the following features:
+
+- 2/4GB LPDDR4
+- 1x HDMI Type A
+- 3.5mm jack with mic
+- 1x PCIE 2.0 WiFi slot
+- 1x USB 3.0, 2x USB 2.0
+- 2x 2.5GbE RTL8125B Ethernet
+- MicroSD card slot / eMMC 32GB
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20250818100009.170202-5-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts | 10 ++++++++++
+ 2 files changed, 11 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -116,6 +116,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ea
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h66k.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-hinlink-h68k.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mecsbc.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-h66k.dts
+@@ -0,0 +1,10 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk3568-hinlink-opc.dtsi"
++
++/ {
++ model = "HINLINK H66K";
++ compatible = "hinlink,h66k", "rockchip,rk3568";
++};
--- /dev/null
+From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Fri, 10 Jul 2020 21:38:20 +0200
+Subject: [PATCH] rockchip: use system LED for OpenWrt
+
+Use the SYS LED on the casing for showing system status.
+
+This patch is kept separate from the NanoPi R2S support patch, as i plan
+on submitting the device support upstream.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -6,6 +6,7 @@
+ /dts-v1/;
+
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include "rk3328.dtsi"
+
+@@ -17,6 +18,11 @@
+ ethernet0 = &gmac2io;
+ ethernet1 = &rtl8153;
+ mmc0 = &sdmmc;
++
++ led-boot = &sys_led;
++ led-failsafe = &sys_led;
++ led-running = &sys_led;
++ led-upgrade = &sys_led;
+ };
+
+ chosen {
+@@ -49,19 +55,22 @@
+ pinctrl-names = "default";
+
+ lan_led: led-0 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_LAN;
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+- label = "nanopi-r2s:green:lan";
+ };
+
+ sys_led: led-1 {
++ color = <LED_COLOR_ID_RED>;
++ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+- label = "nanopi-r2s:red:sys";
+ default-state = "on";
+ };
+
+ wan_led: led-2 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_WAN;
+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
+- label = "nanopi-r2s:green:wan";
+ };
+ };
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -14,6 +14,11 @@
+ ethernet0 = &gmac2io;
+ mmc0 = &sdmmc;
+ mmc1 = &emmc;
++
++ led-boot = &power_led;
++ led-failsafe = &power_led;
++ led-running = &power_led;
++ led-upgrade = &power_led;
+ };
+
+ chosen {
--- /dev/null
+From dca5896703826d0d5fadcc11ee755b83db705571 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Mon, 1 Dec 2025 18:00:06 +0800
+Subject: [PATCH] arm64: dts: rockchip: Add HINLINK H28K
+
+The HINLINK H28K is a development board with the
+Rockchip RK3528 SoC. It has the following features:
+
+- 1x USB 2.0
+- 8/32GB eMMC
+- 1/2/4GB LPDDR4
+- MicroSD card slot
+- 1x 1GbE RTL8111H Ethernet
+- 1x 1GbE RTL8211F Ethernet
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../boot/dts/rockchip/rk3528-hinlink-h28k.dts | 301 ++++++++++++++++++
+ 2 files changed, 302 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -76,6 +76,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-hinlink-h28k.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-radxa-e20c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-rock-2f.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts
+@@ -0,0 +1,318 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pwm/pwm.h>
++#include "rk3528.dtsi"
++
++/ {
++ model = "HINLINK H28K";
++ compatible = "hinlink,h28k", "rockchip,rk3528";
++
++ aliases {
++ ethernet0 = &gmac1;
++ mmc0 = &sdhci;
++ mmc1 = &sdmmc;
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:1500000n8";
++ };
++
++ keys {
++ compatible = "adc-keys";
++ io-channels = <&saradc 0>;
++ io-channel-names = "buttons";
++ keyup-threshold-microvolt = <1800000>;
++ poll-interval = <100>;
++
++ button-boot {
++ label = "BOOT";
++ linux,code = <KEY_SETUP>;
++ press-threshold-microvolt = <0>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&lan_led>, <&wan_led>, <&work_led>;
++
++ led-0 {
++ color = <LED_COLOR_ID_AMBER>;
++ function = LED_FUNCTION_LAN;
++ gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "netdev";
++ };
++
++ led-1 {
++ color = <LED_COLOR_ID_BLUE>;
++ function = LED_FUNCTION_WAN;
++ gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "netdev";
++ };
++
++ led-2 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_STATUS;
++ gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_LOW>;
++ linux,default-trigger = "default-on";
++ };
++ };
++
++ vdd_0v9: regulator-0v9-vdd {
++ compatible = "regulator-fixed";
++ regulator-name = "vdd_0v9";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <900000>;
++ regulator-max-microvolt = <900000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc_ddr: regulator-1v1-vcc-ddr {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc_1v8: regulator-1v8-vcc {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_1v8";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ vin-supply = <&vcc_3v3>;
++ };
++
++ vcc_3v3: regulator-3v3-vcc {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_3v3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc3v3_sd: regulator-3v3-vcc-sd {
++ compatible = "regulator-fixed";
++ gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc_pwren_l>;
++ regulator-name = "vcc3v3_sd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_3v3>;
++ };
++
++ vcc5v0_sys: regulator-5v0-vcc-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vccio_sd: regulator-vccio-sd {
++ compatible = "regulator-gpio";
++ gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc_vol_ctrl_h>;
++ regulator-name = "vccio_sd";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ states = <1800000 0x0>, <3300000 0x1>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vdd_arm: regulator-vdd-arm {
++ compatible = "pwm-regulator";
++ pwms = <&pwm1 0 5000 PWM_POLARITY_INVERTED>;
++ pwm-supply = <&vcc5v0_sys>;
++ regulator-name = "vdd_arm";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <746000>;
++ regulator-max-microvolt = <1201000>;
++ regulator-settling-time-up-us = <250>;
++ };
++
++ vdd_logic: regulator-vdd-logic {
++ compatible = "pwm-regulator";
++ pwms = <&pwm2 0 5000 PWM_POLARITY_INVERTED>;
++ pwm-supply = <&vcc5v0_sys>;
++ regulator-name = "vdd_logic";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <705000>;
++ regulator-max-microvolt = <1006000>;
++ regulator-settling-time-up-us = <250>;
++ };
++};
++
++&combphy {
++ status = "okay";
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&gmac1 {
++ clock_in_out = "output";
++ phy-handle = <&rgmii_phy>;
++ phy-mode = "rgmii-id";
++ phy-supply = <&vcc_3v3>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rgmii_miim>,
++ <&rgmii_tx_bus2>,
++ <&rgmii_rx_bus2>,
++ <&rgmii_rgmii_clk>,
++ <&rgmii_rgmii_bus>;
++ status = "okay";
++};
++
++&gpu {
++ mali-supply = <&vdd_logic>;
++ status = "okay";
++};
++
++&mdio1 {
++ rgmii_phy: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0x1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&gmac1_rstn_l>;
++ reset-assert-us = <20000>;
++ reset-deassert-us = <100000>;
++ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
++ };
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtl8111hs_isolateb_l>;
++ reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3>;
++ status = "okay";
++};
++
++&pinctrl {
++ gmac {
++ gmac1_rstn_l: gmac1-rstn-l {
++ rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ leds {
++ lan_led: lan-led {
++ rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ wan_led: wan-led {
++ rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ work_led: work-led {
++ rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pcie {
++ rtl8111hs_isolateb_l: rtl8111hs-isolateb-l {
++ rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ sdmmc {
++ sdmmc_pwren_l: sdmmc-pwren-l {
++ rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ sdmmc_vol_ctrl_h: sdmmc-vol-ctrl-h {
++ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&pwm1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm1m0_pins>;
++ status = "okay";
++};
++
++&pwm2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm2m0_pins>;
++ status = "okay";
++};
++
++&saradc {
++ vref-supply = <&vcc_1v8>;
++ status = "okay";
++};
++
++&sdhci {
++ bus-width = <8>;
++ cap-mmc-highspeed;
++ mmc-hs200-1_8v;
++ non-removable;
++ vmmc-supply = <&vcc_3v3>;
++ vqmmc-supply = <&vcc_1v8>;
++ status = "okay";
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-sd-highspeed;
++ disable-wp;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc3v3_sd>;
++ vqmmc-supply = <&vccio_sd>;
++ status = "okay";
++};
++
++&uart0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0m0_xfer>;
++ status = "okay";
++};
++
++&usb2phy {
++ status = "okay";
++};
++
++&usb2phy_host {
++ phy-supply = <&vcc5v0_sys>;
++ status = "okay";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
--- /dev/null
+From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 26 Jul 2020 13:32:59 +0200
+Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
+
+This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
+NanoPi R2S. Add the correct value for the RTL8153 LED configuration
+register to match the blink behavior of the other port on the device.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
+ 1 file changed, 1 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -407,6 +407,7 @@
+ rtl8153: device@2 {
+ compatible = "usbbda,8153";
+ reg = <2>;
++ realtek,led-data = <0x87>;
+ };
+ };
+
--- /dev/null
+From: David Bauer <mail@david-bauer.net>
+Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S
+
+The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting
+while U-Boot requires the card to be in 3.3V mode.
+
+Remove UHS support from the SD controller so the card remains in 3.3V
+mode. This reduces transfer speeds but ensures a reboot whether from
+userspace or following a kernel panic is always working.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -336,7 +336,6 @@
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+- sd-uhs-sdr104;
+ vmmc-supply = <&vcc_sd>;
+ vqmmc-supply = <&vcc_sdio>;
+ status = "okay";
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -111,6 +111,11 @@
+ status = "disabled";
+ };
+
++&sdmmc {
++ /delete-property/ sd-uhs-sdr104;
++ cap-sd-highspeed;
++};
++
+ &u2phy0_host {
+ phy-supply = <&vdd_5v>;
+ };
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+@@ -19,6 +19,13 @@
+ model = "FriendlyElec NanoPi R4S";
+ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
+
++ aliases {
++ led-boot = &sys_led;
++ led-failsafe = &sys_led;
++ led-running = &sys_led;
++ led-upgrade = &sys_led;
++ };
++
+ /delete-node/ display-subsystem;
+
+ gpio-leds {
--- /dev/null
+From d2166e3b3680bd2b206aebf1e1ce4c0d346f3c50 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Fri, 19 May 2023 12:10:52 +0800
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Orange Pi R1
+ Plus
+
+Add OpenWrt's LED aliases for showing system status.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+---
+ .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 17 +++++++++--------
+ 1 file changed, 9 insertions(+), 8 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+@@ -18,6 +18,11 @@
+ ethernet0 = &gmac2io;
+ ethernet1 = &rtl8153;
+ mmc0 = &sdmmc;
++
++ led-boot = &status_led;
++ led-failsafe = &status_led;
++ led-running = &status_led;
++ led-upgrade = &status_led;
+ };
+
+ chosen {
+@@ -42,11 +47,10 @@
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ };
+
+- led-1 {
++ status_led: led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+
+ led-2 {
--- /dev/null
+From b46a530d12ada422b9d5b2b97059e0d3ed950b40 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Fri, 19 May 2023 12:38:04 +0800
+Subject: [PATCH] arm64: dts: rockchip: add LED configuration to Orange Pi R1
+ Plus
+
+Add the correct value for the RTL8153 LED configuration register to
+match the blink behavior of the other port on the device.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+@@ -366,6 +366,7 @@
+ rtl8153: device@2 {
+ compatible = "usbbda,8153";
+ reg = <2>;
++ realtek,led-data = <0x87>;
+ };
+ };
+
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dts
+@@ -15,6 +15,13 @@
+ model = "FriendlyElec NanoPC-T4";
+ compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399";
+
++ aliases {
++ led-boot = &status_led;
++ led-failsafe = &status_led;
++ led-running = &status_led;
++ led-upgrade = &status_led;
++ };
++
+ vcc12v0_sys: vcc12v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Tue Jun 20 16:45:27 2023 +0800
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for NanoPi R5
+ series
+
+Add OpenWrt's LED aliases for showing system status.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
+@@ -40,7 +40,6 @@
+ power_led: led-power {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+- linux,default-trigger = "heartbeat";
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
+ };
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+@@ -52,7 +52,6 @@
+ power_led: led-power {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+- linux,default-trigger = "heartbeat";
+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
+ };
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
+@@ -18,6 +18,11 @@
+ aliases {
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
++
++ led-boot = &power_led;
++ led-failsafe = &power_led;
++ led-running = &power_led;
++ led-upgrade = &power_led;
+ };
+
+ chosen: chosen {
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Marius Durbaca <mariusd84@gmail.com>
+Date: Tue Feb 20 15:05:27 2024 +0200
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa
+CM3 IO board
+
+Add OpenWrt's LED aliases for showing system status.
+
+Suggested-by: Tianling Shen <cnsztl@immortalwrt.org>
+Signed-off-by: Marius Durbaca <mariusd84@gmail.com>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -16,6 +16,10 @@
+ aliases {
+ ethernet0 = &gmac1;
+ mmc1 = &sdmmc0;
++ led-boot = &status_led;
++ led-failsafe = &status_led;
++ led-running = &status_led;
++ led-upgrade = &status_led;
+ };
+
+ chosen: chosen {
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+@@ -17,7 +17,7 @@
+ leds {
+ compatible = "gpio-leds";
+
+- led-0 {
++ status_led: led-0 {
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Marius Durbaca <mariusd84@gmail.com>
+Date: Tue Feb 27 16:25:27 2024 +0200
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa
+E25
+
+Add OpenWrt's LED aliases for showing system status.
+
+Signed-off-by: Marius Durbaca <mariusd84@gmail.com>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+@@ -9,6 +9,10 @@
+
+ aliases {
+ mmc1 = &sdmmc0;
++ led-boot = &led_user;
++ led-failsafe = &led_user;
++ led-running = &led_user;
++ led-upgrade = &led_user;
+ };
+
+ pwm-leds {
+--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
+@@ -23,7 +23,7 @@
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ function = LED_FUNCTION_HEARTBEAT;
+ color = <LED_COLOR_ID_GREEN>;
+- linux,default-trigger = "heartbeat";
++ default-state = "on";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_user_en>;
+ };
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
+@@ -18,6 +18,10 @@
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
++ led-boot = &blue_led;
++ led-failsafe = &blue_led;
++ led-running = &blue_led;
++ led-upgrade = &blue_led;
+ };
+
+ chosen {
+@@ -29,22 +33,19 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&green_led>, <&heartbeat_led>;
+
+- green-led {
++ led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+- label = "rockpis:green:power";
+ linux,default-trigger = "default-on";
+ };
+
+- blue-led {
++ blue_led: led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+- label = "rockpis:blue:user";
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dts
+@@ -25,6 +25,10 @@
+ ethernet1 = &gmac2phy;
+ mmc0 = &sdmmc;
+ mmc1 = &emmc;
++ led-boot = &led_blue;
++ led-failsafe = &led_blue;
++ led-running = &led_blue;
++ led-upgrade = &led_blue;
+ };
+
+ chosen {
+@@ -57,10 +61,11 @@
+ pinctrl-0 = <&led_pin>;
+ pinctrl-names = "default";
+
+- led-0 {
++ led_blue: led-0 {
+ color = <LED_COLOR_ID_BLUE>;
++ default-state = "on";
++ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -16,6 +16,10 @@
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc2;
++ led-boot = &led_blue;
++ led-failsafe = &led_blue;
++ led-running = &led_blue;
++ led-upgrade = &led_blue;
+ };
+
+ chosen: chosen {
+@@ -43,11 +47,11 @@
+ leds {
+ compatible = "gpio-leds";
+
+- led_user: led-0 {
+- gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+- function = LED_FUNCTION_HEARTBEAT;
++ led_blue: led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+- linux,default-trigger = "heartbeat";
++ default-state = "on";
++ function = LED_FUNCTION_HEARTBEAT;
++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_user_en>;
+ };
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Mon Aug 05 16:14:33 2024 +0800
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa
+ Rock 5A
+
+Add OpenWrt's LED aliases for showing system status.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -16,6 +16,10 @@
+ ethernet0 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
++ led-boot = &led_green;
++ led-failsafe = &led_green;
++ led-running = &led_green;
++ led-upgrade = &led_green;
+ };
+
+ analog-sound {
+@@ -50,13 +54,19 @@
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+- pinctrl-0 = <&io_led>;
++ pinctrl-0 = <&leds>;
++
++ led_green: led-0 {
++ color = <LED_COLOR_ID_GREEN>;
++ default-state = "on";
++ function = LED_FUNCTION_POWER;
++ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
++ };
+
+ io-led {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
+@@ -366,8 +376,9 @@
+
+ &pinctrl {
+ leds {
+- io_led: io-led {
+- rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++ leds: leds {
++ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
++ <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Mon Aug 05 16:14:33 2024 +0800
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for Radxa
+ Rock 5B/5B+/5T
+
+Add OpenWrt's LED aliases for showing system status.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi
+@@ -27,11 +27,11 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_rgb_b>;
+
+- led_rgb_b {
++ led_blue: led_rgb_b {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
++ default-state = "on";
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
+@@ -30,11 +30,11 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_rgb_b>;
+
+- led_rgb_b {
++ led_blue: led_rgb_b {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
++ default-state = "on";
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
+@@ -12,6 +12,10 @@
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
++ led-boot = &led_blue;
++ led-failsafe = &led_blue;
++ led-running = &led_blue;
++ led-upgrade = &led_blue;
+ };
+
+ chosen {
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
+@@ -20,6 +20,10 @@
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
++ led-boot = &sys_led;
++ led-failsafe = &sys_led;
++ led-running = &sys_led;
++ led-upgrade = &sys_led;
+ };
+
+ adc-keys-0 {
+@@ -53,7 +57,7 @@
+ sys_led: led-0 {
+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ label = "system-led";
+- linux,default-trigger = "heartbeat";
++ default-state = "on";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sys_led_pin>;
+ };
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-hinlink-h28k.dts
+@@ -16,6 +16,11 @@
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ serial0 = &uart0;
++
++ led-boot = &led_work;
++ led-failsafe = &led_work;
++ led-running = &led_work;
++ led-upgrade = &led_work;
+ };
+
+ chosen {
+@@ -55,7 +60,7 @@
+ linux,default-trigger = "netdev";
+ };
+
+- led-2 {
++ led_work: led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_LOW>;
+--- a/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568-hinlink-opc.dtsi
+@@ -11,6 +11,11 @@
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
++
++ led-boot = &led_work;
++ led-failsafe = &led_work;
++ led-running = &led_work;
++ led-upgrade = &led_work;
+ };
+
+ chosen {
+@@ -66,7 +71,7 @@
+ gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+ };
+
+- led-2 {
++ led_work: led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-rock-3c.dts
+@@ -16,6 +16,10 @@
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc1;
++ led-boot = &led_blue;
++ led-failsafe = &led_blue;
++ led-running = &led_blue;
++ led-upgrade = &led_blue;
+ };
+
+ chosen: chosen {
+@@ -43,11 +47,11 @@
+ leds {
+ compatible = "gpio-leds";
+
+- led-0 {
+- gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+- function = LED_FUNCTION_HEARTBEAT;
++ led_blue: led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+- linux,default-trigger = "heartbeat";
++ default-state = "on";
++ function = LED_FUNCTION_HEARTBEAT;
++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led2>;
+ };
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-zero-3.dtsi
+@@ -6,6 +6,13 @@
+ #include "rk3566.dtsi"
+
+ / {
++ aliases {
++ led-boot = &led_green;
++ led-failsafe = &led_green;
++ led-running = &led_green;
++ led-upgrade = &led_green;
++ };
++
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+@@ -26,12 +33,11 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led2>;
+
+- led-green {
++ led_green: led-green {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3b.dts
+@@ -18,6 +18,10 @@
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ mmc2 = &sdmmc2;
++ led-boot = &led_green;
++ led-failsafe = &led_green;
++ led-running = &led_green;
++ led-upgrade = &led_green;
+ };
+
+ chosen {
+@@ -47,12 +51,11 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&led>;
+
+- led-0 {
++ led_green: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Mon Sep 23 13:22:56 2024 +0800
+Subject: [PATCH] arm64: dts: rockchip: Update LED properties for ArmSom
+ Sige7
+
+Add OpenWrt's LED aliases for showing system status.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
+@@ -13,6 +13,11 @@
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
++
++ led-boot = &led_red;
++ led-failsafe = &led_red;
++ led-running = &led_red;
++ led-upgrade = &led_red;
+ };
+
+ chosen {
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+@@ -24,6 +24,11 @@
+ ethernet0 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
++
++ led-boot = &power_led;
++ led-failsafe = &power_led;
++ led-running = &power_led;
++ led-upgrade = &power_led;
+ };
+
+ chosen: chosen {
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
+@@ -17,6 +17,10 @@
+ ethernet0 = &gmac;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
++ led-boot = &led_blue;
++ led-failsafe = &led_blue;
++ led-running = &led_blue;
++ led-upgrade = &led_blue;
+ };
+
+ chosen {
+@@ -44,11 +48,11 @@
+ };
+
+ /* USER_LED2 */
+- led-1 {
++ led_blue: led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
++ default-state = "on";
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+@@ -13,6 +13,10 @@
+ ethernet0 = &gmac;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
++ led-boot = &led_blue;
++ led-failsafe = &led_blue;
++ led-running = &led_blue;
++ led-upgrade = &led_blue;
+ };
+
+ chosen {
+@@ -32,11 +36,11 @@
+ pinctrl-0 = <&user_led2>;
+
+ /* USER_LED2 */
+- led-0 {
++ led_blue: led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_BLUE>;
++ default-state = "on";
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+@@ -23,6 +23,10 @@
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
++ led-boot = &power_led;
++ led-failsafe = &power_led;
++ led-running = &power_led;
++ led-upgrade = &power_led;
+ };
+
+ chosen {
+@@ -62,12 +66,14 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+- power-led1 {
++ power_led: power-led1 {
++ default-state = "on";
++ function = LED_FUNCTION_POWER;
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "default-on";
+ };
+
+ hdd-led2 {
++ function = LED_FUNCTION_DISK;
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ };
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+@@ -19,6 +19,10 @@
+ ethernet0 = &gmac1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
++ led-boot = &led_green;
++ led-failsafe = &led_green;
++ led-running = &led_green;
++ led-upgrade = &led_green;
+ };
+
+ chosen {
+@@ -52,7 +56,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+- led-0 {
++ led_green: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_POWER;
+@@ -61,10 +65,8 @@
+
+ led-1 {
+ color = <LED_COLOR_ID_BLUE>;
+- default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3582-radxa-e52c.dts
+@@ -19,6 +19,10 @@
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
++ led-boot = &led_green;
++ led-failsafe = &led_green;
++ led-running = &led_green;
++ led-upgrade = &led_green;
+ };
+
+ chosen {
+@@ -57,12 +61,11 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_0>;
+
+- led-0 {
++ led_green: led-0 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
+@@ -71,7 +74,6 @@
+
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+- default-state = "on";
+ function = LED_FUNCTION_LAN;
+ linux,default-trigger = "netdev";
+ pwms = <&pwm14 0 1000000 PWM_POLARITY_INVERTED>;
+@@ -80,7 +82,6 @@
+
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+- default-state = "on";
+ function = LED_FUNCTION_WAN;
+ linux,default-trigger = "netdev";
+ pwms = <&pwm11 0 1000000 PWM_POLARITY_INVERTED>;
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
+@@ -9,6 +9,13 @@
+ #include "rk3568.dtsi"
+
+ / {
++ aliases {
++ led-boot = &status_led;
++ led-failsafe = &status_led;
++ led-running = &status_led;
++ led-upgrade = &status_led;
++ };
++
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+@@ -35,7 +42,6 @@
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+ };
+
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts
+@@ -18,6 +18,10 @@
+ compatible = "radxa,rock-4d", "rockchip,rk3576";
+
+ aliases {
++ led-boot = &power_led;
++ led-failsafe = &power_led;
++ led-running = &power_led;
++ led-upgrade = &power_led;
+ ethernet0 = &gmac0;
+ mmc0 = &sdmmc;
+ };
+@@ -50,11 +54,10 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_rgb_g &led_rgb_r>;
+
+- power-led {
++ power_led: power-led {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "default-on";
+ };
+
+ user-led {
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
+@@ -23,6 +23,11 @@
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ mmc2 = &sdio;
++
++ led-boot = &power_led;
++ led-failsafe = &power_led;
++ led-running = &power_led;
++ led-upgrade = &power_led;
+ };
+
+ chosen {
+@@ -54,11 +59,10 @@
+ gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
+ };
+
+- led-1 {
++ power_led: led-1 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+ };
+
+ led-2 {
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts
+@@ -17,6 +17,11 @@
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdhci;
++
++ led-boot = &status_led;
++ led-failsafe = &status_led;
++ led-running = &status_led;
++ led-upgrade = &status_led;
+ };
+
+ chosen: chosen {
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -22,6 +22,11 @@
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ serial0 = &uart0;
++
++ led-boot = &sys_led;
++ led-failsafe = &sys_led;
++ led-running = &sys_led;
++ led-upgrade = &sys_led;
+ };
+
+ chosen {
+@@ -65,15 +70,13 @@
+ default-state = "off";
+ function = LED_FUNCTION_LAN;
+ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "netdev";
+ };
+
+- led-sys {
++ sys_led: led-sys {
+ color = <LED_COLOR_ID_GREEN>;
+- default-state = "on";
++ default-state = "off";
+ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>;
+- linux,default-trigger = "heartbeat";
+ };
+
+ led-wan {
+@@ -81,7 +84,6 @@
+ default-state = "off";
+ function = LED_FUNCTION_WAN;
+ gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "netdev";
+ };
+ };
+
--- /dev/null
+--- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2.dtsi
+@@ -38,7 +38,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_led_b>;
+
+- led-0 {
++ state_led: led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "on";
+ function = LED_FUNCTION_HEARTBEAT;
+--- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2a.dts
+@@ -10,6 +10,11 @@
+
+ aliases {
+ ethernet0 = &gmac1;
++
++ led-boot = &sys_led;
++ led-failsafe = &sys_led;
++ led-running = &sys_led;
++ led-upgrade = &sys_led;
+ };
+
+ vcc5v0_usb30_otg: regulator-5v0-vcc-usb30-otg {
+@@ -40,12 +45,10 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&state_led_b>, <&sys_led_g>;
+
+- led-1 {
++ sys_led: led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+- default-state = "on";
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
+- linux,default-trigger = "default-on";
+ };
+ };
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-rock-2f.dts
+@@ -7,4 +7,16 @@
+ / {
+ model = "Radxa ROCK 2F";
+ compatible = "radxa,rock-2f", "rockchip,rk3528";
++
++ aliases {
++ led-boot = &state_led;
++ led-failsafe = &state_led;
++ led-running = &state_led;
++ led-upgrade = &state_led;
++ };
++};
++
++&state_led {
++ /delete-property/ default-state;
++ /delete-property/ linux,default-trigger;
+ };
--- /dev/null
+From 4e7d472b61625804f585035a54364a6620bf803a Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 23 Jul 2025 12:23:00 +0000
+Subject: [PATCH] phy: rockchip: inno-usb2: Simplify rockchip,usbgrf handling
+
+The logic to decide if usbgrf or grf should be used is more complex than
+it needs to be. For RK3568, RV1108 and soon RK3528 we can assign the
+rockchip,usbgrf regmap directly to grf instead of doing a usbgrf and grf
+dance.
+
+Simplify the code to only use the grf regmap and handle the logic of
+what regmap should be used in driver probe instead.
+
+The only expected change from this is that RK3528 can be supported
+because of an addition of a of_property_present() check.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 68 +++++--------------
+ 1 file changed, 18 insertions(+), 50 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -228,7 +228,6 @@ struct rockchip_usb2phy_port {
+ * struct rockchip_usb2phy - usb2.0 phy driver data.
+ * @dev: pointer to device.
+ * @grf: General Register Files regmap.
+- * @usbgrf: USB General Register Files regmap.
+ * @clks: array of phy input clocks.
+ * @clk480m: clock struct of phy output clk.
+ * @clk480m_hw: clock struct of phy output clk management.
+@@ -246,7 +245,6 @@ struct rockchip_usb2phy_port {
+ struct rockchip_usb2phy {
+ struct device *dev;
+ struct regmap *grf;
+- struct regmap *usbgrf;
+ struct clk_bulk_data *clks;
+ struct clk *clk480m;
+ struct clk_hw clk480m_hw;
+@@ -261,11 +259,6 @@ struct rockchip_usb2phy {
+ struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
+ };
+
+-static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
+-{
+- return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
+-}
+-
+ static inline int property_enable(struct regmap *base,
+ const struct usb2phy_reg *reg, bool en)
+ {
+@@ -323,12 +316,11 @@ static int rockchip_usb2phy_clk480m_prep
+ {
+ struct rockchip_usb2phy *rphy =
+ container_of(hw, struct rockchip_usb2phy, clk480m_hw);
+- struct regmap *base = get_reg_base(rphy);
+ int ret;
+
+ /* turn on 480m clk output if it is off */
+- if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
+- ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
++ if (!property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl)) {
++ ret = property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl, true);
+ if (ret)
+ return ret;
+
+@@ -343,19 +335,17 @@ static void rockchip_usb2phy_clk480m_unp
+ {
+ struct rockchip_usb2phy *rphy =
+ container_of(hw, struct rockchip_usb2phy, clk480m_hw);
+- struct regmap *base = get_reg_base(rphy);
+
+ /* turn off 480m clk output */
+- property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
++ property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl, false);
+ }
+
+ static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
+ {
+ struct rockchip_usb2phy *rphy =
+ container_of(hw, struct rockchip_usb2phy, clk480m_hw);
+- struct regmap *base = get_reg_base(rphy);
+
+- return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
++ return property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl);
+ }
+
+ static unsigned long
+@@ -574,7 +564,6 @@ static int rockchip_usb2phy_power_on(str
+ {
+ struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
+ struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
+- struct regmap *base = get_reg_base(rphy);
+ int ret;
+
+ dev_dbg(&rport->phy->dev, "port power on\n");
+@@ -586,7 +575,7 @@ static int rockchip_usb2phy_power_on(str
+ if (ret)
+ return ret;
+
+- ret = property_enable(base, &rport->port_cfg->phy_sus, false);
++ ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, false);
+ if (ret) {
+ clk_disable_unprepare(rphy->clk480m);
+ return ret;
+@@ -615,7 +604,6 @@ static int rockchip_usb2phy_power_off(st
+ {
+ struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
+ struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
+- struct regmap *base = get_reg_base(rphy);
+ int ret;
+
+ dev_dbg(&rport->phy->dev, "port power off\n");
+@@ -623,7 +611,7 @@ static int rockchip_usb2phy_power_off(st
+ if (rport->suspended)
+ return 0;
+
+- ret = property_enable(base, &rport->port_cfg->phy_sus, true);
++ ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, true);
+ if (ret)
+ return ret;
+
+@@ -787,28 +775,22 @@ static const char *chg_to_string(enum po
+ static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
+ bool en)
+ {
+- struct regmap *base = get_reg_base(rphy);
+-
+- property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
+- property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
++ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
++ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.idp_src_en, en);
+ }
+
+ static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
+ bool en)
+ {
+- struct regmap *base = get_reg_base(rphy);
+-
+- property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
+- property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
++ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.vdp_src_en, en);
++ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.idm_sink_en, en);
+ }
+
+ static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
+ bool en)
+ {
+- struct regmap *base = get_reg_base(rphy);
+-
+- property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
+- property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
++ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.vdm_src_en, en);
++ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.idp_sink_en, en);
+ }
+
+ #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
+@@ -820,7 +802,6 @@ static void rockchip_chg_detect_work(str
+ struct rockchip_usb2phy_port *rport =
+ container_of(work, struct rockchip_usb2phy_port, chg_work.work);
+ struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
+- struct regmap *base = get_reg_base(rphy);
+ bool is_dcd, tmout, vout, vbus_attach;
+ unsigned long delay;
+
+@@ -834,7 +815,7 @@ static void rockchip_chg_detect_work(str
+ rockchip_usb2phy_power_off(rport->phy);
+ /* put the controller in non-driving mode */
+ if (!vbus_attach)
+- property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
++ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.opmode, false);
+ /* Start DCD processing stage 1 */
+ rockchip_chg_enable_dcd(rphy, true);
+ rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
+@@ -898,7 +879,7 @@ static void rockchip_chg_detect_work(str
+ case USB_CHG_STATE_DETECTED:
+ /* put the controller in normal mode */
+ if (!vbus_attach)
+- property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
++ property_enable(rphy->grf, &rphy->phy_cfg->chg_det.opmode, true);
+ rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
+ dev_dbg(&rport->phy->dev, "charger = %s\n",
+ chg_to_string(rphy->chg_type));
+@@ -1353,29 +1334,14 @@ static int rockchip_usb2phy_probe(struct
+ if (!rphy)
+ return -ENOMEM;
+
+- if (!dev->parent || !dev->parent->of_node) {
++ if (!dev->parent || !dev->parent->of_node ||
++ of_property_present(np, "rockchip,usbgrf")) {
+ rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
+- if (IS_ERR(rphy->grf)) {
+- dev_err(dev, "failed to locate usbgrf\n");
+- return PTR_ERR(rphy->grf);
+- }
+- }
+-
+- else {
+- rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
+- if (IS_ERR(rphy->grf))
+- return PTR_ERR(rphy->grf);
+- }
+-
+- if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
+- rphy->usbgrf =
+- syscon_regmap_lookup_by_phandle(dev->of_node,
+- "rockchip,usbgrf");
+- if (IS_ERR(rphy->usbgrf))
+- return PTR_ERR(rphy->usbgrf);
+ } else {
+- rphy->usbgrf = NULL;
++ rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
+ }
++ if (IS_ERR(rphy->grf))
++ return PTR_ERR(rphy->grf);
+
+ if (of_property_read_u32_index(np, "reg", 0, ®)) {
+ dev_err(dev, "the reg property is not assigned in %pOFn node\n",
--- /dev/null
+From 6b767459cf9295f10ee95b8ab78fbce5991132ed Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 23 Jul 2025 12:23:02 +0000
+Subject: [PATCH] phy: rockchip: inno-usb2: Add clkout_ctl_phy support
+
+The 480m clk is controlled using regs in the PHY address space and not
+in the USB GRF address space on e.g. RK3528 and RK3506.
+
+Add a clkout_ctl_phy usb2phy_reg to handle enable/disable of the 480m
+clk on these SoCs.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 47 +++++++++++++++----
+ 1 file changed, 38 insertions(+), 9 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -179,6 +179,7 @@ struct rockchip_usb2phy_cfg {
+ unsigned int num_ports;
+ int (*phy_tuning)(struct rockchip_usb2phy *rphy);
+ struct usb2phy_reg clkout_ctl;
++ struct usb2phy_reg clkout_ctl_phy;
+ const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
+ const struct rockchip_chg_det_reg chg_det;
+ };
+@@ -228,6 +229,7 @@ struct rockchip_usb2phy_port {
+ * struct rockchip_usb2phy - usb2.0 phy driver data.
+ * @dev: pointer to device.
+ * @grf: General Register Files regmap.
++ * @phy_base: USB PHY regmap.
+ * @clks: array of phy input clocks.
+ * @clk480m: clock struct of phy output clk.
+ * @clk480m_hw: clock struct of phy output clk management.
+@@ -245,6 +247,7 @@ struct rockchip_usb2phy_port {
+ struct rockchip_usb2phy {
+ struct device *dev;
+ struct regmap *grf;
++ struct regmap *phy_base;
+ struct clk_bulk_data *clks;
+ struct clk *clk480m;
+ struct clk_hw clk480m_hw;
+@@ -312,15 +315,33 @@ static void rockchip_usb2phy_clk_bulk_di
+ clk_bulk_disable_unprepare(rphy->num_clks, rphy->clks);
+ }
+
+-static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
++static void
++rockchip_usb2phy_clk480m_clkout_ctl(struct clk_hw *hw, struct regmap **base,
++ const struct usb2phy_reg **clkout_ctl)
+ {
+ struct rockchip_usb2phy *rphy =
+ container_of(hw, struct rockchip_usb2phy, clk480m_hw);
++
++ if (rphy->phy_cfg->clkout_ctl_phy.enable) {
++ *base = rphy->phy_base;
++ *clkout_ctl = &rphy->phy_cfg->clkout_ctl_phy;
++ } else {
++ *base = rphy->grf;
++ *clkout_ctl = &rphy->phy_cfg->clkout_ctl;
++ }
++}
++
++static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
++{
++ const struct usb2phy_reg *clkout_ctl;
++ struct regmap *base;
+ int ret;
+
++ rockchip_usb2phy_clk480m_clkout_ctl(hw, &base, &clkout_ctl);
++
+ /* turn on 480m clk output if it is off */
+- if (!property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl)) {
+- ret = property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl, true);
++ if (!property_enabled(base, clkout_ctl)) {
++ ret = property_enable(base, clkout_ctl, true);
+ if (ret)
+ return ret;
+
+@@ -333,19 +354,23 @@ static int rockchip_usb2phy_clk480m_prep
+
+ static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
+ {
+- struct rockchip_usb2phy *rphy =
+- container_of(hw, struct rockchip_usb2phy, clk480m_hw);
++ const struct usb2phy_reg *clkout_ctl;
++ struct regmap *base;
++
++ rockchip_usb2phy_clk480m_clkout_ctl(hw, &base, &clkout_ctl);
+
+ /* turn off 480m clk output */
+- property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl, false);
++ property_enable(base, clkout_ctl, false);
+ }
+
+ static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
+ {
+- struct rockchip_usb2phy *rphy =
+- container_of(hw, struct rockchip_usb2phy, clk480m_hw);
++ const struct usb2phy_reg *clkout_ctl;
++ struct regmap *base;
++
++ rockchip_usb2phy_clk480m_clkout_ctl(hw, &base, &clkout_ctl);
+
+- return property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl);
++ return property_enabled(base, clkout_ctl);
+ }
+
+ static unsigned long
+@@ -1336,9 +1361,13 @@ static int rockchip_usb2phy_probe(struct
+
+ if (!dev->parent || !dev->parent->of_node ||
+ of_property_present(np, "rockchip,usbgrf")) {
++ rphy->phy_base = device_node_to_regmap(np);
++ if (IS_ERR(rphy->phy_base))
++ return PTR_ERR(rphy->phy_base);
+ rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
+ } else {
+ rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
++ rphy->phy_base = rphy->grf;
+ }
+ if (IS_ERR(rphy->grf))
+ return PTR_ERR(rphy->grf);
--- /dev/null
+From 8faac4ef6206a1c771e1c016e205dcee8164d618 Mon Sep 17 00:00:00 2001
+From: Jianwei Zheng <jianwei.zheng@rock-chips.com>
+Date: Wed, 23 Jul 2025 12:23:03 +0000
+Subject: [PATCH] phy: rockchip: inno-usb2: Add support for RK3528
+
+The RK3528 has a single USB2PHY with a otg and host port.
+
+Add support for the RK3528 variant of USB2PHY.
+
+PHY tuning for RK3528:
+
+- Turn off differential receiver in suspend mode to save power
+ consumption.
+
+- Set HS eye-height to 400mV instead of default 450mV.
+
+- Choose the Tx fs/ls data as linestate from TX driver for otg port
+ which uses dwc3 controller to improve fs/ls devices compatibility with
+ long cables.
+
+This is based on vendor kernel linux-stan-6.1-rkr5 tag.
+
+Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 74 +++++++++++++++++++
+ 1 file changed, 74 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -1516,6 +1516,28 @@ static int rk3128_usb2phy_tuning(struct
+ BIT(2) << BIT_WRITEABLE_SHIFT | 0);
+ }
+
++static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
++{
++ int ret = 0;
++
++ /* Turn off otg port differential receiver in suspend mode */
++ ret |= regmap_write(rphy->phy_base, 0x30, BIT(18) | 0x0000);
++
++ /* Turn off host port differential receiver in suspend mode */
++ ret |= regmap_write(rphy->phy_base, 0x430, BIT(18) | 0x0000);
++
++ /* Set otg port HS eye height to 400mv (default is 450mv) */
++ ret |= regmap_write(rphy->phy_base, 0x30, GENMASK(22, 20) | 0x0000);
++
++ /* Set host port HS eye height to 400mv (default is 450mv) */
++ ret |= regmap_write(rphy->phy_base, 0x430, GENMASK(22, 20) | 0x0000);
++
++ /* Choose the Tx fs/ls data as linestate from TX driver for otg port */
++ ret |= regmap_write(rphy->phy_base, 0x94, GENMASK(22, 19) | 0x0018);
++
++ return ret;
++}
++
+ static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+ {
+ int ret;
+@@ -1898,6 +1920,57 @@ static const struct rockchip_usb2phy_cfg
+ { /* sentinel */ }
+ };
+
++static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
++ {
++ .reg = 0xffdf0000,
++ .num_ports = 2,
++ .phy_tuning = rk3528_usb2phy_tuning,
++ .clkout_ctl_phy = { 0x041c, 7, 2, 0, 0x27 },
++ .port_cfgs = {
++ [USB2PHY_PORT_OTG] = {
++ .phy_sus = { 0x004c, 8, 0, 0, 0x1d1 },
++ .bvalid_det_en = { 0x0074, 3, 2, 0, 3 },
++ .bvalid_det_st = { 0x0078, 3, 2, 0, 3 },
++ .bvalid_det_clr = { 0x007c, 3, 2, 0, 3 },
++ .idfall_det_en = { 0x0074, 5, 5, 0, 1 },
++ .idfall_det_st = { 0x0078, 5, 5, 0, 1 },
++ .idfall_det_clr = { 0x007c, 5, 5, 0, 1 },
++ .idrise_det_en = { 0x0074, 4, 4, 0, 1 },
++ .idrise_det_st = { 0x0078, 4, 4, 0, 1 },
++ .idrise_det_clr = { 0x007c, 4, 4, 0, 1 },
++ .ls_det_en = { 0x0074, 0, 0, 0, 1 },
++ .ls_det_st = { 0x0078, 0, 0, 0, 1 },
++ .ls_det_clr = { 0x007c, 0, 0, 0, 1 },
++ .utmi_avalid = { 0x006c, 1, 1, 0, 1 },
++ .utmi_bvalid = { 0x006c, 0, 0, 0, 1 },
++ .utmi_id = { 0x006c, 6, 6, 0, 1 },
++ .utmi_ls = { 0x006c, 5, 4, 0, 1 },
++ },
++ [USB2PHY_PORT_HOST] = {
++ .phy_sus = { 0x005c, 8, 0, 0x1d2, 0x1d1 },
++ .ls_det_en = { 0x0090, 0, 0, 0, 1 },
++ .ls_det_st = { 0x0094, 0, 0, 0, 1 },
++ .ls_det_clr = { 0x0098, 0, 0, 0, 1 },
++ .utmi_ls = { 0x006c, 13, 12, 0, 1 },
++ .utmi_hstdet = { 0x006c, 15, 15, 0, 1 },
++ }
++ },
++ .chg_det = {
++ .opmode = { 0x004c, 3, 0, 5, 1 },
++ .cp_det = { 0x006c, 19, 19, 0, 1 },
++ .dcp_det = { 0x006c, 18, 18, 0, 1 },
++ .dp_det = { 0x006c, 20, 20, 0, 1 },
++ .idm_sink_en = { 0x0058, 1, 1, 0, 1 },
++ .idp_sink_en = { 0x0058, 0, 0, 0, 1 },
++ .idp_src_en = { 0x0058, 2, 2, 0, 1 },
++ .rdm_pdwn_en = { 0x0058, 3, 3, 0, 1 },
++ .vdm_src_en = { 0x0058, 5, 5, 0, 1 },
++ .vdp_src_en = { 0x0058, 4, 4, 0, 1 },
++ },
++ },
++ { /* sentinel */ }
++};
++
+ static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
+ {
+ .reg = 0xfe8a0000,
+@@ -2216,6 +2289,7 @@ static const struct of_device_id rockchi
+ { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
+ { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
+ { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
++ { .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs },
+ { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
+ { .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs },
+ { .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
--- /dev/null
+From 8d3a5547b908e371998376be106fe2b5cd6aacd4 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Thu, 13 Mar 2025 17:49:33 +0000
+Subject: [PATCH] thermal: rockchip: Change to use bulk clks
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/thermal/rockchip_thermal.c | 33 ++++++++++--------------------
+ 1 file changed, 11 insertions(+), 22 deletions(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -140,8 +140,8 @@ struct rockchip_thermal_sensor {
+ * @pdev: platform device of thermal
+ * @reset: the reset controller of tsadc
+ * @sensors: array of thermal sensors
+- * @clk: the controller clock is divided by the exteral 24MHz
+- * @pclk: the advanced peripherals bus clock
++ * @clks: array of clks, e.g. controller and advanced peripherals bus clock
++ * @num_clks: the number of clks
+ * @grf: the general register file will be used to do static set by software
+ * @regs: the base address of tsadc controller
+ * @trim_base: major component of sensor trim value, in Celsius
+@@ -159,8 +159,8 @@ struct rockchip_thermal_data {
+
+ struct rockchip_thermal_sensor *sensors;
+
+- struct clk *clk;
+- struct clk *pclk;
++ struct clk_bulk_data *clks;
++ int num_clks;
+
+ struct regmap *grf;
+ void __iomem *regs;
+@@ -1741,15 +1741,11 @@ static int rockchip_thermal_probe(struct
+ return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset),
+ "failed to get tsadc reset.\n");
+
+- thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc");
+- if (IS_ERR(thermal->clk))
+- return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk),
+- "failed to get tsadc clock.\n");
+-
+- thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
+- if (IS_ERR(thermal->pclk))
+- return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk),
+- "failed to get apb_pclk clock.\n");
++ thermal->num_clks = devm_clk_bulk_get_all_enabled(&pdev->dev,
++ &thermal->clks);
++ if (thermal->num_clks < 0)
++ return dev_err_probe(&pdev->dev, thermal->num_clks,
++ "failed to get clocks.\n");
+
+ rockchip_thermal_reset_controller(thermal->reset);
+
+@@ -1831,8 +1827,7 @@ static int __maybe_unused rockchip_therm
+
+ thermal->chip->control(thermal->regs, false);
+
+- clk_disable(thermal->pclk);
+- clk_disable(thermal->clk);
++ clk_bulk_disable(thermal->num_clks, thermal->clks);
+
+ pinctrl_pm_select_sleep_state(dev);
+
+@@ -1848,16 +1843,10 @@ static int __maybe_unused rockchip_therm
+ int error;
+ int i;
+
+- error = clk_enable(thermal->clk);
++ error = clk_bulk_enable(thermal->num_clks, thermal->clks);
+ if (error)
+ return error;
+
+- error = clk_enable(thermal->pclk);
+- if (error) {
+- clk_disable(thermal->clk);
+- return error;
+- }
+-
+ rockchip_thermal_reset_controller(thermal->reset);
+
+ tsadc->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity);
--- /dev/null
+From ddd86340a007963e8e893555d64f66b63a174ff7 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Thu, 13 Mar 2025 22:51:45 +0000
+Subject: [PATCH] thermal: rockchip: Add support for RK3528
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/thermal/rockchip_thermal.c | 117 +++++++++++++++++++++++++++++
+ 1 file changed, 117 insertions(+)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -206,6 +206,7 @@ struct rockchip_thermal_data {
+ #define TSADCV2_AUTO_PERIOD_HT 0x6c
+ #define TSADCV3_AUTO_PERIOD 0x154
+ #define TSADCV3_AUTO_PERIOD_HT 0x158
++#define TSADCV9_Q_MAX 0x210
+
+ #define TSADCV2_AUTO_EN BIT(0)
+ #define TSADCV2_AUTO_EN_MASK BIT(16)
+@@ -216,6 +217,7 @@ struct rockchip_thermal_data {
+ #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
+
+ #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
++#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17)
+
+ #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
+ #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
+@@ -229,6 +231,7 @@ struct rockchip_thermal_data {
+ #define TSADCV2_DATA_MASK 0xfff
+ #define TSADCV3_DATA_MASK 0x3ff
+ #define TSADCV4_DATA_MASK 0x1ff
++#define TSADCV5_DATA_MASK 0x7ff
+
+ #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
+ #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
+@@ -241,6 +244,9 @@ struct rockchip_thermal_data {
+ #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
+ #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
+ #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
++#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
++#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
++#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
+
+ #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
+ #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
+@@ -251,6 +257,8 @@ struct rockchip_thermal_data {
+
+ #define PX30_GRF_SOC_CON2 0x0408
+
++#define RK3528_GRF_TSADC_CON 0x0030
++
+ #define RK3568_GRF_TSADC_CON 0x0600
+ #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
+ #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
+@@ -522,6 +530,45 @@ static const struct tsadc_table rk3399_c
+ {TSADCV3_DATA_MASK, 125000},
+ };
+
++static const struct tsadc_table rk3528_code_table[] = {
++ {0, -40000},
++ {1410, -40000},
++ {1419, -35000},
++ {1428, -30000},
++ {1436, -25000},
++ {1445, -20000},
++ {1454, -15000},
++ {1463, -10000},
++ {1471, -5000},
++ {1480, 0},
++ {1489, 5000},
++ {1498, 10000},
++ {1506, 15000},
++ {1515, 20000},
++ {1524, 25000},
++ {1533, 30000},
++ {1541, 35000},
++ {1550, 40000},
++ {1558, 45000},
++ {1567, 50000},
++ {1575, 55000},
++ {1584, 60000},
++ {1593, 65000},
++ {1602, 70000},
++ {1610, 75000},
++ {1619, 80000},
++ {1628, 85000},
++ {1637, 90000},
++ {1646, 95000},
++ {1654, 100000},
++ {1663, 105000},
++ {1672, 110000},
++ {1680, 115000},
++ {1689, 120000},
++ {1697, 125000},
++ {TSADCV5_DATA_MASK, 125000},
++};
++
+ static const struct tsadc_table rk3568_code_table[] = {
+ {0, -40000},
+ {1584, -40000},
+@@ -859,6 +906,40 @@ static void rk_tsadcv8_initialize(struct
+ regs + TSADCV2_AUTO_CON);
+ }
+
++static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs,
++ enum tshut_polarity tshut_polarity)
++{
++ writel_relaxed(TSADCV7_AUTO_PERIOD_TIME,
++ regs + TSADCV3_AUTO_PERIOD);
++ writel_relaxed(TSADCV7_AUTO_PERIOD_HT_TIME,
++ regs + TSADCV3_AUTO_PERIOD_HT);
++ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
++ regs + TSADCV3_HIGHT_INT_DEBOUNCE);
++ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
++ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
++ writel_relaxed(TSADCV3_Q_MAX_VAL,
++ regs + TSADCV9_Q_MAX);
++ writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
++ regs + TSADCV2_AUTO_CON);
++
++ if (tshut_polarity == TSHUT_HIGH_ACTIVE)
++ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
++ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
++ regs + TSADCV2_AUTO_CON);
++ else
++ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
++ regs + TSADCV2_AUTO_CON);
++
++ if (!IS_ERR(grf)) {
++ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
++ udelay(15);
++ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
++ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
++ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
++ usleep_range(100, 200);
++ }
++}
++
+ static void rk_tsadcv2_irq_ack(void __iomem *regs)
+ {
+ u32 val;
+@@ -1094,6 +1175,15 @@ static int rk_tsadcv2_get_trim_code(cons
+ return code - base_code;
+ }
+
++static int rk_tsadcv3_get_trim_code(const struct chip_tsadc_table *table,
++ int code, int trim_base, int trim_base_frac)
++{
++ int temp = trim_base * 1000 + trim_base_frac * 100;
++ u32 base_code = rk_tsadcv2_temp_to_code(table, temp);
++
++ return (TSADCV3_Q_MAX_VAL - code) - base_code;
++}
++
+ static const struct rockchip_tsadc_chip px30_tsadc_data = {
+ /* cpu, gpu */
+ .chn_offset = 0,
+@@ -1292,6 +1382,29 @@ static const struct rockchip_tsadc_chip
+ },
+ };
+
++static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
++ /* soc */
++ .chn_offset = 0,
++ .chn_num = 1, /* one channel for tsadc */
++ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
++ .tshut_temp = 95000,
++ .initialize = rk_tsadcv11_initialize,
++ .irq_ack = rk_tsadcv4_irq_ack,
++ .control = rk_tsadcv4_control,
++ .get_temp = rk_tsadcv4_get_temp,
++ .set_alarm_temp = rk_tsadcv3_alarm_temp,
++ .set_tshut_temp = rk_tsadcv3_tshut_temp,
++ .set_tshut_mode = rk_tsadcv4_tshut_mode,
++ .get_trim_code = rk_tsadcv3_get_trim_code,
++ .trim_slope = 574,
++ .table = {
++ .id = rk3528_code_table,
++ .length = ARRAY_SIZE(rk3528_code_table),
++ .data_mask = TSADCV5_DATA_MASK,
++ .mode = ADC_INCREMENT,
++ },
++};
++
+ static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
+ /* cpu, gpu */
+ .chn_offset = 0,
+@@ -1396,6 +1509,10 @@ static const struct of_device_id of_rock
+ .data = (void *)&rk3399_tsadc_data,
+ },
+ {
++ .compatible = "rockchip,rk3528-tsadc",
++ .data = (void *)&rk3528_tsadc_data,
++ },
++ {
+ .compatible = "rockchip,rk3568-tsadc",
+ .data = (void *)&rk3568_tsadc_data,
+ },
--- /dev/null
+From 7f6f8fc3ee62f6eb633320c7989d4ba502787e3c Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 16 Mar 2025 19:18:58 +0000
+Subject: [PATCH] nvmem: rockchip-otp: Handle internal word_size in main
+ reg_read op
+
+Rockchip SoCs RK3576 and RK3588 read data from the OTP using 32-bit
+words instead of normal 8-bit bytes. Similar RK3506, RK3528, RK3562 and
+RK3568 will read data from OTP using 16-bit words.
+
+The nvmem core stride and word_size cannot fully be used as cells is not
+always aligned. Continue to report a stride=1 and word_size=1 in
+nvmem_config and instead handle use of SoC specific word_size internally
+in the driver.
+
+Move current SoC specific word_size handling from the RK3588 read_reg
+operation to the main read_reg operation to help simplify the SoC
+specific read_reg operation and allow code reuse in a future RK3568
+reg_read operation.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+---
+ drivers/nvmem/rockchip-otp.c | 72 ++++++++++++++++++++----------------
+ 1 file changed, 40 insertions(+), 32 deletions(-)
+
+--- a/drivers/nvmem/rockchip-otp.c
++++ b/drivers/nvmem/rockchip-otp.c
+@@ -59,7 +59,6 @@
+ #define RK3588_OTPC_AUTO_EN 0x08
+ #define RK3588_OTPC_INT_ST 0x84
+ #define RK3588_OTPC_DOUT0 0x20
+-#define RK3588_NBYTES 4
+ #define RK3588_BURST_NUM 1
+ #define RK3588_BURST_SHIFT 8
+ #define RK3588_ADDR_SHIFT 16
+@@ -69,6 +68,7 @@
+ struct rockchip_data {
+ int size;
+ int read_offset;
++ int word_size;
+ const char * const *clks;
+ int num_clks;
+ nvmem_reg_read_t reg_read;
+@@ -185,48 +185,28 @@ read_end:
+ }
+
+ static int rk3588_otp_read(void *context, unsigned int offset,
+- void *val, size_t bytes)
++ void *val, size_t count)
+ {
+ struct rockchip_otp *otp = context;
+- unsigned int addr_start, addr_end, addr_len;
+- int ret, i = 0;
+- u32 data;
+- u8 *buf;
+-
+- addr_start = round_down(offset, RK3588_NBYTES) / RK3588_NBYTES;
+- addr_end = round_up(offset + bytes, RK3588_NBYTES) / RK3588_NBYTES;
+- addr_len = addr_end - addr_start;
+- addr_start += otp->data->read_offset / RK3588_NBYTES;
+-
+- buf = kzalloc(array_size(addr_len, RK3588_NBYTES), GFP_KERNEL);
+- if (!buf)
+- return -ENOMEM;
++ u32 *buf = val;
++ int ret;
+
+- while (addr_len--) {
+- writel((addr_start << RK3588_ADDR_SHIFT) |
++ while (count--) {
++ writel((offset++ << RK3588_ADDR_SHIFT) |
+ (RK3588_BURST_NUM << RK3588_BURST_SHIFT),
+ otp->base + RK3588_OTPC_AUTO_CTRL);
+ writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN);
+
+ ret = rockchip_otp_wait_status(otp, RK3588_OTPC_INT_ST,
+ RK3588_RD_DONE);
+- if (ret < 0) {
++ if (ret) {
+ dev_err(otp->dev, "timeout during read setup\n");
+- goto read_end;
++ return ret;
+ }
+
+- data = readl(otp->base + RK3588_OTPC_DOUT0);
+- memcpy(&buf[i], &data, RK3588_NBYTES);
+-
+- i += RK3588_NBYTES;
+- addr_start++;
++ *buf++ = readl(otp->base + RK3588_OTPC_DOUT0);
+ }
+
+- memcpy(val, buf + offset % RK3588_NBYTES, bytes);
+-
+-read_end:
+- kfree(buf);
+-
+ return ret;
+ }
+
+@@ -234,7 +214,7 @@ static int rockchip_otp_read(void *conte
+ void *val, size_t bytes)
+ {
+ struct rockchip_otp *otp = context;
+- int ret;
++ int ret, word_size;
+
+ if (!otp->data || !otp->data->reg_read)
+ return -EINVAL;
+@@ -245,8 +225,34 @@ static int rockchip_otp_read(void *conte
+ return ret;
+ }
+
+- ret = otp->data->reg_read(context, offset, val, bytes);
++ offset += otp->data->read_offset;
++ word_size = otp->data->word_size;
++
++ if (word_size > 1) {
++ unsigned int addr_start, addr_end;
++ size_t count;
++ u8 *buf;
++
++ addr_start = offset / word_size;
++ addr_end = DIV_ROUND_UP(offset + bytes, word_size);
++ count = addr_end - addr_start;
++
++ buf = kzalloc(array_size(count, word_size), GFP_KERNEL);
++ if (!buf) {
++ ret = -ENOMEM;
++ goto err;
++ }
++
++ ret = otp->data->reg_read(context, addr_start, buf, count);
++ if (!ret)
++ memcpy(val, buf + (offset % word_size), bytes);
++
++ kfree(buf);
++ } else {
++ ret = otp->data->reg_read(context, offset, val, bytes);
++ }
+
++err:
+ clk_bulk_disable_unprepare(otp->data->num_clks, otp->clks);
+
+ return ret;
+@@ -259,7 +265,7 @@ static struct nvmem_config otp_config =
+ .type = NVMEM_TYPE_OTP,
+ .read_only = true,
+ .stride = 1,
+- .word_size = 1,
++ .word_size = sizeof(u8),
+ .reg_read = rockchip_otp_read,
+ };
+
+@@ -277,6 +283,7 @@ static const struct rockchip_data px30_d
+ static const struct rockchip_data rk3576_data = {
+ .size = 0x100,
+ .read_offset = 0x700,
++ .word_size = sizeof(u32),
+ .clks = px30_otp_clocks,
+ .num_clks = ARRAY_SIZE(px30_otp_clocks),
+ .reg_read = rk3588_otp_read,
+@@ -289,6 +296,7 @@ static const char * const rk3588_otp_clo
+ static const struct rockchip_data rk3588_data = {
+ .size = 0x400,
+ .read_offset = 0xc00,
++ .word_size = sizeof(u32),
+ .clks = rk3588_otp_clocks,
+ .num_clks = ARRAY_SIZE(rk3588_otp_clocks),
+ .reg_read = rk3588_otp_read,
--- /dev/null
+From 24ddbf99c76a352cc1931ccb5118bca0656034b8 Mon Sep 17 00:00:00 2001
+From: Finley Xiao <finley.xiao@rock-chips.com>
+Date: Tue, 15 Apr 2025 18:32:02 +0800
+Subject: [PATCH] nvmem: rockchip-otp: Add support for RK3568
+
+This adds the necessary data for handling otp the rk3568.
+
+Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/nvmem/rockchip-otp.c | 69 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 69 insertions(+)
+
+--- a/drivers/nvmem/rockchip-otp.c
++++ b/drivers/nvmem/rockchip-otp.c
+@@ -27,6 +27,7 @@
+ #define OTPC_USER_CTRL 0x0100
+ #define OTPC_USER_ADDR 0x0104
+ #define OTPC_USER_ENABLE 0x0108
++#define OTPC_USER_QP 0x0120
+ #define OTPC_USER_Q 0x0124
+ #define OTPC_INT_STATUS 0x0304
+ #define OTPC_SBPI_CMD0_OFFSET 0x1000
+@@ -184,6 +185,58 @@ read_end:
+ return ret;
+ }
+
++static int rk3568_otp_read(void *context, unsigned int offset, void *val,
++ size_t count)
++{
++ struct rockchip_otp *otp = context;
++ u16 *buf = val;
++ u32 otp_qp;
++ int ret;
++
++ ret = rockchip_otp_reset(otp);
++ if (ret) {
++ dev_err(otp->dev, "failed to reset otp phy\n");
++ return ret;
++ }
++
++ ret = rockchip_otp_ecc_enable(otp, true);
++ if (ret) {
++ dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
++ return ret;
++ }
++
++ writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
++ udelay(5);
++
++ while (count--) {
++ writel(offset++ | OTPC_USER_ADDR_MASK,
++ otp->base + OTPC_USER_ADDR);
++ writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
++ otp->base + OTPC_USER_ENABLE);
++
++ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS,
++ OTPC_USER_DONE);
++ if (ret) {
++ dev_err(otp->dev, "timeout during read setup\n");
++ goto read_end;
++ }
++
++ otp_qp = readl(otp->base + OTPC_USER_QP);
++ if (((otp_qp & 0xc0) == 0xc0) || (otp_qp & 0x20)) {
++ ret = -EIO;
++ dev_err(otp->dev, "ecc check error during read setup\n");
++ goto read_end;
++ }
++
++ *buf++ = readl(otp->base + OTPC_USER_Q);
++ }
++
++read_end:
++ writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
++
++ return ret;
++}
++
+ static int rk3588_otp_read(void *context, unsigned int offset,
+ void *val, size_t count)
+ {
+@@ -280,6 +333,18 @@ static const struct rockchip_data px30_d
+ .reg_read = px30_otp_read,
+ };
+
++static const char * const rk3568_otp_clocks[] = {
++ "otp", "apb_pclk", "phy", "sbpi",
++};
++
++static const struct rockchip_data rk3568_data = {
++ .size = 0x80,
++ .word_size = sizeof(u16),
++ .clks = rk3568_otp_clocks,
++ .num_clks = ARRAY_SIZE(rk3568_otp_clocks),
++ .reg_read = rk3568_otp_read,
++};
++
+ static const struct rockchip_data rk3576_data = {
+ .size = 0x100,
+ .read_offset = 0x700,
+@@ -312,6 +377,10 @@ static const struct of_device_id rockchi
+ .data = &px30_data,
+ },
+ {
++ .compatible = "rockchip,rk3568-otp",
++ .data = &rk3568_data,
++ },
++ {
+ .compatible = "rockchip,rk3576-otp",
+ .data = &rk3576_data,
+ },
--- /dev/null
+From 249b07e24d3d1d47b7ec23d5f09a56837b66d7f5 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 16 Mar 2025 00:05:45 +0000
+Subject: [PATCH] nvmem: rockchip-otp: Add support for RK3528
+
+Add support for the OTP controller in RK3528. The OTPC is similar to the
+OTPC in RK3562 and RK3568, exept for a missing phy clock and reset.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ drivers/nvmem/rockchip-otp.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/drivers/nvmem/rockchip-otp.c
++++ b/drivers/nvmem/rockchip-otp.c
+@@ -333,6 +333,18 @@ static const struct rockchip_data px30_d
+ .reg_read = px30_otp_read,
+ };
+
++static const char * const rk3528_otp_clocks[] = {
++ "otp", "apb_pclk", "sbpi",
++};
++
++static const struct rockchip_data rk3528_data = {
++ .size = 0x80,
++ .word_size = sizeof(u16),
++ .clks = rk3528_otp_clocks,
++ .num_clks = ARRAY_SIZE(rk3528_otp_clocks),
++ .reg_read = rk3568_otp_read,
++};
++
+ static const char * const rk3568_otp_clocks[] = {
+ "otp", "apb_pclk", "phy", "sbpi",
+ };
+@@ -377,6 +389,10 @@ static const struct of_device_id rockchi
+ .data = &px30_data,
+ },
+ {
++ .compatible = "rockchip,rk3528-otp",
++ .data = &rk3528_data,
++ },
++ {
+ .compatible = "rockchip,rk3568-otp",
+ .data = &rk3568_data,
+ },
--- /dev/null
+From 8a50a4471e4b0db33a74c01229a7ad386918344b Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Sun, 16 Mar 2025 00:06:43 +0000
+Subject: [PATCH] arm64: dts: rockchip: Enable OTP controller for RK3528
+
+Enable the One Time Programmable Controller (OTPC) in RK3528 and add
+an initial nvmem fixed layout.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 49 ++++++++++++++++++++++++
+ 1 file changed, 49 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -1190,6 +1190,55 @@
+ status = "disabled";
+ };
+
++ otp: nvmem@ffce0000 {
++ compatible = "rockchip,rk3528-otp";
++ reg = <0x0 0xffce0000 0x0 0x4000>;
++ clocks = <&cru CLK_USER_OTPC_NS>,
++ <&cru PCLK_OTPC_NS>,
++ <&cru CLK_SBPI_OTPC_NS>;
++ clock-names = "otp", "apb_pclk", "sbpi";
++ resets = <&cru SRST_USER_OTPC_NS>,
++ <&cru SRST_P_OTPC_NS>,
++ <&cru SRST_SBPI_OTPC_NS>;
++ reset-names = "otp", "apb", "sbpi";
++
++ nvmem-layout {
++ compatible = "fixed-layout";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ cpu_code: cpu-code@2 {
++ reg = <0x02 0x2>;
++ };
++
++ otp_cpu_version: cpu-version@8 {
++ reg = <0x08 0x1>;
++ bits = <3 3>;
++ };
++
++ otp_id: id@a {
++ reg = <0x0a 0x10>;
++ };
++
++ cpu_leakage: cpu-leakage@1a {
++ reg = <0x1a 0x1>;
++ };
++
++ logic_leakage: logic-leakage@1b {
++ reg = <0x1b 0x1>;
++ };
++
++ gpu_leakage: gpu-leakage@1c {
++ reg = <0x1c 0x1>;
++ };
++
++ tsadc_trim: tsadc-trim@44 {
++ reg = <0x44 0x2>;
++ bits = <0 10>;
++ };
++ };
++ };
++
+ dmac: dma-controller@ffd60000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xffd60000 0x0 0x4000>;
--- /dev/null
+From a41519d8b438adc154debd433c3a1436ebb93a10 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 23 Jul 2025 12:23:05 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add USB nodes for RK3528
+
+Rockchip RK3528 has one USB 3.0 DWC3 controller, a USB 2.0 EHCI/OHCI
+controller and uses a USB2PHY for USB 2.0. The DWC3 controller may also
+use the Naneng Combo PHY for USB3.
+
+Add device tree nodes to describe these USB controllers along with the
+USB 2.0 PHYs.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 77 ++++++++++++++++++++++++
+ 1 file changed, 77 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -336,6 +336,30 @@
+ };
+ };
+
++ usb_host0_xhci: usb@fe500000 {
++ compatible = "rockchip,rk3528-dwc3", "snps,dwc3";
++ reg = <0x0 0xfe500000 0x0 0x400000>;
++ clocks = <&cru CLK_REF_USB3OTG>,
++ <&cru CLK_SUSPEND_USB3OTG>,
++ <&cru ACLK_USB3OTG>;
++ clock-names = "ref_clk", "suspend_clk", "bus_clk";
++ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3528_PD_VPU>;
++ resets = <&cru SRST_A_USB3OTG>;
++ dr_mode = "otg";
++ phy_type = "utmi_wide";
++ snps,dis_enblslpm_quirk;
++ snps,dis_rxdet_inp3_quirk;
++ snps,dis-del-phy-power-chg-quirk;
++ snps,dis-tx-ipgap-linecheck-quirk;
++ snps,dis-u1-entry-quirk;
++ snps,dis-u2-entry-quirk;
++ snps,dis-u2-freeclk-exists-quirk;
++ snps,parkmode-disable-hs-quirk;
++ snps,parkmode-disable-ss-quirk;
++ status = "disabled";
++ };
++
+ gic: interrupt-controller@fed01000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xfed01000 0 0x1000>,
+@@ -349,6 +373,30 @@
+ #interrupt-cells = <3>;
+ };
+
++ usb_host0_ehci: usb@ff100000 {
++ compatible = "generic-ehci";
++ reg = <0x0 0xff100000 0x0 0x40000>;
++ clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
++ <&usb2phy>;
++ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&usb2phy_host>;
++ phy-names = "usb";
++ power-domains = <&power RK3528_PD_VO>;
++ status = "disabled";
++ };
++
++ usb_host0_ohci: usb@ff140000 {
++ compatible = "generic-ohci";
++ reg = <0x0 0xff140000 0x0 0x40000>;
++ clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>,
++ <&usb2phy>;
++ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&usb2phy_host>;
++ phy-names = "usb";
++ power-domains = <&power RK3528_PD_VO>;
++ status = "disabled";
++ };
++
+ qos_crypto_a: qos@ff200000 {
+ compatible = "rockchip,rk3528-qos", "syscon";
+ reg = <0x0 0xff200000 0x0 0x20>;
+@@ -1275,6 +1323,35 @@
+ rockchip,pipe-phy-grf = <&pipe_phy_grf>;
+ status = "disabled";
+ };
++
++ usb2phy: usb2phy@ffdf0000 {
++ compatible = "rockchip,rk3528-usb2phy";
++ reg = <0x0 0xffdf0000 0x0 0x10000>;
++ clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
++ clock-names = "phyclk", "pclk";
++ #clock-cells = <0>;
++ clock-output-names = "clk_usbphy_480m";
++ power-domains = <&power RK3528_PD_VO>;
++ rockchip,usbgrf = <&vo_grf>;
++ status = "disabled";
++
++ usb2phy_otg: otg-port {
++ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "otg-bvalid", "otg-id",
++ "linestate";
++ #phy-cells = <0>;
++ status = "disabled";
++ };
++
++ usb2phy_host: host-port {
++ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "linestate";
++ #phy-cells = <0>;
++ status = "disabled";
++ };
++ };
+ };
+ };
+
--- /dev/null
+From bcc0886b4d25cc9d82e4aa0cfa78c1268c3fcb86 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Thu, 13 Mar 2025 22:48:27 +0000
+Subject: [PATCH] arm64: dts: rockchip: Add TSADC controller for RK3528
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ arch/arm64/boot/dts/rockchip/rk3528.dtsi | 78 ++++++++++++++++++++++++
+ 1 file changed, 78 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/thermal/thermal.h>
+ #include <dt-bindings/clock/rockchip,rk3528-cru.h>
+ #include <dt-bindings/power/rockchip,rk3528-power.h>
+ #include <dt-bindings/reset/rockchip,rk3528-cru.h>
+@@ -55,6 +56,7 @@
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
++ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+
+@@ -64,6 +66,7 @@
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
++ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+
+@@ -73,6 +76,7 @@
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
++ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+
+@@ -82,6 +86,7 @@
+ device_type = "cpu";
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
++ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+ };
+@@ -255,6 +260,51 @@
+ };
+ };
+
++ thermal-zones {
++ soc_thermal: soc-thermal {
++ polling-delay-passive = <20>;
++ polling-delay = <1000>;
++ sustainable-power = <638>;
++ thermal-sensors = <&tsadc 0>;
++
++ trips {
++ threshold: trip-point-0 {
++ temperature = <70000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ target: trip-point-1 {
++ temperature = <85000>;
++ hysteresis = <2000>;
++ type = "passive";
++ };
++ soc_crit: soc-crit {
++ temperature = <95000>;
++ hysteresis = <2000>;
++ type = "critical";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&target>;
++ cooling-device =
++ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++ contribution = <2048>;
++ };
++ map1 {
++ trip = <&target>;
++ cooling-device =
++ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++ contribution = <1024>;
++ };
++ };
++ };
++ };
++
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+@@ -689,6 +739,7 @@
+ assigned-clock-rates = <297000000>, <300000000>;
+ clocks = <&cru ACLK_GPU_MALI>, <&scmi_clk SCMI_CLK_GPU>;
+ clock-names = "bus", "core";
++ #cooling-cells = <2>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+@@ -1031,6 +1082,33 @@
+ status = "disabled";
+ };
+
++ tsadc: tsadc@ffad0000 {
++ compatible = "rockchip,rk3528-tsadc";
++ reg = <0x0 0xffad0000 0x0 0x400>;
++ assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
++ assigned-clock-rates = <1200000>, <12000000>;
++ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>,
++ <&cru CLK_TSADC_TSEN>;
++ clock-names = "tsadc", "apb_pclk", "tsen";
++ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
++ power-domains = <&power RK3528_PD_VPU>;
++ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
++ reset-names = "tsadc-apb", "tsadc";
++ rockchip,grf = <&vpu_grf>;
++ rockchip,hw-tshut-mode = <0>;
++ rockchip,hw-tshut-polarity = <0>;
++ rockchip,hw-tshut-temp = <100000>;
++ #thermal-sensor-cells = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ sensor@0 {
++ reg = <0>;
++ nvmem-cells = <&tsadc_trim>;
++ nvmem-cell-names = "trim";
++ };
++ };
++
+ saradc: adc@ffae0000 {
+ compatible = "rockchip,rk3528-saradc";
+ reg = <0x0 0xffae0000 0x0 0x10000>;
--- /dev/null
+From d78af3aa816344d6e76dd77fbaf410fcbfa58bef Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Wed, 23 Jul 2025 12:23:06 +0000
+Subject: [PATCH] arm64: dts: rockchip: Enable USB 2.0 ports on Radxa E20C
+
+The Radxa E20C has one USB2.0 Type-A HOST port and one USB2.0 Type-C OTG
+port.
+
+Add support for using the USB 2.0 ports on Radxa E20C.
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+---
+ .../boot/dts/rockchip/rk3528-radxa-e20c.dts | 48 +++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -136,6 +136,18 @@
+ regulator-max-microvolt = <5000000>;
+ };
+
++ vcc5v0_usb20: regulator-5v0-vcc-usb20 {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&usb_host_en>;
++ regulator-name = "vcc5v0_usb20";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
+ vccio_sd: regulator-vccio-sd {
+ compatible = "regulator-gpio";
+ gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+@@ -275,6 +287,12 @@
+ rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
++
++ usb {
++ usb_host_en: usb-host-en {
++ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
+ };
+
+ &pwm1 {
+@@ -322,3 +340,33 @@
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+ };
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
++
++&usb_host0_xhci {
++ extcon = <&usb2phy>;
++ maximum-speed = "high-speed";
++ phys = <&usb2phy_otg>;
++ phy-names = "usb2-phy";
++ snps,dis_u2_susphy_quirk;
++ status = "okay";
++};
++
++&usb2phy {
++ status = "okay";
++};
++
++&usb2phy_host {
++ phy-supply = <&vcc5v0_usb20>;
++ status = "okay";
++};
++
++&usb2phy_otg {
++ status = "okay";
++};
--- /dev/null
+From 66f872646878e1f124d39bca3966dc65c2af6eef Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Sun, 30 Nov 2025 18:09:03 +0800
+Subject: [PATCH] arm64: dts: rockchip: Use MAC address from EEPROM for
+ Radxa E20C
+
+The EEPROM on the Radxa E20C stores two unique MAC addresses.
+Assigned to network interfaces via device tree.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+---
+
+--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+@@ -17,7 +17,6 @@
+ compatible = "radxa,e20c", "rockchip,rk3528";
+
+ aliases {
+- ethernet0 = &gmac1;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+@@ -213,6 +212,8 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_miim>, <&rgmii_tx_bus2>, <&rgmii_rx_bus2>,
+ <&rgmii_rgmii_clk>, <&rgmii_rgmii_bus>;
++ nvmem-cells = <ð_mac1>;
++ nvmem-cell-names = "mac-address";
+ status = "okay";
+ };
+
+@@ -232,6 +233,20 @@
+ pagesize = <16>;
+ read-only;
+ vcc-supply = <&vcc_3v3>;
++
++ nvmem-layout {
++ compatible = "fixed-layout";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ eth_mac0: macaddr@9e {
++ reg = <0x9e 0x06>;
++ };
++
++ eth_mac1: macaddr@a4 {
++ reg = <0xa4 0x06>;
++ };
++ };
+ };
+ };
+
--- /dev/null
+From 93be10e4e180eeac9b6a57a4363e08c35bee3af9 Mon Sep 17 00:00:00 2001
+From: Sebastian Kropatsch <seb-dev@mail.de>
+Date: Wed, 12 Jun 2024 22:48:10 +0200
+Subject: [PATCH 1/5] arm64: dts: rockchip: Add common definitions for NanoPi
+ R6C and R6S
+
+The FriendlyElec NanoPi R6C and R6S are quite similar boards,
+although they differ in:
+- M.2 M-Key connector vs second RTL8125BG Ethernet port
+- One of the LEDs has a different function on each board
+- 12-pin GPIO FPC vs 30-pin GPIO header
+- R6S has a PWM-based IR receiver while the R6C has not
+- R6S has a 5V fan connector while the R6C has not
+
+Refactor their DT files by adding a common definitions file to
+improve differentiation clarity between both boards and to make
+hardware-specific DT changes easier in the long run.
+Do not introduce any functional changes.
+
+Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
+---
+ .../boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 763 ++++++++++++++++++
+ .../boot/dts/rockchip/rk3588s-nanopi-r6c.dts | 2 +-
+ .../boot/dts/rockchip/rk3588s-nanopi-r6s.dts | 756 +----------------
+ 3 files changed, 767 insertions(+), 754 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+@@ -0,0 +1,763 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Common devicetree definitions for the NanoPi R6C and R6S
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include "rk3588s.dtsi"
++
++/ {
++ aliases {
++ ethernet0 = &gmac1;
++ mmc0 = &sdmmc;
++ mmc1 = &sdhci;
++ };
++
++ chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ adc-keys {
++ compatible = "adc-keys";
++ io-channels = <&saradc 0>;
++ io-channel-names = "buttons";
++ keyup-threshold-microvolt = <1800000>;
++ poll-interval = <100>;
++
++ button-maskrom {
++ label = "Maskrom";
++ linux,code = <KEY_VENDOR>;
++ press-threshold-microvolt = <1800>;
++ };
++ };
++
++ gpio-keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&key1_pin>;
++
++ button-user {
++ label = "User";
++ linux,code = <BTN_1>;
++ gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
++ debounce-interval = <50>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ sys_led: led-0 {
++ label = "sys_led";
++ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ pinctrl-names = "default";
++ pinctrl-0 = <&sys_led_pin>;
++ };
++
++ wan_led: led-1 {
++ label = "wan_led";
++ gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&wan_led_pin>;
++ };
++
++ lan1_led: led-2 {
++ label = "lan1_led";
++ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&lan1_led_pin>;
++ };
++
++ lan2_led: led-3 {
++ gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&lan2_led_pin>;
++ };
++ };
++
++ vcc5v0_sys: vcc5v0-sys-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_1v1_nldo_s3";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1100000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc_3v3_s0: vcc-3v3-s0-regulator {
++ compatible = "regulator-fixed";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_s0";
++ vin-supply = <&vcc_3v3_s3>;
++ };
++
++ vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sd_s0_pwr>;
++ regulator-name = "vcc_3v3_sd_s0";
++ regulator-boot-on;
++ regulator-max-microvolt = <3000000>;
++ regulator-min-microvolt = <3000000>;
++ vin-supply = <&vcc_3v3_s3>;
++ };
++
++ vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_3v3_pcie20";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_3v3_s3>;
++ };
++
++ vcc5v0_usb: vcc5v0-usb-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_usb";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
++
++ vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&typec5v_pwren>;
++ regulator-name = "vcc5v0_usb_otg0";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_usb>;
++ };
++
++ vcc5v0_host_20: vcc5v0-host-20-regulator {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vcc5v0_host20_en>;
++ regulator-name = "vcc5v0_host_20";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_usb>;
++ };
++};
++
++&combphy0_ps {
++ status = "okay";
++};
++
++&combphy2_psu {
++ status = "okay";
++};
++
++&cpu_b0 {
++ cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b1 {
++ cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b2 {
++ cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_b3 {
++ cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_l0 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l1 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l2 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l3 {
++ cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&gmac1 {
++ clock_in_out = "output";
++ phy-handle = <&rgmii_phy1>;
++ phy-mode = "rgmii-rxid";
++ pinctrl-0 = <&gmac1_miim
++ &gmac1_tx_bus2
++ &gmac1_rx_bus2
++ &gmac1_rgmii_clk
++ &gmac1_rgmii_bus>;
++ pinctrl-names = "default";
++ tx_delay = <0x42>;
++ status = "okay";
++};
++
++&i2c0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0m2_xfer>;
++ status = "okay";
++
++ vdd_cpu_big0_s0: regulator@42 {
++ compatible = "rockchip,rk8602";
++ reg = <0x42>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu_big0_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1050000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_big1_s0: regulator@43 {
++ compatible = "rockchip,rk8603", "rockchip,rk8602";
++ reg = <0x43>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_cpu_big1_s0";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <1050000>;
++ regulator-ramp-delay = <2300>;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++};
++
++&i2c2 {
++ status = "okay";
++
++ vdd_npu_s0: regulator@42 {
++ compatible = "rockchip,rk8602";
++ reg = <0x42>;
++ fcs,suspend-voltage-selector = <1>;
++ regulator-name = "vdd_npu_s0";
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <2300>;
++ regulator-boot-on;
++ regulator-always-on;
++ vin-supply = <&vcc5v0_sys>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++};
++
++&i2c6 {
++ clock-frequency = <200000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c6m0_xfer>;
++ status = "okay";
++
++ hym8563: rtc@51 {
++ compatible = "haoyu,hym8563";
++ reg = <0x51>;
++ #clock-cells = <0>;
++ clock-output-names = "hym8563";
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtc_int>;
++ interrupt-parent = <&gpio0>;
++ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
++ wakeup-source;
++ };
++};
++
++&mdio1 {
++ rgmii_phy1: ethernet-phy@1 {
++ compatible = "ethernet-phy-id001c.c916";
++ reg = <0x1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtl8211f_rst>;
++ reset-assert-us = <20000>;
++ reset-deassert-us = <100000>;
++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++ };
++};
++
++&pcie2x1l1 {
++ reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3_pcie20>;
++ status = "okay";
++};
++
++&pcie2x1l2 {
++ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
++ vpcie3v3-supply = <&vcc_3v3_pcie20>;
++ status = "okay";
++};
++
++&pinctrl {
++ gpio-key {
++ key1_pin: key1-pin {
++ rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ gpio-leds {
++ sys_led_pin: sys-led-pin {
++ rockchip,pins =
++ <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ wan_led_pin: wan-led-pin {
++ rockchip,pins =
++ <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ lan1_led_pin: lan1-led-pin {
++ rockchip,pins =
++ <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ lan2_led_pin: lan2-led-pin {
++ rockchip,pins =
++ <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ hym8563 {
++ rtc_int: rtc-int {
++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ sdmmc {
++ sd_s0_pwr: sd-s0-pwr {
++ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ usb {
++ typec5v_pwren: typec5v-pwren {
++ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ vcc5v0_host20_en: vcc5v0-host20-en {
++ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ rtl8211f {
++ rtl8211f_rst: rtl8211f-rst {
++ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
++
++&saradc {
++ vref-supply = <&avcc_1v8_s0>;
++ status = "okay";
++};
++
++&sdhci {
++ bus-width = <8>;
++ no-sdio;
++ no-sd;
++ non-removable;
++ mmc-hs200-1_8v;
++ status = "okay";
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-sd-highspeed;
++ disable-wp;
++ max-frequency = <150000000>;
++ no-mmc;
++ no-sdio;
++ sd-uhs-sdr104;
++ vmmc-supply = <&vcc_3v3_sd_s0>;
++ vqmmc-supply = <&vccio_sd_s0>;
++ status = "okay";
++};
++
++&spi2 {
++ status = "okay";
++ assigned-clocks = <&cru CLK_SPI2>;
++ assigned-clock-rates = <200000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
++ num-cs = <1>;
++
++ pmic@0 {
++ compatible = "rockchip,rk806";
++ spi-max-frequency = <1000000>;
++ reg = <0x0>;
++
++ interrupt-parent = <&gpio0>;
++ interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
++ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
++
++ system-power-controller;
++
++ vcc1-supply = <&vcc5v0_sys>;
++ vcc2-supply = <&vcc5v0_sys>;
++ vcc3-supply = <&vcc5v0_sys>;
++ vcc4-supply = <&vcc5v0_sys>;
++ vcc5-supply = <&vcc5v0_sys>;
++ vcc6-supply = <&vcc5v0_sys>;
++ vcc7-supply = <&vcc5v0_sys>;
++ vcc8-supply = <&vcc5v0_sys>;
++ vcc9-supply = <&vcc5v0_sys>;
++ vcc10-supply = <&vcc5v0_sys>;
++ vcc11-supply = <&vcc_2v0_pldo_s3>;
++ vcc12-supply = <&vcc5v0_sys>;
++ vcc13-supply = <&vcc_1v1_nldo_s3>;
++ vcc14-supply = <&vcc_1v1_nldo_s3>;
++ vcca-supply = <&vcc5v0_sys>;
++
++ gpio-controller;
++ #gpio-cells = <2>;
++
++ rk806_dvs1_null: dvs1-null-pins {
++ pins = "gpio_pwrctrl1";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs2_null: dvs2-null-pins {
++ pins = "gpio_pwrctrl2";
++ function = "pin_fun0";
++ };
++
++ rk806_dvs3_null: dvs3-null-pins {
++ pins = "gpio_pwrctrl3";
++ function = "pin_fun0";
++ };
++
++ regulators {
++ vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_gpu_s0";
++ regulator-enable-ramp-delay = <400>;
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_cpu_lit_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_log_s0: dcdc-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <675000>;
++ regulator-max-microvolt = <750000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_log_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <550000>;
++ regulator-max-microvolt = <950000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_vdenc_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_ddr_s0: dcdc-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <675000>;
++ regulator-max-microvolt = <900000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_ddr_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ vdd2_ddr_s3: dcdc-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vdd2_ddr_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_2v0_pldo_s3: dcdc-reg7 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <2000000>;
++ regulator-max-microvolt = <2000000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vdd_2v0_pldo_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <2000000>;
++ };
++ };
++
++ vcc_3v3_s3: dcdc-reg8 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vddq_ddr_s0: dcdc-reg9 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-name = "vddq_ddr_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vcc_1v8_s3: dcdc-reg10 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ avcc_1v8_s0: pldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "avcc_1v8_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcc_1v8_s0: pldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "vcc_1v8_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ avdd_1v2_s0: pldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-name = "avdd_1v2_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ avcc_3v3_s0: pldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "avcc_3v3_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vccio_sd_s0: pldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-ramp-delay = <12500>;
++ regulator-name = "vccio_sd_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ pldo6_s3: pldo-reg6 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-name = "pldo6_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_0v75_s3: nldo-reg1 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdd_0v75_s3";
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <750000>;
++ };
++ };
++
++ avdd_ddr_pll_s0: nldo-reg2 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "avdd_ddr_pll_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ regulator-suspend-microvolt = <850000>;
++ };
++ };
++
++ avdd_0v75_s0: nldo-reg3 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "avdd_0v75_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ avdd_0v85_s0: nldo-reg4 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <850000>;
++ regulator-max-microvolt = <850000>;
++ regulator-name = "avdd_0v85_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++
++ vdd_0v75_s0: nldo-reg5 {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <750000>;
++ regulator-max-microvolt = <750000>;
++ regulator-name = "vdd_0v75_s0";
++
++ regulator-state-mem {
++ regulator-off-in-suspend;
++ };
++ };
++ };
++ };
++};
++
++&tsadc {
++ status = "okay";
++};
++
++&u2phy2 {
++ status = "okay";
++};
++
++&u2phy2_host {
++ phy-supply = <&vcc5v0_host_20>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-0 = <&uart2m0_xfer>;
++ status = "okay";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
+@@ -2,7 +2,7 @@
+
+ /dts-v1/;
+
+-#include "rk3588s-nanopi-r6s.dts"
++#include "rk3588s-nanopi-r6.dtsi"
+
+ / {
+ model = "FriendlyElec NanoPi R6C";
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
+@@ -2,763 +2,13 @@
+
+ /dts-v1/;
+
+-#include <dt-bindings/pinctrl/rockchip.h>
+-#include <dt-bindings/gpio/gpio.h>
+-#include <dt-bindings/input/input.h>
+-#include "rk3588s.dtsi"
++#include "rk3588s-nanopi-r6.dtsi"
+
+ / {
+ model = "FriendlyElec NanoPi R6S";
+ compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s";
+-
+- aliases {
+- ethernet0 = &gmac1;
+- mmc0 = &sdmmc;
+- mmc1 = &sdhci;
+- };
+-
+- chosen {
+- stdout-path = "serial2:1500000n8";
+- };
+-
+- adc-keys {
+- compatible = "adc-keys";
+- io-channels = <&saradc 0>;
+- io-channel-names = "buttons";
+- keyup-threshold-microvolt = <1800000>;
+- poll-interval = <100>;
+-
+- button-maskrom {
+- label = "Maskrom";
+- linux,code = <KEY_VENDOR>;
+- press-threshold-microvolt = <1800>;
+- };
+- };
+-
+- gpio-keys {
+- compatible = "gpio-keys";
+- pinctrl-names = "default";
+- pinctrl-0 = <&key1_pin>;
+-
+- button-user {
+- label = "User";
+- linux,code = <BTN_1>;
+- gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
+- debounce-interval = <50>;
+- };
+- };
+-
+- leds {
+- compatible = "gpio-leds";
+-
+- sys_led: led-0 {
+- label = "sys_led";
+- gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
+- pinctrl-names = "default";
+- pinctrl-0 = <&sys_led_pin>;
+- };
+-
+- wan_led: led-1 {
+- label = "wan_led";
+- gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&wan_led_pin>;
+- };
+-
+- lan1_led: led-2 {
+- label = "lan1_led";
+- gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&lan1_led_pin>;
+- };
+-
+- lan2_led: led-3 {
+- label = "lan2_led";
+- gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&lan2_led_pin>;
+- };
+- };
+-
+- vcc5v0_sys: vcc5v0-sys-regulator {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc5v0_sys";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <5000000>;
+- regulator-max-microvolt = <5000000>;
+- };
+-
+- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc_1v1_nldo_s3";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1100000>;
+- regulator-max-microvolt = <1100000>;
+- vin-supply = <&vcc5v0_sys>;
+- };
+-
+- vcc_3v3_s0: vcc-3v3-s0-regulator {
+- compatible = "regulator-fixed";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-name = "vcc_3v3_s0";
+- vin-supply = <&vcc_3v3_s3>;
+- };
+-
+- vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
+- compatible = "regulator-fixed";
+- enable-active-high;
+- gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&sd_s0_pwr>;
+- regulator-name = "vcc_3v3_sd_s0";
+- regulator-boot-on;
+- regulator-max-microvolt = <3000000>;
+- regulator-min-microvolt = <3000000>;
+- vin-supply = <&vcc_3v3_s3>;
+- };
+-
+- vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc_3v3_pcie20";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- vin-supply = <&vcc_3v3_s3>;
+- };
+-
+- vcc5v0_usb: vcc5v0-usb-regulator {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc5v0_usb";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <5000000>;
+- regulator-max-microvolt = <5000000>;
+- vin-supply = <&vcc5v0_sys>;
+- };
+-
+- vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator {
+- compatible = "regulator-fixed";
+- enable-active-high;
+- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&typec5v_pwren>;
+- regulator-name = "vcc5v0_usb_otg0";
+- regulator-min-microvolt = <5000000>;
+- regulator-max-microvolt = <5000000>;
+- vin-supply = <&vcc5v0_usb>;
+- };
+-
+- vcc5v0_host_20: vcc5v0-host-20-regulator {
+- compatible = "regulator-fixed";
+- enable-active-high;
+- gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&vcc5v0_host20_en>;
+- regulator-name = "vcc5v0_host_20";
+- regulator-min-microvolt = <5000000>;
+- regulator-max-microvolt = <5000000>;
+- vin-supply = <&vcc5v0_usb>;
+- };
+-};
+-
+-&combphy0_ps {
+- status = "okay";
+-};
+-
+-&combphy2_psu {
+- status = "okay";
+-};
+-
+-&cpu_b0 {
+- cpu-supply = <&vdd_cpu_big0_s0>;
+-};
+-
+-&cpu_b1 {
+- cpu-supply = <&vdd_cpu_big0_s0>;
+-};
+-
+-&cpu_b2 {
+- cpu-supply = <&vdd_cpu_big1_s0>;
+-};
+-
+-&cpu_b3 {
+- cpu-supply = <&vdd_cpu_big1_s0>;
+-};
+-
+-&cpu_l0 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&cpu_l1 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&cpu_l2 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&cpu_l3 {
+- cpu-supply = <&vdd_cpu_lit_s0>;
+-};
+-
+-&gmac1 {
+- clock_in_out = "output";
+- phy-handle = <&rgmii_phy1>;
+- phy-mode = "rgmii-rxid";
+- pinctrl-0 = <&gmac1_miim
+- &gmac1_tx_bus2
+- &gmac1_rx_bus2
+- &gmac1_rgmii_clk
+- &gmac1_rgmii_bus>;
+- pinctrl-names = "default";
+- tx_delay = <0x42>;
+- status = "okay";
+-};
+-
+-&i2c0 {
+- pinctrl-names = "default";
+- pinctrl-0 = <&i2c0m2_xfer>;
+- status = "okay";
+-
+- vdd_cpu_big0_s0: regulator@42 {
+- compatible = "rockchip,rk8602";
+- reg = <0x42>;
+- fcs,suspend-voltage-selector = <1>;
+- regulator-name = "vdd_cpu_big0_s0";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <1050000>;
+- regulator-ramp-delay = <2300>;
+- vin-supply = <&vcc5v0_sys>;
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_cpu_big1_s0: regulator@43 {
+- compatible = "rockchip,rk8603", "rockchip,rk8602";
+- reg = <0x43>;
+- fcs,suspend-voltage-selector = <1>;
+- regulator-name = "vdd_cpu_big1_s0";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <1050000>;
+- regulator-ramp-delay = <2300>;
+- vin-supply = <&vcc5v0_sys>;
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-};
+-
+-&i2c2 {
+- status = "okay";
+-
+- vdd_npu_s0: regulator@42 {
+- compatible = "rockchip,rk8602";
+- reg = <0x42>;
+- fcs,suspend-voltage-selector = <1>;
+- regulator-name = "vdd_npu_s0";
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <950000>;
+- regulator-ramp-delay = <2300>;
+- regulator-boot-on;
+- regulator-always-on;
+- vin-supply = <&vcc5v0_sys>;
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-};
+-
+-&i2c6 {
+- clock-frequency = <200000>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&i2c6m0_xfer>;
+- status = "okay";
+-
+- hym8563: rtc@51 {
+- compatible = "haoyu,hym8563";
+- reg = <0x51>;
+- #clock-cells = <0>;
+- clock-output-names = "hym8563";
+- pinctrl-names = "default";
+- pinctrl-0 = <&rtc_int>;
+- interrupt-parent = <&gpio0>;
+- interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
+- wakeup-source;
+- };
+-};
+-
+-&mdio1 {
+- rgmii_phy1: ethernet-phy@1 {
+- compatible = "ethernet-phy-id001c.c916";
+- reg = <0x1>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&rtl8211f_rst>;
+- reset-assert-us = <20000>;
+- reset-deassert-us = <100000>;
+- reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+- };
+-};
+-
+-&pcie2x1l1 {
+- reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+- vpcie3v3-supply = <&vcc_3v3_pcie20>;
+- status = "okay";
+-};
+-
+-&pcie2x1l2 {
+- reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+- vpcie3v3-supply = <&vcc_3v3_pcie20>;
+- status = "okay";
+-};
+-
+-&pinctrl {
+- gpio-key {
+- key1_pin: key1-pin {
+- rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
+- };
+- };
+-
+- gpio-leds {
+- sys_led_pin: sys-led-pin {
+- rockchip,pins =
+- <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+- wan_led_pin: wan-led-pin {
+- rockchip,pins =
+- <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+- lan1_led_pin: lan1-led-pin {
+- rockchip,pins =
+- <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+- lan2_led_pin: lan2-led-pin {
+- rockchip,pins =
+- <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- hym8563 {
+- rtc_int: rtc-int {
+- rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
+- };
+- };
+-
+- sdmmc {
+- sd_s0_pwr: sd-s0-pwr {
+- rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+- };
+- };
+-
+- usb {
+- typec5v_pwren: typec5v-pwren {
+- rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+- vcc5v0_host20_en: vcc5v0-host20-en {
+- rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-
+- rtl8211f {
+- rtl8211f_rst: rtl8211f-rst {
+- rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+- };
+-};
+-
+-&saradc {
+- vref-supply = <&avcc_1v8_s0>;
+- status = "okay";
+-};
+-
+-&sdhci {
+- bus-width = <8>;
+- no-sdio;
+- no-sd;
+- non-removable;
+- mmc-hs200-1_8v;
+- status = "okay";
+-};
+-
+-&sdmmc {
+- bus-width = <4>;
+- cap-sd-highspeed;
+- disable-wp;
+- max-frequency = <150000000>;
+- no-mmc;
+- no-sdio;
+- sd-uhs-sdr104;
+- vmmc-supply = <&vcc_3v3_sd_s0>;
+- vqmmc-supply = <&vccio_sd_s0>;
+- status = "okay";
+-};
+-
+-&spi2 {
+- status = "okay";
+- assigned-clocks = <&cru CLK_SPI2>;
+- assigned-clock-rates = <200000000>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+- num-cs = <1>;
+-
+- pmic@0 {
+- compatible = "rockchip,rk806";
+- spi-max-frequency = <1000000>;
+- reg = <0x0>;
+-
+- interrupt-parent = <&gpio0>;
+- interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
+-
+- pinctrl-names = "default";
+- pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+- <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+-
+- system-power-controller;
+-
+- vcc1-supply = <&vcc5v0_sys>;
+- vcc2-supply = <&vcc5v0_sys>;
+- vcc3-supply = <&vcc5v0_sys>;
+- vcc4-supply = <&vcc5v0_sys>;
+- vcc5-supply = <&vcc5v0_sys>;
+- vcc6-supply = <&vcc5v0_sys>;
+- vcc7-supply = <&vcc5v0_sys>;
+- vcc8-supply = <&vcc5v0_sys>;
+- vcc9-supply = <&vcc5v0_sys>;
+- vcc10-supply = <&vcc5v0_sys>;
+- vcc11-supply = <&vcc_2v0_pldo_s3>;
+- vcc12-supply = <&vcc5v0_sys>;
+- vcc13-supply = <&vcc_1v1_nldo_s3>;
+- vcc14-supply = <&vcc_1v1_nldo_s3>;
+- vcca-supply = <&vcc5v0_sys>;
+-
+- gpio-controller;
+- #gpio-cells = <2>;
+-
+- rk806_dvs1_null: dvs1-null-pins {
+- pins = "gpio_pwrctrl1";
+- function = "pin_fun0";
+- };
+-
+- rk806_dvs2_null: dvs2-null-pins {
+- pins = "gpio_pwrctrl2";
+- function = "pin_fun0";
+- };
+-
+- rk806_dvs3_null: dvs3-null-pins {
+- pins = "gpio_pwrctrl3";
+- function = "pin_fun0";
+- };
+-
+- regulators {
+- vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <950000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_gpu_s0";
+- regulator-enable-ramp-delay = <400>;
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <950000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_cpu_lit_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_log_s0: dcdc-reg3 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <675000>;
+- regulator-max-microvolt = <750000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_log_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <750000>;
+- };
+- };
+-
+- vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <550000>;
+- regulator-max-microvolt = <950000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_vdenc_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_ddr_s0: dcdc-reg5 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <675000>;
+- regulator-max-microvolt = <900000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_ddr_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <850000>;
+- };
+- };
+-
+- vdd2_ddr_s3: dcdc-reg6 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-name = "vdd2_ddr_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- };
+- };
+-
+- vcc_2v0_pldo_s3: dcdc-reg7 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <2000000>;
+- regulator-max-microvolt = <2000000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vdd_2v0_pldo_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <2000000>;
+- };
+- };
+-
+- vcc_3v3_s3: dcdc-reg8 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-name = "vcc_3v3_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <3300000>;
+- };
+- };
+-
+- vddq_ddr_s0: dcdc-reg9 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-name = "vddq_ddr_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vcc_1v8_s3: dcdc-reg10 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "vcc_1v8_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <1800000>;
+- };
+- };
+-
+- avcc_1v8_s0: pldo-reg1 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "avcc_1v8_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <1800000>;
+- };
+- };
+-
+- vcc_1v8_s0: pldo-reg2 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "vcc_1v8_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <1800000>;
+- };
+- };
+-
+- avdd_1v2_s0: pldo-reg3 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1200000>;
+- regulator-max-microvolt = <1200000>;
+- regulator-name = "avdd_1v2_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- avcc_3v3_s0: pldo-reg4 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "avcc_3v3_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vccio_sd_s0: pldo-reg5 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-ramp-delay = <12500>;
+- regulator-name = "vccio_sd_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- pldo6_s3: pldo-reg6 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <1800000>;
+- regulator-max-microvolt = <1800000>;
+- regulator-name = "pldo6_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <1800000>;
+- };
+- };
+-
+- vdd_0v75_s3: nldo-reg1 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <750000>;
+- regulator-max-microvolt = <750000>;
+- regulator-name = "vdd_0v75_s3";
+-
+- regulator-state-mem {
+- regulator-on-in-suspend;
+- regulator-suspend-microvolt = <750000>;
+- };
+- };
+-
+- avdd_ddr_pll_s0: nldo-reg2 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <850000>;
+- regulator-max-microvolt = <850000>;
+- regulator-name = "avdd_ddr_pll_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- regulator-suspend-microvolt = <850000>;
+- };
+- };
+-
+- avdd_0v75_s0: nldo-reg3 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <750000>;
+- regulator-max-microvolt = <750000>;
+- regulator-name = "avdd_0v75_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- avdd_0v85_s0: nldo-reg4 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <850000>;
+- regulator-max-microvolt = <850000>;
+- regulator-name = "avdd_0v85_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+-
+- vdd_0v75_s0: nldo-reg5 {
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <750000>;
+- regulator-max-microvolt = <750000>;
+- regulator-name = "vdd_0v75_s0";
+-
+- regulator-state-mem {
+- regulator-off-in-suspend;
+- };
+- };
+- };
+- };
+-};
+-
+-&tsadc {
+- status = "okay";
+-};
+-
+-&u2phy2 {
+- status = "okay";
+-};
+-
+-&u2phy2_host {
+- phy-supply = <&vcc5v0_host_20>;
+- status = "okay";
+-};
+-
+-&uart2 {
+- pinctrl-0 = <&uart2m0_xfer>;
+- status = "okay";
+-};
+-
+-&usb_host0_ehci {
+- status = "okay";
+ };
+
+-&usb_host0_ohci {
+- status = "okay";
++&lan2_led {
++ label = "lan2_led";
+ };
--- /dev/null
+From cd909b668132acd6f846336f15abf5185cfc4dbc Mon Sep 17 00:00:00 2001
+From: Sebastian Kropatsch <seb-dev@mail.de>
+Date: Wed, 12 Jun 2024 22:48:11 +0200
+Subject: [PATCH 2/5] arm64: dts: rockchip: Fix regulators, gmac and naming on
+ NanoPi R6C/R6S
+
+Fix the alphabetical ordering in some nodes and rename some regulators
+and pins to match the schematics [1][2] as well as to adhere to
+preferred naming schemes.
+
+In addition to that:
+* vcc_3v3_sd_s0: Fix voltage to be 3.3V
+* vcc3v3_pcie:
+ - Move to NanoPi R6C, this power switch is not available on R6S
+ - Fix vin-supply (is vcc_5v0 per schematics)
+ - Add gpios/pincrtl to enable power
+* vcc5v0_usb: Remove this regulator since according to the schematics,
+ vcc5v0_host_20 and vcc5v0_usb_otg0 are directly powered by vcc_5v0
+* gmac1: Add rx_delay of 0 (no delay since phy-mode = "rgmii-rxid")
+* rgmii_phy1: Add phy-supply as seen in schematics
+* pcie2*:
+ - Add pinctrl reset pins
+ - Update vpcie3v3-supply to match the schematics
+* sdhci: Add vmmc-supply and vqmmc-supply
+
+Links:
+[1] https://wiki.friendlyelec.com/wiki/images/f/f7/NanoPi_R6C_2302_SCH.PDF
+[2] https://wiki.friendlyelec.com/wiki/images/2/2f/NanoPi_R6S_2208_SCH.PDF
+
+Fixes: f1b11f43b3e9 ("arm64: dts: rockchip: Add support for NanoPi R6S")
+Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
+---
+ .../boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 169 +++++++++---------
+ .../boot/dts/rockchip/rk3588s-nanopi-r6c.dts | 28 +++
+ .../boot/dts/rockchip/rk3588s-nanopi-r6s.dts | 5 +
+ 3 files changed, 122 insertions(+), 80 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+@@ -21,7 +21,7 @@
+ stdout-path = "serial2:1500000n8";
+ };
+
+- adc-keys {
++ adc-key-maskrom {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+@@ -41,10 +41,10 @@
+ pinctrl-0 = <&key1_pin>;
+
+ button-user {
+- label = "User";
+- linux,code = <BTN_1>;
+- gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
+ debounce-interval = <50>;
++ gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
++ label = "User Button";
++ linux,code = <BTN_1>;
+ };
+ };
+
+@@ -80,26 +80,27 @@
+ };
+ };
+
+- vcc5v0_sys: vcc5v0-sys-regulator {
++ vcc_5v0: regulator-vcc-5v0 {
+ compatible = "regulator-fixed";
+- regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
++ regulator-name = "vcc_5v0";
+ };
+
+- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
++ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+- regulator-name = "vcc_1v1_nldo_s3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+- vin-supply = <&vcc5v0_sys>;
++ regulator-name = "vcc_1v1_nldo_s3";
++ vin-supply = <&vcc_5v0>;
+ };
+
+- vcc_3v3_s0: vcc-3v3-s0-regulator {
++ /* SY6280AAC power switch (U3824 in schematics) */
++ vcc_3v3_s0: regulator-vcc-3v3-s0 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+@@ -109,61 +110,45 @@
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+- vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
++ vcc_3v3_sd_s0: regulator-vcc-3v3-sd-s0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_s0_pwr>;
+- regulator-name = "vcc_3v3_sd_s0";
+- regulator-boot-on;
+- regulator-max-microvolt = <3000000>;
+- regulator-min-microvolt = <3000000>;
+- vin-supply = <&vcc_3v3_s3>;
+- };
+-
+- vcc_3v3_pcie20: vcc3v3-pcie20-regulator {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc_3v3_pcie20";
+- regulator-always-on;
+ regulator-boot-on;
+- regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
++ regulator-min-microvolt = <3300000>;
++ regulator-name = "vcc_3v3_sd_s0";
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+- vcc5v0_usb: vcc5v0-usb-regulator {
+- compatible = "regulator-fixed";
+- regulator-name = "vcc5v0_usb";
+- regulator-always-on;
+- regulator-boot-on;
+- regulator-min-microvolt = <5000000>;
+- regulator-max-microvolt = <5000000>;
+- vin-supply = <&vcc5v0_sys>;
+- };
+-
+- vcc5v0_usb_otg0: vcc5v0-usb-otg0-regulator {
++ /* SY6280AAC power switch (U9539 in schematics) */
++ /* For USB 2.0 Type-A port */
++ vcc_5v0_host_20: regulator-vcc-5v0-host-20 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+- gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
++ gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&typec5v_pwren>;
+- regulator-name = "vcc5v0_usb_otg0";
++ pinctrl-0 = <&usb_host_pwren_h>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+- vin-supply = <&vcc5v0_usb>;
++ regulator-name = "vcc_5v0_host_20";
++ vin-supply = <&vcc_5v0>;
+ };
+
+- vcc5v0_host_20: vcc5v0-host-20-regulator {
++ /* SY6280AAC power switch (U9538 in schematics) */
++ /* For USB 3.0 Type-A port */
++ vcc5v0_usb_otg0: regulator-vcc5v0-usb-otg0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+- gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
++ gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&vcc5v0_host20_en>;
+- regulator-name = "vcc5v0_host_20";
++ pinctrl-0 = <&typec5v_pwren_h>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+- vin-supply = <&vcc5v0_usb>;
++ regulator-name = "vcc5v0_usb_otg0";
++ vin-supply = <&vcc_5v0>;
+ };
+ };
+
+@@ -211,12 +196,13 @@
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-rxid";
++ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1_miim
+ &gmac1_tx_bus2
+ &gmac1_rx_bus2
+ &gmac1_rgmii_clk
+ &gmac1_rgmii_bus>;
+- pinctrl-names = "default";
++ rx_delay = <0x00>;
+ tx_delay = <0x42>;
+ status = "okay";
+ };
+@@ -230,13 +216,13 @@
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+- regulator-name = "vdd_cpu_big0_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
++ regulator-name = "vdd_cpu_big0_s0";
+ regulator-ramp-delay = <2300>;
+- vin-supply = <&vcc5v0_sys>;
++ vin-supply = <&vcc_5v0>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+@@ -247,13 +233,13 @@
+ compatible = "rockchip,rk8603", "rockchip,rk8602";
+ reg = <0x43>;
+ fcs,suspend-voltage-selector = <1>;
+- regulator-name = "vdd_cpu_big1_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1050000>;
++ regulator-name = "vdd_cpu_big1_s0";
+ regulator-ramp-delay = <2300>;
+- vin-supply = <&vcc5v0_sys>;
++ vin-supply = <&vcc_5v0>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+@@ -268,13 +254,13 @@
+ compatible = "rockchip,rk8602";
+ reg = <0x42>;
+ fcs,suspend-voltage-selector = <1>;
+- regulator-name = "vdd_npu_s0";
++ regulator-always-on;
++ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
++ regulator-name = "vdd_npu_s0";
+ regulator-ramp-delay = <2300>;
+- regulator-boot-on;
+- regulator-always-on;
+- vin-supply = <&vcc5v0_sys>;
++ vin-supply = <&vcc_5v0>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+@@ -293,35 +279,43 @@
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+- pinctrl-names = "default";
+- pinctrl-0 = <&rtc_int>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtc_int>;
+ wakeup-source;
+ };
+ };
+
++/* RTL8211F-CG Ethernet */
+ &mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id001c.c916";
+ reg = <0x1>;
++ phy-supply = <&vcc_3v3_s0>;
+ pinctrl-names = "default";
+- pinctrl-0 = <&rtl8211f_rst>;
++ pinctrl-0 = <&gmac1_rstn_l>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
++/* RTL8125BG Ethernet */
+ &pcie2x1l1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie20x1_1_perstn_m2>;
+ reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
+- vpcie3v3-supply = <&vcc_3v3_pcie20>;
++ vpcie3v3-supply = <&vcc_3v3_s3>;
+ status = "okay";
+ };
+
++/* R6C: M.2 M-Key socket */
++/* R6S: RTL8125BG Ethernet */
+ &pcie2x1l2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie20x1_2_perstn_m0>;
+ reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
+- vpcie3v3-supply = <&vcc_3v3_pcie20>;
+ status = "okay";
+ };
+
+@@ -360,24 +354,34 @@
+ };
+ };
+
++ pcie {
++ pcie20x1_1_perstn_m2: pcie2x1-1-rst {
++ rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ pcie20x1_2_perstn_m0: pcie2x1-2-rst {
++ rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ sdmmc {
+- sd_s0_pwr: sd-s0-pwr {
++ sd_s0_pwr: sd-pwr {
+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+- typec5v_pwren: typec5v-pwren {
++ typec5v_pwren_h: usb3-pwren {
+ rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+- vcc5v0_host20_en: vcc5v0-host20-en {
++ usb_host_pwren_h: usb2-pwren {
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ rtl8211f {
+- rtl8211f_rst: rtl8211f-rst {
++ gmac1_rstn_l: rtl8211f-rst {
+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+@@ -388,15 +392,19 @@
+ status = "okay";
+ };
+
++/* eMMC */
+ &sdhci {
+ bus-width = <8>;
+- no-sdio;
++ mmc-hs200-1_8v;
+ no-sd;
++ no-sdio;
+ non-removable;
+- mmc-hs200-1_8v;
++ vmmc-supply = <&vcc_3v3_s3>;
++ vqmmc-supply = <&vcc_1v8_s3>;
+ status = "okay";
+ };
+
++/* microSD card */
+ &sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
+@@ -411,16 +419,15 @@
+ };
+
+ &spi2 {
+- status = "okay";
+ assigned-clocks = <&cru CLK_SPI2>;
+ assigned-clock-rates = <200000000>;
++ num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
+- num-cs = <1>;
++ status = "okay";
+
+- pmic@0 {
++ rk806_single: pmic@0 {
+ compatible = "rockchip,rk806";
+- spi-max-frequency = <1000000>;
+ reg = <0x0>;
+
+ interrupt-parent = <&gpio0>;
+@@ -430,23 +437,24 @@
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+
++ spi-max-frequency = <1000000>;
+ system-power-controller;
+
+- vcc1-supply = <&vcc5v0_sys>;
+- vcc2-supply = <&vcc5v0_sys>;
+- vcc3-supply = <&vcc5v0_sys>;
+- vcc4-supply = <&vcc5v0_sys>;
+- vcc5-supply = <&vcc5v0_sys>;
+- vcc6-supply = <&vcc5v0_sys>;
+- vcc7-supply = <&vcc5v0_sys>;
+- vcc8-supply = <&vcc5v0_sys>;
+- vcc9-supply = <&vcc5v0_sys>;
+- vcc10-supply = <&vcc5v0_sys>;
++ vcc1-supply = <&vcc_5v0>;
++ vcc2-supply = <&vcc_5v0>;
++ vcc3-supply = <&vcc_5v0>;
++ vcc4-supply = <&vcc_5v0>;
++ vcc5-supply = <&vcc_5v0>;
++ vcc6-supply = <&vcc_5v0>;
++ vcc7-supply = <&vcc_5v0>;
++ vcc8-supply = <&vcc_5v0>;
++ vcc9-supply = <&vcc_5v0>;
++ vcc10-supply = <&vcc_5v0>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+- vcc12-supply = <&vcc5v0_sys>;
++ vcc12-supply = <&vcc_5v0>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+- vcca-supply = <&vcc5v0_sys>;
++ vcca-supply = <&vcc_5v0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+@@ -745,10 +753,11 @@
+ };
+
+ &u2phy2_host {
+- phy-supply = <&vcc5v0_host_20>;
++ phy-supply = <&vcc_5v0_host_20>;
+ status = "okay";
+ };
+
++/* Debug UART */
+ &uart2 {
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "okay";
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
+@@ -7,8 +7,36 @@
+ / {
+ model = "FriendlyElec NanoPi R6C";
+ compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588s";
++
++ /* MP2143DJ power switch (U9536 in schematics) */
++ vcc3v3_pcie: regulator-vcc3v3-pcie {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie20x1_2_con_pwren>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc3v3_pcie";
++ vin-supply = <&vcc_5v0>;
++ };
+ };
+
+ &lan2_led {
+ label = "user_led";
+ };
++
++/* M.2 M-Key socket */
++&pcie2x1l2 {
++ vpcie3v3-supply = <&vcc3v3_pcie>;
++};
++
++&pinctrl {
++ pcie {
++ pcie20x1_2_con_pwren: pcie20x1-2-con-pwren {
++ rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
+@@ -12,3 +12,8 @@
+ &lan2_led {
+ label = "lan2_led";
+ };
++
++/* RTL8125BG Ethernet */
++&pcie2x1l2 {
++ vpcie3v3-supply = <&vcc_3v3_s3>;
++};
--- /dev/null
+From dfa0e0a42f3e256189849a45203aac98a0b4d1aa Mon Sep 17 00:00:00 2001
+From: Sebastian Kropatsch <seb-dev@mail.de>
+Date: Wed, 12 Jun 2024 22:48:12 +0200
+Subject: [PATCH 3/5] arm64: dts: rockchip: Improve LEDs on NanoPi R6C/R6S
+
+Move led-3 node into NanoPi R6C/R6S's source files since they have
+different functionalities on each board: On the R6S this LED is used
+to signal LAN2 link up, while on the R6C this LED does not have a
+pre-defined purpose.
+
+In addition to that:
+ - Remove deprecated label property
+ - Add color and function properties
+ - Add linux,default-trigger to trigger on Ethernet link
+
+Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
+---
+ .../boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 32 +++++++------------
+ .../boot/dts/rockchip/rk3588s-nanopi-r6c.dts | 22 ++++++++++---
+ .../boot/dts/rockchip/rk3588s-nanopi-r6s.dts | 26 +++++++++++++--
+ 3 files changed, 54 insertions(+), 26 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
+ #include "rk3588s.dtsi"
+
+ / {
+@@ -52,7 +53,8 @@
+ compatible = "gpio-leds";
+
+ sys_led: led-0 {
+- label = "sys_led";
++ color = <LED_COLOR_ID_RED>;
++ function = LED_FUNCTION_HEARTBEAT;
+ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+@@ -60,24 +62,22 @@
+ };
+
+ wan_led: led-1 {
+- label = "wan_led";
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_WAN;
+ gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "stmmac-0:01:link";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wan_led_pin>;
+ };
+
+ lan1_led: led-2 {
+- label = "lan1_led";
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_LAN;
+ gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "r8169-3-3100:00:link";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan1_led_pin>;
+ };
+-
+- lan2_led: led-3 {
+- gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
+- pinctrl-names = "default";
+- pinctrl-0 = <&lan2_led_pin>;
+- };
+ };
+
+ vcc_5v0: regulator-vcc-5v0 {
+@@ -328,23 +328,15 @@
+
+ gpio-leds {
+ sys_led_pin: sys-led-pin {
+- rockchip,pins =
+- <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wan_led_pin: wan-led-pin {
+- rockchip,pins =
+- <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ lan1_led_pin: lan1-led-pin {
+- rockchip,pins =
+- <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+- };
+-
+- lan2_led_pin: lan2-led-pin {
+- rockchip,pins =
+- <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++ rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
+@@ -8,6 +8,18 @@
+ model = "FriendlyElec NanoPi R6C";
+ compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588s";
+
++ leds {
++ compatible = "gpio-leds";
++
++ led1_led: led-3 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = "led1";
++ gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&led1_led_pin>;
++ };
++ };
++
+ /* MP2143DJ power switch (U9536 in schematics) */
+ vcc3v3_pcie: regulator-vcc3v3-pcie {
+ compatible = "regulator-fixed";
+@@ -24,16 +36,18 @@
+ };
+ };
+
+-&lan2_led {
+- label = "user_led";
+-};
+-
+ /* M.2 M-Key socket */
+ &pcie2x1l2 {
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ };
+
+ &pinctrl {
++ gpio-leds {
++ led1_led_pin: led1-led-pin {
++ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ pcie {
+ pcie20x1_2_con_pwren: pcie20x1-2-con-pwren {
+ rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
+@@ -7,13 +7,35 @@
+ / {
+ model = "FriendlyElec NanoPi R6S";
+ compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s";
++
++ leds {
++ compatible = "gpio-leds";
++
++ lan2_led: led-3 {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_LAN;
++ function-enumerator = <2>;
++ gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "r8169-4-4100:00:link";
++ pinctrl-names = "default";
++ pinctrl-0 = <&lan2_led_pin>;
++ };
++ };
+ };
+
+-&lan2_led {
+- label = "lan2_led";
++&lan1_led {
++ function-enumerator = <1>;
+ };
+
+ /* RTL8125BG Ethernet */
+ &pcie2x1l2 {
+ vpcie3v3-supply = <&vcc_3v3_s3>;
+ };
++
++&pinctrl {
++ gpio-leds {
++ lan2_led_pin: lan2-led-pin {
++ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++};
--- /dev/null
+From e067643b4e321db4de3274198b13732cce37f5c1 Mon Sep 17 00:00:00 2001
+From: Sebastian Kropatsch <seb-dev@mail.de>
+Date: Wed, 12 Jun 2024 22:48:13 +0200
+Subject: [PATCH 4/5] arm64: dts: rockchip: Enable lower USB3 port on NanoPi
+ R6C/R6S
+
+Enable support for the lower USB 3.0 Type-A port on the NanoPi R6C and
+NanoPi R6S. The upper USB 2.0 Type-A port is already supported.
+
+Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
+---
+ .../boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 28 +++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+@@ -740,6 +740,17 @@
+ status = "okay";
+ };
+
++/* USB2 PHY for USB 3.0 Type-A (lower port)*/
++&u2phy0 {
++ status = "okay";
++};
++
++&u2phy0_otg {
++ phy-supply = <&vcc5v0_usb_otg0>;
++ status = "okay";
++};
++
++/* USB2 PHY for USB 2.0 Type-A (upper port)*/
+ &u2phy2 {
+ status = "okay";
+ };
+@@ -755,10 +766,27 @@
+ status = "okay";
+ };
+
++/* USB 2.0 Type-A (upper port) */
++/* PHY: <&u2phy2_host> */
+ &usb_host0_ehci {
+ status = "okay";
+ };
+
++/* USB 2.0 Type-A (upper port) */
++/* PHY: <&u2phy2_host> */
+ &usb_host0_ohci {
+ status = "okay";
+ };
++
++/* USB 3.0 Type-A (lower port) */
++/* PHYs: <&u2phy0_otg>, <&usbdp_phy0> */
++&usb_host0_xhci {
++ dr_mode = "host";
++ extcon = <&u2phy0>;
++ status = "okay";
++};
++
++/* USB3 PHY for USB 3.0 Type-A (lower port)*/
++&usbdp_phy0 {
++ status = "okay";
++};
--- /dev/null
+From 04cd713c3834b87fcd147e4bf7b7066cfe60fffc Mon Sep 17 00:00:00 2001
+From: Sebastian Kropatsch <seb-dev@mail.de>
+Date: Wed, 12 Jun 2024 22:48:14 +0200
+Subject: [PATCH 5/5] arm64: dts: rockchip: Enable GPU on NanoPi R6C/R6S
+
+Enable the Mali GPU on the FriendlyElec NanoPi R6C and R6S.
+
+Signed-off-by: Sebastian Kropatsch <seb-dev@mail.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+@@ -207,6 +207,12 @@
+ status = "okay";
+ };
+
++&gpu {
++ mali-supply = <&vdd_gpu_s0>;
++ sram-supply = <&vdd_gpu_mem_s0>;
++ status = "okay";
++};
++
+ &i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m2_xfer>;
--- /dev/null
+Nanopi R6: show boot progress on the system LED
+
+Set up openwrt to show boot progress on the nanopi R6S or R6C system LED.
+
+The LED blinking states indicate the boot stage. The led is defined as
+a power LED, but can still be set to heartbeat in /etc/config/system
+after the system is done booting.
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+@@ -16,6 +16,10 @@
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc;
+ mmc1 = &sdhci;
++ led-boot = &sys_led;
++ led-failsafe = &sys_led;
++ led-running = &sys_led;
++ led-upgrade = &sys_led;
+ };
+
+ chosen {
+@@ -54,9 +58,9 @@
+
+ sys_led: led-0 {
+ color = <LED_COLOR_ID_RED>;
+- function = LED_FUNCTION_HEARTBEAT;
++ function = LED_FUNCTION_POWER;
+ gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
+- linux,default-trigger = "heartbeat";
++ default-state = "on";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sys_led_pin>;
+ };
--- /dev/null
+Nanopi R6: set up reset button to be handled by openwrt
+
+Set up openwrt to handle the reset button appropriately (so that it
+can trigger the various recovery modes) on the nanopi R6S and R6C models.
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+@@ -48,8 +48,8 @@
+ button-user {
+ debounce-interval = <50>;
+ gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>;
+- label = "User Button";
+- linux,code = <BTN_1>;
++ label = "reset";
++ linux,code = <KEY_RESTART>;
+ };
+ };
+
--- /dev/null
+From 95147bb42bc163866fc103c957820345fefa96cd Mon Sep 17 00:00:00 2001
+From: Anton Kirilov <anton.kirilov@arm.com>
+Date: Thu, 19 Dec 2024 11:31:45 +0000
+Subject: [PATCH] arm64: dts: rockchip: Fix the SD card detection on NanoPi
+ R6C/R6S
+
+Fix the SD card detection on FriendlyElec NanoPi R6C/R6S boards.
+
+Signed-off-by: Anton Kirilov <anton.kirilov@arm.com>
+Link: https://lore.kernel.org/r/20241219113145.483205-1-anton.kirilov@arm.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6.dtsi
+@@ -410,6 +410,7 @@
+ &sdmmc {
+ bus-width = <4>;
+ cap-sd-highspeed;
++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ max-frequency = <150000000>;
+ no-mmc;
projects / thirdparty / openwrt.git / commitdiff
