hw/timer/mss_timer: Remove dead code in timer_write()

In timer_write(), we switch() on the address offset to handle
registers that need special-casing, with a default case that handles
both "unsupported (64-bit mode) register" and "can just write value
to st->regs[]".  However, as Coverity points out, every register is
covered by the special-casing, so the "write to st->regs[]" code path
is dead.  (timer_read() has a similar structure but there several
registers do go through the default code path.)

Replace the dead code with an assertion.

CID: 1613905
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260512134750.3543639-1-peter.maydell@linaro.org

diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c
index bd3f3e845fd87758eab2653c61623a684936adde..25fcf42aa02aa8e76832fa6e225f872745df5545 100644 (file)
--- a/hw/timer/mss-timer.c
+++ b/hw/timer/mss-timer.c
@@ -189,14 +189,11 @@ timer_write(void *opaque, hwaddr offset,
         break;
 
     default:
-        if (addr < R_TIM1_MAX) {
-            st->regs[addr] = value;
-        } else {
-            qemu_log_mask(LOG_GUEST_ERROR,
-                        TYPE_MSS_TIMER": 64-bit mode not supported\n");
-            return;
-        }
-        break;
+        /* All non-64-bit regs covered by the switch cases */
+        assert(addr >= R_TIM1_MAX);
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      TYPE_MSS_TIMER": 64-bit mode not supported\n");
+        return;
     }
     timer_update_irq(st);
 }