* point a bit earlier in the sequence. If we had
* generated a reset a short time ago, we'll wait for
* the link timer to check the status until a
- * timer expires (link_transistion_jiffies_valid is
+ * timer expires (link_transition_jiffies_valid is
* true when the timer is running.) Instead of using
* a system timer, we just do a check whenever the
* link timer is running - this clears the flag after
}
if (linkstate != link_up) {
/* Force these to "unknown" if the link is not up and
- * autonogotiation in enabled. We can set the link
+ * autonegotiation is enabled. We can set the link
* speed to 0, but not cmd->duplex,
* because its legal values are 0 and 1. Ethtool will
* print the value reported in parentheses after the
*/
pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff);
- /* The Read Prefecth Policy register is 16-bit and sits at
+ /* The Read Prefetch Policy register is 16-bit and sits at
* offset 0x52. It enables a "smart" pre-fetch policy. We
* enable it and max out all of the settings since only one
* device is sitting underneath and thus bandwidth sharing is
/*
* On some architectures, the default cache line size set
- * by pci_try_set_mwi reduces perforamnce. We have to increase
+ * by pci_try_set_mwi reduces performance. We have to increase
* it for this case. To start, we'll print some configuration
* data.
*/
/* output enables are provided for each device's chip select and for the rest
* of the outputs from cassini to its local bus devices. two sw programmable
- * bits are connected to general purpus control/status bits.
+ * bits are connected to general purpose control/status bits.
* DEFAULT: 0x7
*/
#define REG_BIM_LOCAL_DEV_EN 0x1020 /* BIM local device
GMII on SERDES pins for
monitoring. */
#define SATURN_PCFG_FSI 0x00000200 /* 1 = freeze serdes/gmii. all
- pins configed as outputs.
+ pins configured as outputs.
for power saving when using
internal phy. */
#define SATURN_PCFG_LAD 0x00000800 /* 0 = mac core led ctrl
enabled */
#define RX_CFG_SWIVEL_MASK 0x00001C00 /* byte offset of the 1st
data byte of the packet
- w/in 8 byte boundares.
+ w/in 8 byte boundaries.
this swivels the data
DMA'ed to header
buffers, jumbo buffers
*/
#define REG_MAC_TX_STATUS 0x6010 /* TX MAC status reg */
#define MAC_TX_FRAME_XMIT 0x0001 /* successful frame
- transmision */
+ transmission */
#define MAC_TX_UNDERRUN 0x0002 /* terminated frame
transmission due to
data starvation in the
* when passed to the host. to ensure proper operation, need to wait 3.2ms
* after clearing RX_CFG_EN before writing to any other RX MAC registers
* or other MAC parameters. alternatively, poll RX_CFG_EN until it clears
- * to 0. similary, HASH_FILTER_EN and ADDR_FILTER_EN have the same
+ * to 0. Similarly, HASH_FILTER_EN and ADDR_FILTER_EN have the same
* restrictions as CFG_EN.
*/
#define REG_MAC_RX_CFG 0x6034 /* RX MAC config reg */
* programmed in frame mode. load this register w/ a valid instruction
* (as per IEEE 802.3u MII spec). poll this register to check for instruction
* execution completion. during a read operation, this register will also
- * contain the 16-bit data returned by the tranceiver. unless specified
+ * contain the 16-bit data returned by the transceiver. unless specified
* otherwise, fields are considered "don't care" when polling for
* completion.
*/
#define MIF_CFG_POLL_REG_SHIFT 3
#define MIF_CFG_MDIO_0 0x0100 /* (ro) dual purpose.
when MDIO_0 is idle,
- 1 -> tranceiver is
+ 1 -> transceiver is
connected to MDIO_0.
when MIF is communicating
w/ MDIO_0 in bit-bang
mode, this bit indicates
the incoming bit stream
during a read op */
-#define MIF_CFG_POLL_PHY_MASK 0x7C00 /* tranceiver address to
+#define MIF_CFG_POLL_PHY_MASK 0x7C00 /* transceiver address to
be polled */
#define MIF_CFG_POLL_PHY_SHIFT 10
#define FRAME_WRITE 0x50020000
#define FRAME_READ 0x60020000
-/* Tranceiver registers. */
+/* Transceiver registers. */
#define TCVR_PAL_SERIAL 0x00000001 /* Enable serial mode */
#define TCVR_PAL_EXTLBACK 0x00000002 /* Enable external loopback */
#define TCVR_PAL_MSENSE 0x00000004 /* Media sense */
* if we did. This is not an issue however as the reset
* task is synchronized vs. us (rtnl_lock) and will do
* nothing if the device is down or suspended. We do
- * still clear reset_task_pending to avoid a spurrious
+ * still clear reset_task_pending to avoid a spurious
* reset later on in case we do resume before it gets
* scheduled.
*/
gem_do_start(dev);
/* If we had WOL enabled, the cell clock was never turned off during
- * sleep, so we end up beeing unbalanced. Fix that here
+ * sleep, so we end up being unbalanced. Fix that here
*/
if (gp->asleep_wol)
gem_put_cell(gp);
#define MAC_HASH14 0x60F8UL /* Hash Table 14 Register */
#define MAC_HASH15 0x60FCUL /* Hash Table 15 Register */
#define MAC_NCOLL 0x6100UL /* Normal Collision Counter */
-#define MAC_FASUCC 0x6104UL /* First Attmpt. Succ Coll Ctr. */
+#define MAC_FASUCC 0x6104UL /* First Attempt. Succ Coll Ctr.*/
#define MAC_ECOLL 0x6108UL /* Excessive Collision Counter */
#define MAC_LCOLL 0x610CUL /* Late Collision Counter */
#define MAC_DTIMER 0x6110UL /* Defer Timer */
/* MIF Frame/Output Register. This 32-bit register allows the host to
* communicate with a transceiver in frame mode (as opposed to big-bang
- * mode). Writes by the host specify an instrution. After being issued
+ * mode). Writes by the host specify an instruction. After being issued
* the host must poll this register for completion. Also, after
* completion this register holds the data returned by the transceiver
* if applicable.
*
* We use skb_reserve() to align the data block we get in the skb. We
* also program the etxregs->cfg register to use an offset of 2. This
- * imperical constant plus the ethernet header size will always leave
+ * empirical constant plus the ethernet header size will always leave
* us with a nicely aligned ip header once we pass things up to the
* protocol layers.
*
projects / thirdparty / kernel / linux.git / commitdiff
