drm/amd/display: add pstate schedule admissibility flags and frame-time utility

[Why]
Core needs to track pstate schedule admissibility for different global
change scenarios (fclk, temp read, PPT) and requires a reusable way to compute
per-stream frame time from timing parameters.

[How]
Extend dml2_core_internal_mode_support_info with:
fclk_pstate_schedule_admissible
temp_read_pstate_schedule_admissible
ppt_pstate_schedule_admissible
Add dummy_double_array[3][DML2_MAX_PLANES] to
dml2_core_calcs_mode_support_locals.
Introduce dml2_core_utils_get_frame_time_us() in dml2_core_utils.c and export
it in dml2_core_utils.h to compute frame time in microseconds from stream
timing (vline time * (vactive + vblank)).

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h
index 987b29808ca4a938d242696fcf107266179baa1c..080bc3c3d2447cd1121e9054978f1d8af22d1c47 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_shared_types.h
@@ -269,6 +269,9 @@ struct dml2_core_internal_mode_support_info {
        bool global_dram_clock_change_supported;
        bool global_fclk_change_supported;
        bool global_temp_read_or_ppt_supported;
+       bool fclk_pstate_schedule_admissible;
+       bool temp_read_pstate_schedule_admissible;
+       bool ppt_pstate_schedule_admissible;
        bool USRRetrainingSupport;
        bool AvgBandwidthSupport;
        bool UrgVactiveBandwidthSupport;
@@ -1063,6 +1066,8 @@ struct dml2_core_calcs_mode_support_locals {
        bool dummy_boolean_array[2][DML2_MAX_PLANES];
        double dummy_single[3];
        double dummy_single_array[DML2_MAX_PLANES];
+       double dummy_double_array[3][DML2_MAX_PLANES];
+       enum dml2_pstate_method dummy_pstate_method_array[DML2_MAX_PLANES];
        struct dml2_core_internal_watermarks dummy_watermark;
        double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max];
        double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES];

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
index 5dc846802c534afc29338078563e967815d87f44..4f5533dc043095ec92c774d0c9ec0f25beda5c02 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.c
@@ -786,3 +786,11 @@ bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode)
                return false;
        }
 }
+
+double dml2_core_utils_get_frame_time_us(const struct dml2_stream_parameters *stream)
+{
+       double otg_vline_time_us = (double)stream->timing.h_total / (double)stream->timing.pixel_clock_khz * 1000.0;
+       double non_vtotal = stream->timing.vblank_nom + stream->timing.v_active;
+       double frame_time_us = non_vtotal * otg_vline_time_us;
+       return frame_time_us;
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h
index 95f0d017add455f57aff99b48ed8dffc18096822..60fa2abfef85028e4ec0389d56ac36762ee4f181 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_utils.h
@@ -39,5 +39,6 @@ bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stre
 bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate);
 bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate);
 bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode);
+double dml2_core_utils_get_frame_time_us(const struct dml2_stream_parameters *stream);
 
 #endif /* __DML2_CORE_UTILS_H__ */