arm64: dts: renesas: r9a09g087: Add xSPI nodes

Add device tree nodes for the two xSPI (Expanded SPI) controllers
integrated into the RZ/N2H (R9A09G087) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260526204045.3481604-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index c64b532f3d234d6547d7e78967da4f10a203f580..e8d4f76949ccb2fbd056c822fa76c563ee0f3dd4 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -1009,6 +1009,46 @@
                        };
                };
 
+               xspi0: spi@801c0000 {
+                       compatible = "renesas,r9a09g087-xspi",
+                                    "renesas,r9a09g047-xspi";
+                       reg = <0 0x801c0000 0 0x1000>,
+                             <0 0x40000000 0 0x10000000>;
+                       reg-names = "regs", "dirmap";
+                       interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pulse", "err_pulse";
+                       clocks = <&cpg CPG_MOD 4>,
+                                <&cpg CPG_CORE R9A09G087_XSPI_CLK0>;
+                       clock-names = "ahb", "spi";
+                       resets = <&cpg 4>;
+                       reset-names = "hresetn";
+                       power-domains = <&cpg>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               xspi1: spi@801c1000 {
+                       compatible = "renesas,r9a09g087-xspi",
+                                    "renesas,r9a09g047-xspi";
+                       reg = <0 0x801c1000 0 0x1000>,
+                             <0 0x50000000 0 0x10000000>;
+                       reg-names = "regs", "dirmap";
+                       interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "pulse", "err_pulse";
+                       clocks = <&cpg CPG_MOD 5>,
+                                <&cpg CPG_CORE R9A09G087_XSPI_CLK1>;
+                       clock-names = "ahb", "spi";
+                       resets = <&cpg 5>;
+                       reset-names = "hresetn";
+                       power-domains = <&cpg>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
                cpg: clock-controller@80280000 {
                        compatible = "renesas,r9a09g087-cpg-mssr";
                        reg = <0 0x80280000 0 0x10000>,