AMD/Xilinx/FPGA changes for v2026.10-rc1 v3
AMD:
- Firmware interface decoupling (part 1)
ZynqMP:
- DT updates
- Add TCG variant detection
Versal/Versal2:
- Drop DDR MMU mapping and map it dynamically
tools:
- Add register initialization to mkimage
MAINTAINERS:
- Clean Zynq/ZynqMP fragments
ufs:
- Fix driver reregistration
fpga:
- altera: Simplify driver conditional compilation selection