clk: mediatek: mt8512: convert CLK_XTAL to CLK_PAD_CLK26M

Replace all uses of CLK_XTAL with CLK_PAD_CLK26M.

This avoids declaring the same parent clock two different ways and will
eventually let us remove CLK_PARENT_XTAL completely.

Reviewed-by: Julien Stephan <jstephan@baylibre.com>
Link: https://patch.msgid.link/20260310-clk-mtk-parent-cleanup-v1-13-66175ca8f637@baylibre.com
Signed-off-by: David Lechner <dlechner@baylibre.com>

diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
index f7d41f4cfdbb70c9d22d7a9e06b2f3742d36f40e..d6e58be8e22e4ef33f2293a8d7d559569d644d1c 100644 (file)
--- a/drivers/clk/mediatek/clk-mt8512.c
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -68,7 +68,7 @@ static const struct mtk_pll_data apmixed_plls[] = {
 
 /* topckgen */
 #define FIXED_CLK0(_id, _rate)                 \
-       FIXED_CLK(_id, CLK_XTAL, CLK_PARENT_XTAL, _rate)
+       FIXED_CLK(_id, CLK_PAD_CLK26M, CLK_PARENT_EXT, _rate)
 
 #define FACTOR0(_id, _parent, _mult, _div)     \
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
@@ -77,7 +77,7 @@ static const struct mtk_pll_data apmixed_plls[] = {
        FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
 
 #define FACTOR2(_id, _parent, _mult, _div)     \
-       FACTOR(_id, _parent, _mult, _div, CLK_PARENT_XTAL)
+       FACTOR(_id, _parent, _mult, _div, CLK_PARENT_EXT)
 
 static const struct mtk_fixed_clk top_fixed_clks[] = {
        FIXED_CLK0(CLK_TOP_CLK_NULL, 26000000),
@@ -130,8 +130,8 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
        FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4),
        FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8),
        FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16),
-       FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
-       FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2),
+       FACTOR2(CLK_TOP_CLK26M, CLK_PAD_CLK26M, 1, 1),
+       FACTOR2(CLK_TOP_SYS_26M_D2, CLK_PAD_CLK26M, 1, 2),
        FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
        FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
        FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1),
@@ -793,7 +793,6 @@ static const struct mtk_gate infra_clks[] = {
 };
 
 static const struct mtk_clk_tree mt8512_clk_tree = {
-       .xtal_rate = 26 * MHZ,
        .pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
        .ext_clk_rates = ext_clock_rates,
        .num_ext_clks = ARRAY_SIZE(ext_clock_rates),