target/arm: GICv5 cpuif: Implement ICC_APR_EL1 and ICC_HAPR_EL1

The ICC_APR_EL1 GICv5 cpuif register records the physical active
priorities.  Since the GICv5 always uses 5 bits of priority, this
register always has 32 non-RES0 bits, and we don't need the
complicated GICv3 setup where there might be 1, 2 or 4 APR registers.

ICC_HAPR_EL1 is a read-only register which reports the current
running priority.  This is defined to be the lowest set bit (i.e.
the highest priority) in the APR, or the Idle priority 0xff if there
are no active interrupts, so it is effectively a convenience
re-presentation of the APR register data.

The APR register is banked per interrupt domain; ICC_APR_EL1 accesses
the version of the register corresponding to the current logical
interrupt domain.  The APR data for the final domain (EL3) is
accessed via ICC_APR_EL3.  Although we are starting with an EL1-only
implementation, we define the CPU state as banked here so we don't
have to change our representation of it later when we add EL3 and RME
support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Message-id: 20260327111700.795099-42-peter.maydell@linaro.org

diff --git a/include/hw/intc/arm_gicv5_types.h b/include/hw/intc/arm_gicv5_types.h
index f6f8709a6a72f4d69294b9ee245e679629bd6824..5966ebde050b2bd04a7c827af25db119d69605d3 100644 (file)
--- a/include/hw/intc/arm_gicv5_types.h
+++ b/include/hw/intc/arm_gicv5_types.h
@@ -84,4 +84,6 @@ typedef enum GICv5TriggerMode {
     GICV5_TRIGGER_LEVEL = 1,
 } GICv5TriggerMode;
 
+#define PRIO_IDLE 0xff
+
 #endif

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cf7f8f8facf70f199480002849e847dd833de935..76db5a9197e7efa97d474471c0b172cccbf7f8ff 100644 (file)
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -34,6 +34,7 @@
 #include "target/arm/gtimer.h"
 #include "target/arm/cpu-sysregs.h"
 #include "target/arm/mmuidx.h"
+#include "hw/intc/arm_gicv5_types.h"
 
 #define EXCP_UDEF            1   /* undefined instruction */
 #define EXCP_SWI             2   /* software interrupt */
@@ -602,6 +603,7 @@ typedef struct CPUArchState {
     struct {
         /* GICv5 CPU interface data */
         uint64_t icc_icsr_el1;
+        uint64_t icc_apr[NUM_GICV5_DOMAINS];
         /* Most PPI registers have 1 bit per PPI, so 64 PPIs to a register */
         uint64_t ppi_active[GICV5_NUM_PPIS / 64];
         uint64_t ppi_hm[GICV5_NUM_PPIS / 64];

diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c
index 74132ca097fd3716f115eb9014a9331544021c35..33e4762ef47d0e0a591ac1655493c8961fa4824f 100644 (file)
--- a/target/arm/tcg/gicv5-cpuif.c
+++ b/target/arm/tcg/gicv5-cpuif.c
@@ -95,6 +95,16 @@ static GICv5Domain gicv5_current_phys_domain(CPUARMState *env)
     return gicv5_logical_domain(env);
 }
 
+static uint64_t gic_running_prio(CPUARMState *env, GICv5Domain domain)
+{
+    /*
+     * Return the current running priority; this is the lowest set bit in
+     * the Active Priority Register, or the idle priority if none (D_XMBQZ)
+     */
+    uint64_t hap = ctz64(env->gicv5_cpuif.icc_apr[domain]);
+    return hap < 32 ? hap : PRIO_IDLE;
+}
+
 static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri,
                             uint64_t value)
 {
@@ -231,6 +241,44 @@ static void gic_ppi_priority_write(CPUARMState *env, const ARMCPRegInfo *ri,
     raw_write(env, ri, value);
 }
 
+/*
+ * ICC_APR_EL1 is banked and reads/writes as the version for the
+ * current logical interrupt domain.
+ */
+static void gic_icc_apr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                  uint64_t value)
+{
+    /*
+     * With an architectural 5 bits of priority, this register has 32
+     * non-RES0 bits
+     */
+    GICv5Domain domain = gicv5_logical_domain(env);
+    value &= 0xffffffff;
+    env->gicv5_cpuif.icc_apr[domain] = value;
+}
+
+static uint64_t gic_icc_apr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    GICv5Domain domain = gicv5_logical_domain(env);
+    return env->gicv5_cpuif.icc_apr[domain];
+}
+
+static void gic_icc_apr_el1_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    for (int i = 0; i < ARRAY_SIZE(env->gicv5_cpuif.icc_apr); i++) {
+        env->gicv5_cpuif.icc_apr[i] = 0;
+    }
+}
+
+static uint64_t gic_icc_hapr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    /*
+     * ICC_HAPR_EL1 reports the current running priority, which can be
+     * calculated from the APR register.
+     */
+    return gic_running_prio(env, gicv5_current_phys_domain(env));
+}
+
 static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
     /*
      * Barrier: wait until the effects of a cpuif system register
@@ -382,6 +430,18 @@ static const ARMCPRegInfo gicv5_cpuif_reginfo[] = {
         .fieldoffset = offsetof(CPUARMState, gicv5_cpuif.ppi_pend[1]),
         .writefn = gic_ppi_spend_write,
     },
+    {   .name = "ICC_APR_EL1", .state = ARM_CP_STATE_AA64,
+        .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 0,
+        .access = PL1_RW, .type = ARM_CP_IO | ARM_CP_NO_RAW,
+        .readfn = gic_icc_apr_el1_read,
+        .writefn = gic_icc_apr_el1_write,
+        .resetfn = gic_icc_apr_el1_reset,
+    },
+    {   .name = "ICC_HAPR_EL1", .state = ARM_CP_STATE_AA64,
+        .opc0 = 3, .opc1 = 1, .crn = 12, .crm = 0, .opc2 = 3,
+        .access = PL1_R, .type = ARM_CP_IO | ARM_CP_NO_RAW,
+        .readfn = gic_icc_hapr_el1_read, .raw_writefn = arm_cp_write_ignore,
+    },
 };
 
 void define_gicv5_cpuif_regs(ARMCPU *cpu)