if (regname[0] != 'c' && regname[0] != 'a')
{
regnum = reg_name_search (regname);
- if (regname[0] == 'f' && regnum != -1)
+ if ((regname[0] == 'f' || regname[0] == 'v') && regnum != -1)
{
- /* Convert from floating-point register number (0..15)
- * to DWARF floating point register number (15..31):
- * Right rotate the least significant three bits and add 16. */
+ /* Convert from floating-point register number (0..15) and
+ * vector register number (0..31) to DWARF register number
+ * (15..31, 68..83): Right rotate the least significant
+ * three bits. For floating-point registers add 16. For
+ * vector registers 0..15 add 16 and for 16..31 add 86. */
int dw2_regnum;
dw2_regnum = (regnum & 0b110) >> 1;
dw2_regnum |= (regnum & 0b1) << 2;
dw2_regnum |= (regnum & 0b1000);
- dw2_regnum += 16;
+ dw2_regnum += (regnum < 16) ? 16 : 68;
regnum = dw2_regnum;
}
}
# Invalid floating-point register names
.*:7: Error: bad register expression
.*:8: Error: bad register expression
+# Invalid vector register names
+.*:10: Error: bad register expression
+.*:11: Error: bad register expression
# Invalid floating-point register names
.cfi_register f0, f16
.cfi_register %f0, %f16
+# Invalid vector register names
+ .cfi_register v0, v32
+ .cfi_register %v0, %v32
.cfi_endproc
DW_CFA_register: r27 \(f14\) in r31 \(f15\)
DW_CFA_nop
DW_CFA_nop
+
+# Vector register (VR) names v0..v31
+00000070 0000000000000044 00000074 FDE cie=00000000 pc=0000000000000008..000000000000000c
+ DW_CFA_advance_loc: 2 to 000000000000000a
+ DW_CFA_register: r16 \(f0\) in r20 \(f1\)
+ DW_CFA_register: r17 \(f2\) in r21 \(f3\)
+ DW_CFA_register: r18 \(f4\) in r22 \(f5\)
+ DW_CFA_register: r19 \(f6\) in r23 \(f7\)
+ DW_CFA_register: r24 \(f8\) in r28 \(f9\)
+ DW_CFA_register: r25 \(f10\) in r29 \(f11\)
+ DW_CFA_register: r26 \(f12\) in r30 \(f13\)
+ DW_CFA_register: r27 \(f14\) in r31 \(f15\)
+ DW_CFA_register: r68 \(v16\) in r72 \(v17\)
+ DW_CFA_register: r69 \(v18\) in r73 \(v19\)
+ DW_CFA_register: r70 \(v20\) in r74 \(v21\)
+ DW_CFA_register: r71 \(v22\) in r75 \(v23\)
+ DW_CFA_register: r76 \(v24\) in r80 \(v25\)
+ DW_CFA_register: r77 \(v26\) in r81 \(v27\)
+ DW_CFA_register: r78 \(v28\) in r82 \(v29\)
+ DW_CFA_register: r79 \(v30\) in r83 \(v31\)
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
+ DW_CFA_nop
.word 0
.cfi_endproc
.size fpr, .-fpr
+# Vector register (VR) names v0..v31
+ .type vr, @function
+vr:
+ .cfi_startproc
+ .word 0
+ .cfi_register v0, v1
+ .cfi_register v2, v3
+ .cfi_register v4, v5
+ .cfi_register v6, v7
+ .cfi_register v8, v9
+ .cfi_register v10, v11
+ .cfi_register v12, v13
+ .cfi_register v14, v15
+ .cfi_register v16, v17
+ .cfi_register v18, v19
+ .cfi_register v20, v21
+ .cfi_register v22, v23
+ .cfi_register v24, v25
+ .cfi_register v26, v27
+ .cfi_register v28, v29
+ .cfi_register v30, v31
+ .word 0
+ .cfi_endproc
+ .size vr, .-vr