x86/cpufeatures: Add SEV-ES CPU feature

commit 360e7c5c4ca4fd8e627781ed42f95d58bc3bb732 upstream.

Add CPU feature detection for Secure Encrypted Virtualization with
Encrypted State. This feature enhances SEV by also encrypting the
guest register state, making it in-accessible to the hypervisor.

Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200907131613.12703-6-joro@8bytes.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index a64c7ea19383cd7f0dc4bdc87e753e583580548c..474b2c34879f4826cf860c0af6deb0cd5f5cac03 100644 (file)
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -235,6 +235,7 @@
 #define X86_FEATURE_EPT_AD             ( 8*32+17) /* Intel Extended Page Table access-dirty bit */
 #define X86_FEATURE_VMCALL             ( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
 #define X86_FEATURE_VMW_VMMCALL                ( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
+#define X86_FEATURE_SEV_ES             ( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
 #define X86_FEATURE_FSGSBASE           ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 3f182c06b305c11efe803d80a523ac5250e8ec80..11f09df72f51ac7a4d6434589df996ceb0674aa8 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -663,7 +663,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
         *            If BIOS has not enabled SME then don't advertise the
         *            SME feature (set in scattered.c).
         *   For SEV: If BIOS has not enabled SEV then don't advertise the
-        *            SEV feature (set in scattered.c).
+        *            SEV and SEV_ES feature (set in scattered.c).
         *
         *   In all cases, since support for SME and SEV requires long mode,
         *   don't advertise the feature under CONFIG_X86_32.
@@ -694,6 +694,7 @@ clear_all:
                setup_clear_cpu_cap(X86_FEATURE_SME);
 clear_sev:
                setup_clear_cpu_cap(X86_FEATURE_SEV);
+               setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
        }
 }
 

diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index a03e309a0ac5f401efc1c291691d26435c720cd8..d8d94c199509251319ccac64bf3589d7802090c6 100644 (file)
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -42,6 +42,7 @@ static const struct cpuid_bit cpuid_bits[] = {
        { X86_FEATURE_MBA,              CPUID_EBX,  6, 0x80000008, 0 },
        { X86_FEATURE_SME,              CPUID_EAX,  0, 0x8000001f, 0 },
        { X86_FEATURE_SEV,              CPUID_EAX,  1, 0x8000001f, 0 },
+       { X86_FEATURE_SEV_ES,           CPUID_EAX,  3, 0x8000001f, 0 },
        { X86_FEATURE_SME_COHERENT,     CPUID_EAX, 10, 0x8000001f, 0 },
        { 0, 0, 0, 0, 0 }
 };