Properly disable the "water" in isc_mem

The proper way how to disable the water limit in the isc_mem context is
to call:

    isc_mem_setwater(ctx, NULL, NULL, 0, 0);

this ensures that the old water callback is called with ISC_MEM_LOWATER
if the callback was called with ISC_MEM_HIWATER before.

Historically, there were some places where the limits were disabled by
calling:

    isc_mem_setwater(ctx, water, water_arg, 0, 0);

which would also call the old callback, but it also causes the water_t
to be allocated and extra check to be executed because water callback is
not NULL.

This commits unifies the calls to disable water to the preferred form.

diff --git a/lib/dns/adb.c b/lib/dns/adb.c
index defb75c44cea96ad0f7d02cd0564fb54ac578440..6b1bddad636c67cf4ed2622d23642756ab5e9f2e 100644 (file)
--- a/lib/dns/adb.c
+++ b/lib/dns/adb.c
@@ -2869,7 +2869,7 @@ dns_adb_shutdown(dns_adb_t *adb) {
 
        if (!adb->shutting_down) {
                adb->shutting_down = true;
-               isc_mem_setwater(adb->mctx, water, adb, 0, 0);
+               isc_mem_setwater(adb->mctx, NULL, NULL, 0, 0);
                /*
                 * Isolate shutdown_names and shutdown_entries calls.
                 */
@@ -4699,7 +4699,7 @@ dns_adb_setadbsize(dns_adb_t *adb, size_t size) {
        lowater = size - (size >> 2); /* Approximately 3/4ths. */
 
        if (size == 0U || hiwater == 0U || lowater == 0U) {
-               isc_mem_setwater(adb->mctx, water, adb, 0, 0);
+               isc_mem_setwater(adb->mctx, NULL, NULL, 0, 0);
        } else {
                isc_mem_setwater(adb->mctx, water, adb, hiwater, lowater);
        }

diff --git a/lib/dns/cache.c b/lib/dns/cache.c
index 9935275d8f66e643638dd8ea804e735b7ce22727..bf73300c0584db15bb6ed00b757b9b95481c6a0d 100644 (file)
--- a/lib/dns/cache.c
+++ b/lib/dns/cache.c
@@ -950,7 +950,7 @@ dns_cache_setcachesize(dns_cache_t *cache, size_t size) {
                /*
                 * Disable cache memory limiting.
                 */
-               isc_mem_setwater(cache->mctx, water, cache, 0, 0);
+               isc_mem_setwater(cache->mctx, NULL, NULL, 0, 0);
        } else {
                /*
                 * Establish new cache memory limits (either for the first