drm/amdgpu/vce1: Check that the GPU address is < 128 MiB

When ensuring the low 32-bit address, make sure it is
less than 128 MiB, otherwise the VCE seems to fail to initialize.
This seems to be an undocumented limitation of the firmware
validation mechanism. Note that in case of VCE1 the BAR
address is zero and we can't change it also due to the
firmware validator.

When programming the mmVCE_VCPU_CACHE_OFFSETn registers,
don't AND them with a mask. This is incorrect because
the register mask is actually 0x0fffffff and useless because
we already ensure the addresses are below the limit.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit e729ae5f3ac73c861c062080ac8c3d666c972404)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
index 5b7b46d242c6d794e7ffda621c63b5ed55c8dea8..edabec442cb637cb2116f4f8a14a48efe6dd9eba 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v1_0.c
@@ -313,17 +313,17 @@ static int vce_v1_0_mc_resume(struct amdgpu_device *adev)
 
        offset =  adev->vce.gpu_addr + AMDGPU_VCE_FIRMWARE_OFFSET;
        size = VCE_V1_0_FW_SIZE;
-       WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
+       WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset);
        WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
 
        offset += size;
        size = VCE_V1_0_STACK_SIZE;
-       WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
+       WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset);
        WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
 
        offset += size;
        size = VCE_V1_0_DATA_SIZE;
-       WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
+       WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset);
        WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
 
        WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100);
@@ -527,11 +527,15 @@ static int vce_v1_0_early_init(struct amdgpu_ip_block *ip_block)
  * To accomodate that, we put GART to the LOW address range
  * and reserve some GART pages where we map the VCPU BO,
  * so that it gets a 32-bit address.
+ *
+ * The BAR address is zero and we can't change it
+ * due to the firmware validation mechanism.
+ * It seems that it fails to initialize if the address is >= 128 MiB.
  */
 static int vce_v1_0_ensure_vcpu_bo_32bit_addr(struct amdgpu_device *adev)
 {
        u64 bo_size = amdgpu_bo_size(adev->vce.vcpu_bo);
-       u64 max_vcpu_bo_addr = 0xffffffff - bo_size;
+       u64 max_vcpu_bo_addr = 0x07ffffff - bo_size;
        u64 num_pages = ALIGN(bo_size, AMDGPU_GPU_PAGE_SIZE) / AMDGPU_GPU_PAGE_SIZE;
        u64 pa = amdgpu_gmc_vram_pa(adev, adev->vce.vcpu_bo);
        u64 flags = AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE | AMDGPU_PTE_VALID;