drm/ast: Use constants for WDT registers

WDT is the Watchdog timer. WDC registers are located at the memory
range at [0x1e785000, 0x1e785fff]. There are currently up to 8
watchdog timers in the range, of which 2 are being used by AST2500.

Refer to them with macros named AST_REG_WDT<n>, where <n> is the byte
offset into the watchdog timer's memory range. Each macro also takes
the index of the watchdog timer to access. A new watchdog timer starts
at each 0x40 byte offset.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://patch.msgid.link/20260327133532.79696-8-tzimmermann@suse.de

diff --git a/drivers/gpu/drm/ast/ast_2500.c b/drivers/gpu/drm/ast/ast_2500.c
index d141b34548a9aba47372a8de35732296ef076fd6..f0639f1ef062a8cd2845f7cffa95b7c602bc8796 100644 (file)
--- a/drivers/gpu/drm/ast/ast_2500.c
+++ b/drivers/gpu/drm/ast/ast_2500.c
@@ -127,9 +127,9 @@ void ast_2500_patch_ahb(void __iomem *regs)
                 *      [1]:= 1:WDT will be cleeared and disabled after timeout occurs
                 *      [0]:= 1:WDT enable
                 */
-               __ast_moutdwm(regs, 0x1E785004, 0x00000010);
-               __ast_moutdwm(regs, 0x1E785008, 0x00004755);
-               __ast_moutdwm(regs, 0x1E78500c, 0x00000033);
+               __ast_moutdwm(regs, AST_REG_WDT04(0), 0x00000010);
+               __ast_moutdwm(regs, AST_REG_WDT08(0), 0x00004755);
+               __ast_moutdwm(regs, AST_REG_WDT0C(0), 0x00000033);
                udelay(1000);
        }
 
@@ -304,12 +304,12 @@ static void set_mpll_2500(struct ast_device *ast)
 
 static void reset_mmc_2500(struct ast_device *ast)
 {
-       ast_moutdwm(ast, 0x1E78505C, 0x00000004);
-       ast_moutdwm(ast, 0x1E785044, 0x00000001);
-       ast_moutdwm(ast, 0x1E785048, 0x00004755);
-       ast_moutdwm(ast, 0x1E78504C, 0x00000013);
+       ast_moutdwm(ast, AST_REG_WDT1C(1), 0x00000004);
+       ast_moutdwm(ast, AST_REG_WDT04(1), 0x00000001);
+       ast_moutdwm(ast, AST_REG_WDT08(1), 0x00004755);
+       ast_moutdwm(ast, AST_REG_WDT0C(1), 0x00000013);
        mdelay(100);
-       ast_moutdwm(ast, 0x1E785054, 0x00000077);
+       ast_moutdwm(ast, AST_REG_WDT14(1), 0x00000077);
        ast_moutdwm(ast, AST_REG_MCR00, AST_REG_MCR00_PROTECTION_KEY);
 }
 
@@ -508,8 +508,8 @@ static void ast_post_chip_2500(struct ast_device *ast)
                ast_2500_patch_ahb(ast->regs);
 
                /* Disable watchdog */
-               ast_moutdwm(ast, 0x1E78502C, 0x00000000);
-               ast_moutdwm(ast, 0x1E78504C, 0x00000000);
+               ast_moutdwm(ast, AST_REG_WDT2C(0), 0x00000000);
+               ast_moutdwm(ast, AST_REG_WDT0C(1), 0x00000000);
 
                /*
                 * Reset USB port to patch USB unknown device issue

diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h
index 730072a3c2cd166bddce1abdd46fb1c3081b8f41..5effe6897b51a37fd937d6b3e4baad20025abc25 100644 (file)
--- a/drivers/gpu/drm/ast/ast_reg.h
+++ b/drivers/gpu/drm/ast/ast_reg.h
@@ -196,4 +196,17 @@
 #define AST_REG_A2P(__offset)                  (AST_REG_A2P_BASE + (__offset))
 #define AST_REG_A2P58                          AST_REG_A2P(0x58)
 
+/*
+ * Watchdog timer (0x1e785000 - 0x1e785fff)
+ */
+
+#define AST_REG_WDT_BASE(__n)                  (0x1e785000 + (__n) * 0x40)
+#define AST_REG_WDT(__n, __offset)             (AST_REG_WDT_BASE((__n)) + (__offset))
+#define AST_REG_WDT04(__n)                     AST_REG_WDT((__n), 0x04)
+#define AST_REG_WDT08(__n)                     AST_REG_WDT((__n), 0x08)
+#define AST_REG_WDT0C(__n)                     AST_REG_WDT((__n), 0x0c)
+#define AST_REG_WDT14(__n)                     AST_REG_WDT((__n), 0x14)
+#define AST_REG_WDT1C(__n)                     AST_REG_WDT((__n), 0x1c)
+#define AST_REG_WDT2C(__n)                     AST_REG_WDT((__n), 0x2c)
+
 #endif