RISC-V: Support VLS LMUL cost scaling

Make VLS (fixed-length) vector modes use the same LMUL cost scaling as
VLA modes. This makes the vectorizer to pick smaller LMULs sometimes.

Here is how I update the testsuite which failed in regression test:
  - dyn-lmul-conv-[1-2].c: The cost model now prefers smaller LMULs,
    so update expectations.
  - pr123414.c: This test relies on large LMULs to trigger a specific bug,
    can be fixed by adding -fno-vect-cost-model.

gcc/ChangeLog:

	* config/riscv/riscv-vector-costs.cc (get_lmul_cost_scaling):
	Enable scaling for all vector modes (VLA and VLS).

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/dyn-lmul-conv-1.c: Update expected LMUL counts.
	* gcc.target/riscv/rvv/autovec/dyn-lmul-conv-2.c: Likewise.
	* gcc.target/riscv/rvv/autovec/pr123414.c: Disable vector cost model.

Signed-off-by: Zhongyao Chen <chen.zhongyao@zte.com.cn>

diff --git a/gcc/config/riscv/riscv-vector-costs.cc b/gcc/config/riscv/riscv-vector-costs.cc
index 833a525abd65e167b9a51db3c0f8559c2562d4d1..8e6027526646a6f7c2d2b8efaf7a909a7eaf907e 100644 (file)
--- a/gcc/config/riscv/riscv-vector-costs.cc
+++ b/gcc/config/riscv/riscv-vector-costs.cc
@@ -1334,9 +1334,6 @@ segment_loadstore_group_size (enum vect_cost_for_stmt kind,
 static unsigned
 get_lmul_cost_scaling (machine_mode mode)
 {
-  if (!riscv_vla_mode_p (mode))
-    return 1;
-
   enum vlmul_type vlmul = get_vlmul (mode);
 
   /* Cost scaling based on LMUL and data processed.

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-1.c
index 91d777a58a78c5d798fc96e306d69895a695faf8..e04f16a9d93f3acfeaee84be0affdd217ccda93b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-1.c
@@ -37,7 +37,7 @@ void foo8x (long *restrict a, char *restrict b, int n)
     a[i] = b[i];
 }
 
-/* { dg-final { scan-assembler-times ",m1," 3 } } */
+/* { dg-final { scan-assembler-not ",m1," } } */
 /* { dg-final { scan-assembler-times ",m2," 3 } } */
-/* { dg-final { scan-assembler-times ",m4," 4 } } */
-/* { dg-final { scan-assembler-times ",m8," 2 } } */
+/* { dg-final { scan-assembler-times ",m4," 2 } } */
+/* { dg-final { scan-assembler-times ",m8," 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-2.c
index 468f061e3b1cc7688ea969e9a9f59ff30a4eab7a..4ed92b9e5a9092733b4a27d528866e3cbb325dfd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/dyn-lmul-conv-2.c
@@ -37,8 +37,8 @@ void foo8x (unsigned char *restrict a, unsigned long *restrict b, int n)
     a[i] = b[i];
 }
 
-/* { dg-final { scan-assembler-times ",m1," 7 } } */
+/* { dg-final { scan-assembler-times ",m1," 6 } } */
 /* { dg-final { scan-assembler-times ",m2," 3 } } */
 /* { dg-final { scan-assembler-times ",m4," 1 } } */
-/* { dg-final { scan-assembler-times ",m8," 1 } } */
+/* { dg-final { scan-assembler-not ",m8," } } */
 /* { dg-final { scan-assembler-not ",mf2," } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123414.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123414.c
index 9e3bf6bca816cb75762b271110c4e8da645b50f8..44ca8ef8dda8807b08c93405ce39cdc399a49a49 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123414.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123414.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fsigned-char -fno-strict-aliasing -fwrapv -fdump-tree-optimized -std=gnu99" } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-max-lmul=m8 -O3 -fsigned-char -fno-strict-aliasing -fwrapv -fdump-tree-optimized -std=gnu99 -fno-vect-cost-model" } */
 
 signed char a=2;
 long long b;