drm/amd/display: Fix DCN42 gpuvm_min_page_size_kbytes in SOC BB

[Why & How]
To match the HW specification this should be 4, not 256.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h
index ccdd9fd1e1bd1f346481bc38b60ab5049a182ce2..9ee09255623390c1d4394b80f93021f33d299331 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/bounding_boxes/dcn42_soc_bb.h
@@ -208,7 +208,7 @@ static const struct dml2_soc_bb dml2_socbb_dcn42 = {
        .fabric_datapath_to_dcn_data_return_bytes = 32,
        .return_bus_width_bytes = 64,
        .hostvm_min_page_size_kbytes = 4,
-       .gpuvm_min_page_size_kbytes = 256,
+       .gpuvm_min_page_size_kbytes = 4,
        .gpuvm_max_page_table_levels = 1,
        .hostvm_max_non_cached_page_table_levels = 2,
        .phy_downspread_percent = 0.38,