arm64: dts: s32g: add PWM support for s32g2 and s32g3

Add PWM0 and PWM1 for S32G2 and S32G3 SoCs

Reviewed-by: Enric Balletbo i Serra <eballetb@redhat.com>
Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index a1f33197b4b0108b1402402537addc4852e388cb..809019ea0e29983ff7da9612882985c482af2959 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -563,6 +563,19 @@
                        status = "disabled";
                };
 
+               pwm0: pwm@401f4000 {
+                       compatible = "nxp,s32g2-ftm-pwm";
+                       reg = <0x401f4000 0x1000>;
+                       #pwm-cells = <3>;
+                       clocks = <&clks 5>,
+                                <&clks 6>,
+                                <&clks 5>,
+                                <&clks 5>;
+                       clock-names = "ftm_sys", "ftm_ext",
+                                     "ftm_fix", "ftm_cnt_clk_en";
+                       status = "disabled";
+               };
+
                adc0: adc@401f8000 {
                        compatible = "nxp,s32g2-sar-adc";
                        reg = <0x401f8000 0x1000>;
@@ -745,6 +758,19 @@
                        status = "disabled";
                };
 
+               pwm1: pwm@402e4000 {
+                       compatible = "nxp,s32g2-ftm-pwm";
+                       reg = <0x402e4000 0x1000>;
+                       #pwm-cells = <3>;
+                       clocks = <&clks 7>,
+                                <&clks 8>,
+                                <&clks 7>,
+                                <&clks 7>;
+                       clock-names = "ftm_sys", "ftm_ext",
+                                     "ftm_fix", "ftm_cnt_clk_en";
+                       status = "disabled";
+               };
+
                adc1: adc@402e8000 {
                        compatible = "nxp,s32g2-sar-adc";
                        reg = <0x402e8000 0x1000>;

diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 6a1e0665d73e05ceab91984654d92afe3bcf027d..22e80fc03f9c74ee5de2ef0001e57b5ba7fc6364 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -626,6 +626,20 @@
                        status = "disabled";
                };
 
+               pwm0: pwm@401f4000 {
+                       compatible = "nxp,s32g3-ftm-pwm",
+                                    "nxp,s32g2-ftm-pwm";
+                       reg = <0x401f4000 0x1000>;
+                       #pwm-cells = <3>;
+                       clocks = <&clks 5>,
+                                <&clks 6>,
+                                <&clks 5>,
+                                <&clks 5>;
+                       clock-names = "ftm_sys", "ftm_ext",
+                                     "ftm_fix", "ftm_cnt_clk_en";
+                       status = "disabled";
+               };
+
                adc0: adc@401f8000 {
                        compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
                        reg = <0x401f8000 0x1000>;
@@ -820,6 +834,20 @@
                        status = "disabled";
                };
 
+               pwm1: pwm@402e4000 {
+                       compatible = "nxp,s32g3-ftm-pwm",
+                                    "nxp,s32g2-ftm-pwm";
+                       reg = <0x402e4000 0x1000>;
+                       #pwm-cells = <3>;
+                       clocks = <&clks 7>,
+                                <&clks 8>,
+                                <&clks 7>,
+                                <&clks 7>;
+                       clock-names = "ftm_sys", "ftm_ext",
+                                     "ftm_fix", "ftm_cnt_clk_en";
+                       status = "disabled";
+               };
+
                adc1: adc@402e8000 {
                        compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
                        reg = <0x402e8000 0x1000>;

diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
index 803ff45310771326aeac15188ccf63bb4ea702ba..be7b645afa2de31459d5d65f1ad2333b58e35586 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
- * Copyright 2024 NXP
+ * Copyright 2024, 2026 NXP
  *
  * Authors: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
  *          Ghennadi Procopciuc <ghennadi.procopciuc@oss.nxp.com>
@@ -245,6 +245,70 @@
                        bias-pull-up;
                };
        };
+
+       ftm0_pins: ftm0-pins {
+               ftm0-grp0 {
+                       pinmux = <0x2912>;
+               };
+
+               ftm0-grp1 {
+                       pinmux = <0x122>,
+                                <0xb42>;
+                       output-enable;
+                       input-enable;
+               };
+
+               ftm0-grp2 {
+                       pinmux = <0xb13>,
+                                <0xb53>;
+                       output-enable;
+                       input-enable;
+               };
+
+               ftm0-grp3 {
+                       pinmux = <0x2904>;
+               };
+
+               ftm0-grp4 {
+                       pinmux = <0x2925>;
+               };
+
+               ftm0-grp5 {
+                       pinmux = <0x2936>;
+               };
+       };
+
+       ftm1_pins: ftm1-pins {
+               ftm1-grp0 {
+                       pinmux = <0x1d3>;
+                       output-enable;
+                       input-enable;
+               };
+
+               ftm1-grp1 {
+                       pinmux = <0x29b4>;
+               };
+
+               ftm1-grp2 {
+                       pinmux = <0x29c3>;
+               };
+
+               ftm1-grp3 {
+                       pinmux = <0x1f4>;
+                       output-enable;
+                       input-enable;
+               };
+
+               ftm1-grp4 {
+                       pinmux = <0x202>;
+                       output-enable;
+                       input-enable;
+               };
+
+               ftm1-grp5 {
+                       pinmux = <0x29d2>;
+               };
+       };
 };
 
 &can0 {
@@ -293,6 +357,18 @@
        status = "okay";
 };
 
+&pwm0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&ftm0_pins>;
+       status = "okay";
+};
+
+&pwm1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&ftm1_pins>;
+       status = "okay";
+};
+
 &spi1 {
        pinctrl-0 = <&dspi1_pins>;
        pinctrl-names = "default";