drm/amdgpu: Align amdgpu_gtt_mgr entries to TLB size on all SI

It seems that Pitcairn has the same issues as Tahiti
with regards to the TLB size. This commit fixes a
VCE1 FW validation timeout on suspend/resume on Pitcairn.

Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5336
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 629279e2e798cd161cf74f40aaebfeb16d45eb01)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index a5d26b943f6d48f5065eaf4f134b92518f9cf278..d23a91d029aa810ff1db1102fccab37a8a1e98cc 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -203,7 +203,7 @@ int amdgpu_gtt_mgr_alloc_entries(struct amdgpu_gtt_mgr *mgr,
        int r;
 
        /* Align to TLB L2 cache entry size to work around "V bit HW bug" */
-       if (adev->asic_type == CHIP_TAHITI) {
+       if (adev->family == AMDGPU_FAMILY_SI) {
                alignment = 32 * 1024 / AMDGPU_GPU_PAGE_SIZE;
                num_pages = ALIGN(num_pages, alignment);
        }