cs->spi_base, cs->spi_irs_range, cs->spi_range);
return;
}
+ if (!cs->dma) {
+ error_setg(errp, "sysmem link property not set");
+ return;
+ }
+
+ address_space_init(&cs->dma_as, cs->dma, "gicv5-sysmem");
trace_gicv5_common_realize(cs->irsid, cs->num_cpus,
cs->spi_base, cs->spi_irs_range, cs->spi_range);
DEFINE_PROP_UINT32("spi-base", GICv5Common, spi_base, 0),
DEFINE_PROP_UINT32("spi-irs-range", GICv5Common, spi_irs_range,
GICV5_SPI_IRS_RANGE_NOT_SET),
+ DEFINE_PROP_LINK("sysmem", GICv5Common, dma, TYPE_MEMORY_REGION,
+ MemoryRegion *),
};
static void gicv5_common_class_init(ObjectClass *oc, const void *data)