drm/i915: Remove i915_reg.h from i9xx_wm.c

Move FW_BLC_SELF to common header to make i9xx_wm.c
free from i915_reg.h include. Introduce a common
intel_gmd_misc_regs.h to define common miscellaneous
register definitions across graphics and display.

v3: MISC header included as needed, drop from i915_reg (Jani)

v2: Introdue a common misc header for GMD

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-13-uma.shankar@intel.com

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 39dfceb438ae4fbd9d6e8f8ae5cff69e84d3fde0..24f898efa9dd7f7f9554a3cc451b6d7c580fc4a1 100644 (file)
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -6,8 +6,8 @@
 #include <linux/iopoll.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
-#include "i915_reg.h"
 #include "i9xx_wm.h"
 #include "i9xx_wm_regs.h"
 #include "intel_atomic.h"

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index aba13e8a905184ddacd4bf89fc85b6442dd49dee..f041a71023177b61dd59629242c206a798ba31f8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -13,6 +13,7 @@
 #include <drm/drm_file.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "hsw_ips.h"
 #include "i915_reg.h"

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 5bc891f6de574e76d39aa6cb1d8529a5128fb083..9f241655aa9916b62eaaeea9ff43893e5791b1da 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3132,6 +3132,11 @@ enum skl_power_gate {
 #define   MTL_TRAS_MASK                        REG_GENMASK(16, 8)
 #define   MTL_TRDPRE_MASK              REG_GENMASK(7, 0)
 
-
+#define FW_BLC         _MMIO(0x20d8)
+#define FW_BLC2                _MMIO(0x20dc)
+#define FW_BLC_SELF    _MMIO(0x20e0) /* 915+ only */
+#define   FW_BLC_SELF_EN_MASK      REG_BIT(31)
+#define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
+#define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
 
 #endif /* __INTEL_DISPLAY_REGS_H__ */

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 5eda98ebc1ae94246e1eec2d9d9d2180d5430a28..ee90f5323da75cbda2cb8b962cb9dbe5a80364d4 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -6,6 +6,7 @@
 #include <linux/highmem.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "display/intel_display.h"
 #include "i915_drv.h"

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index c1797e49811d1a2fa950299adae6d47ed59aefc7..099453dd9cd5050d2c89b643ee83b75097bbd89c 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_cache.h>
 #include <drm/intel/intel_gmd_interrupt_regs.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "gem/i915_gem_internal.h"
 

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index ece88c612e2789df8e07e48e11e6c645768b42bd..4427812b2438c82e21cdd195ef515de7a70cf48c 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -3,6 +3,8 @@
  * Copyright © 2014-2018 Intel Corporation
  */
 
+#include <drm/intel/intel_gmd_misc_regs.h>
+
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "i915_mmio_range.h"

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index bf7c3d3f5f8a2b9dfd94aba7337eed3e80718f70..98c35c78a4edb261e3e161afa99ea404819bf77c 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -37,6 +37,7 @@
 #include <linux/slab.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "display/i9xx_plane_regs.h"
 #include "display/intel_display_regs.h"

diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index d4e9d485d382de2f99527e151ab4c60c705a6bc5..3eb442acdf8d907475783f0c4e52a99f5eab38c8 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -34,6 +34,7 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "gt/intel_context.h"
 #include "gt/intel_engine_regs.h"

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 42f6b44f00274c5e52bc583f260784b8d2dbe646..4778ba664ec75758b60ca90f5c8286b6a6785634 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -33,6 +33,7 @@
 
 #include <drm/drm_debugfs.h>
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "gem/i915_gem_context.h"
 #include "gt/intel_gt.h"

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b808d1ec5387a39c9a0377557d5206e259e2b4d5..2bac216bd2b92971649bc88134566d521009e244 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -393,24 +393,10 @@
 
 #define GEN2_ERROR_REGS                I915_ERROR_REGS(EMR, EIR)
 
-#define INSTPM         _MMIO(0x20c0)
-#define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
-#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
-                                       will not assert AGPBUSY# and will only
-                                       be delivered when out of C3. */
-#define   INSTPM_FORCE_ORDERING                                (1 << 7) /* GEN6+ */
-#define   INSTPM_TLB_INVALIDATE        (1 << 9)
-#define   INSTPM_SYNC_FLUSH    (1 << 5)
 #define MEM_MODE       _MMIO(0x20cc)
 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
 #define   MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
 #define   MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
-#define FW_BLC         _MMIO(0x20d8)
-#define FW_BLC2                _MMIO(0x20dc)
-#define FW_BLC_SELF    _MMIO(0x20e0) /* 915+ only */
-#define   FW_BLC_SELF_EN_MASK      REG_BIT(31)
-#define   FW_BLC_SELF_FIFO_MASK    REG_BIT(16) /* 945 only */
-#define   FW_BLC_SELF_EN           REG_BIT(15) /* 945 only */
 #define MM_BURST_LENGTH     0x00700000
 #define MM_FIFO_WATERMARK   0x0001F000
 #define LM_BURST_LENGTH     0x00000700
@@ -833,11 +819,6 @@
 #define   KVM_CONFIG_CHANGE_NOTIFICATION_SELECT        REG_BIT(14)
 
 
-#define DISP_ARB_CTL   _MMIO(0x45000)
-#define   DISP_FBC_MEMORY_WAKE         REG_BIT(31)
-#define   DISP_TILE_SURFACE_SWIZZLING  REG_BIT(13)
-#define   DISP_FBC_WM_DIS              REG_BIT(15)
-
 #define GEN8_CHICKEN_DCPR_1                    _MMIO(0x46430)
 #define   _LATENCY_REPORTING_REMOVED_PIPE_D    REG_BIT(31)
 #define   SKL_SELECT_ALTERNATE_DC_EXIT         REG_BIT(30)

diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 4e18d5a22112f82c6764457d62841b26fa175205..1ad31435bd3ff8b9522fc6a25cb49b9e8d60767b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -26,6 +26,7 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "display/i9xx_plane_regs.h"
 #include "display/intel_display.h"

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 8cfe9b56f1d095d032589a7e09446b9e12c527c6..c8a51e77308690ffdc58204db8dd9017fb97e56a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -4,6 +4,7 @@
  */
 
 #include <drm/intel/intel_pcode_regs.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
 
 #include "display/bxt_dpio_phy_regs.h"
 #include "display/i9xx_plane_regs.h"

diff --git a/include/drm/intel/intel_gmd_misc_regs.h b/include/drm/intel/intel_gmd_misc_regs.h
new file mode 100644 (file)
index 0000000..763d771
--- /dev/null
+++ b/include/drm/intel/intel_gmd_misc_regs.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_GMD_MISC_REGS_H_
+#define _INTEL_GMD_MISC_REGS_H_
+
+#define DISP_ARB_CTL   _MMIO(0x45000)
+#define   DISP_FBC_MEMORY_WAKE         REG_BIT(31)
+#define   DISP_TILE_SURFACE_SWIZZLING  REG_BIT(13)
+#define   DISP_FBC_WM_DIS              REG_BIT(15)
+
+#define INSTPM         _MMIO(0x20c0)
+#define   INSTPM_SELF_EN (1 << 12) /* 915GM only */
+#define   INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
+                                       will not assert AGPBUSY# and will only
+                                       be delivered when out of C3. */
+#define   INSTPM_FORCE_ORDERING                                (1 << 7) /* GEN6+ */
+#define   INSTPM_TLB_INVALIDATE        (1 << 9)
+#define   INSTPM_SYNC_FLUSH    (1 << 5)
+
+#endif