drm/i915/display: Disable DMG Clock Gating

Incorrect clock is connected to DMG registers.
Disable DMG Clock gating during display initialization.

WA: 22021451799
Bspec: 69095
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
Link: https://patch.msgid.link/20260122031818.703590-1-suraj.kandpal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 581d943b9bdc3d3f8f95bc4aa6215bd29dde4dae..86a6cc45b6abac1aba29bf73b21ffd71cbeb101b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -32,9 +32,17 @@ static void adlp_display_wa_apply(struct intel_display *display)
        intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
 }
 
+static void xe3plpd_display_wa_apply(struct intel_display *display)
+{
+       /* Wa_22021451799 */
+       intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, DMG_GATING_DIS);
+}
+
 void intel_display_wa_apply(struct intel_display *display)
 {
-       if (display->platform.alderlake_p)
+       if (DISPLAY_VER(display) == 35)
+               xe3plpd_display_wa_apply(display);
+       else if (display->platform.alderlake_p)
                adlp_display_wa_apply(display);
        else if (DISPLAY_VER(display) == 12)
                xe_d_display_wa_apply(display);

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5bf3b4ab2baa2a2915b03e459c1acc613a6f456f..f928db78a3fa5601353dcc3e67881644c8bf2568 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -763,6 +763,7 @@
  */
 #define GEN9_CLKGATE_DIS_0             _MMIO(0x46530)
 #define   DARBF_GATING_DIS             REG_BIT(27)
+#define   DMG_GATING_DIS               REG_BIT(21)
 #define   MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
 #define   PWM2_GATING_DIS              REG_BIT(14)
 #define   PWM1_GATING_DIS              REG_BIT(13)