drm/amdgpu: Use asic specific pte_addr_mask

For PTE creation use asic specific physical page base address mask

v2: Change variable name from pa_mask to pte_addr_mask

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 2ea989885941a6e5607ef86dbe309e90b7191f21)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 3d9497d121ca20d97b9fdf46833272bb8aadecb9..13a5acdf8da3b1e6138d1720a81f52bfdd6cb841 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -170,7 +170,7 @@ int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
        /*
         * The following is for PTE only. GART does not have PDEs.
        */
-       value = addr & 0x0000FFFFFFFFF000ULL;
+       value = addr & adev->gmc.pte_addr_mask;
        value |= flags;
        writeq(value, ptr + (gpu_page_idx * 8));
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 6ab4c1e297fce7e966e9306c357a5802301db7b2..d03536b969b55e8d48c96aedfd0551d9dd70e608 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -280,6 +280,7 @@ struct amdgpu_gmc {
        u64                     real_vram_size;
        int                     vram_mtrr;
        u64                     mc_mask;
+       uint64_t                pte_addr_mask;
        const struct firmware   *fw;    /* MC firmware */
        uint32_t                fw_version;
        struct amdgpu_irq_src   vm_fault;

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index e1ace7d44ffdfd247b1c3ec2c979155ddd02653e..f5bdfea54afacfe6cb3842235c68e3e133a173b7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -847,6 +847,7 @@ static int gmc_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
+       adev->gmc.pte_addr_mask = 0x0000FFFFFFFFF000ULL; /* 48 bit PA */
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 94d6631ce0bce62be858625bcc8420475b9d3234..807bd180b9d49caf10ad000591dd656e3ea4123c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -821,6 +821,7 @@ static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
+       adev->gmc.pte_addr_mask = 0x0000FFFFFFFFF000ULL; /* 48 bit PA */
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
index e10ac9788d13a7c3414ae5779ce4801a7af86e61..52c161c2df0a1adb4bd10440f04742f385653d98 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
@@ -814,6 +814,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
 {
        int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
        struct amdgpu_device *adev = ip_block->adev;
+       uint64_t pte_addr_mask = 0;
        int i;
 
        adev->mmhub.funcs->init(adev);
@@ -843,6 +844,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
                 * block size 512 (9bit)
                 */
                amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
+               pte_addr_mask = 0x0000FFFFFFFFF000ULL; /* 48 bit PA */
                break;
        case IP_VERSION(12, 1, 0):
                bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
@@ -855,6 +857,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
                 * block size 512 (9bit)
                 */
                amdgpu_vm_adjust_size(adev, 128 * 1024 * 1024, 9, 4, 57);
+               pte_addr_mask = 0x000FFFFFFFFFF000ULL; /* 52 bit PA */
                break;
        default:
                break;
@@ -911,6 +914,7 @@ static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = AMDGPU_GMC_HOLE_MASK;
+       adev->gmc.pte_addr_mask = pte_addr_mask;
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index cc272a96fcef010db0aef26318bf003b9724c655..6aa581b1c14882b7f44148fdcab29fbab5e3c8d5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -836,6 +836,7 @@ static int gmc_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
        amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
 
        adev->gmc.mc_mask = 0xffffffffffULL;
+       adev->gmc.pte_addr_mask = 0x000000FFFFFFF000ULL;
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index bb16ba2ef6fd90deb2c6f7e5329a7cccf1460745..2b0362c4d9eb983e39acedc8ee10aa60bedebc54 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1016,6 +1016,7 @@ static int gmc_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
+       adev->gmc.pte_addr_mask = 0x000000FFFFFFF000ULL; /* 40 bit PA */
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index a59174f6bcc18bb1df632d282d608c044aab5235..fbccfcb3d7cfcedbd23b53c96c0e5dd0c468bcd9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1131,6 +1131,7 @@ static int gmc_v8_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
+       adev->gmc.pte_addr_mask = 0x000000FFFFFFF000ULL; /* 40 bit PA */
 
        r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
        if (r) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index e7b78027002beefb52f377119aa864b448e9d865..c6dbe25f2bd93a0559aaa3734204cf54cdfa8353 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1994,6 +1994,7 @@ static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block)
         * internal address space.
         */
        adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
+       adev->gmc.pte_addr_mask = 0x0000FFFFFFFFF000ULL; /* 48 bit PA */
 
        dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >=
                                        IP_VERSION(9, 4, 2) ?