arm64: dts: s32g: add PIT support for s32g2 and s32g3

Add PIT0 and PIT1 for S32G2 and S32G3 SoCs

Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
Reviewed-by: Enric Balletbo i Serra <eballetb@redhat.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12deb397a6af0ee98540c1740a405954..f508b776b4ddd6d74d96d00132d957bf44c1f122 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,7 +3,7 @@
  * NXP S32G2 SoC family
  *
  * Copyright (c) 2021 SUSE LLC
- * Copyright 2017-2021, 2024-2025 NXP
+ * Copyright 2017-2021, 2024-2026 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -417,6 +417,15 @@
                        clock-names = "dmamux0", "dmamux1";
                };
 
+               pit0: timer@40188000 {
+                       compatible = "nxp,s32g2-pit";
+                       reg = <0x40188000 0x3000>;
+                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 61>;
+                       clock-names = "pit";
+                       status = "disabled";
+               };
+
                can0: can@401b4000 {
                        compatible = "nxp,s32g2-flexcan";
                        reg = <0x401b4000 0xa000>;
@@ -622,6 +631,15 @@
                        clock-names = "dmamux0", "dmamux1";
                };
 
+               pit1: timer@40288000 {
+                       compatible = "nxp,s32g2-pit";
+                       reg = <0x40288000 0x3000>;
+                       interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 61>;
+                       clock-names = "pit";
+                       status = "disabled";
+               };
+
                can2: can@402a8000 {
                        compatible = "nxp,s32g2-flexcan";
                        reg = <0x402a8000 0xa000>;

diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index e314f3c7d61d00d48dbea70bd36291882f2f0ef1..efe5398e12403033cdc2021092ec8db003b49d29 100644 (file)
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
- * Copyright 2021-2025 NXP
+ * Copyright 2021-2026 NXP
  *
  * Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
  *          Ciprian Costea <ciprianmarian.costea@nxp.com>
@@ -475,6 +475,15 @@
                        clock-names = "dmamux0", "dmamux1";
                };
 
+               pit0: pit@40188000 {
+                       compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
+                       reg = <0x40188000 0x3000>;
+                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 61>;
+                       clock-names = "pit";
+                       status = "disabled";
+               };
+
                can0: can@401b4000 {
                        compatible = "nxp,s32g3-flexcan",
                                           "nxp,s32g2-flexcan";
@@ -693,6 +702,15 @@
                        clock-names = "dmamux0", "dmamux1";
                };
 
+               pit1: pit@40288000 {
+                       compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
+                       reg = <0x40288000 0x3000>;
+                       interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clks 61>;
+                       clock-names = "pit";
+                       status = "disabled";
+               };
+
                can2: can@402a8000 {
                        compatible = "nxp,s32g3-flexcan",
                                           "nxp,s32g2-flexcan";