]> git.ipfire.org Git - thirdparty/qemu.git/commitdiff
hw/misc/aspeed_scu: convert to use Resettable interface
authorKane Chen <kane_chen@aspeedtech.com>
Mon, 25 May 2026 04:41:41 +0000 (04:41 +0000)
committerCédric Le Goater <clg@redhat.com>
Tue, 26 May 2026 06:56:48 +0000 (08:56 +0200)
Replace the legacy reset callback registered via
device_class_set_legacy_reset() with the Resettable interface.

Signed-off-by: Kane Chen <kane_chen@aspeedtech.com>
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20260525044129.3133916-9-kane_chen@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
hw/misc/aspeed_scu.c

index c9b73a1148056f084ea62b171e428435d77ee9d1..19da6c075faee100ba26dde758ad2aba01ed5db5 100644 (file)
@@ -542,10 +542,10 @@ static uint32_t aspeed_2600_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg)
     return clkin * multiplier;
 }
 
-static void aspeed_scu_reset(DeviceState *dev)
+static void aspeed_scu_reset_hold(Object *obj, ResetType type)
 {
-    AspeedSCUState *s = ASPEED_SCU(dev);
-    AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
+    AspeedSCUState *s = ASPEED_SCU(obj);
+    AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(obj);
 
     memcpy(s->regs, asc->resets, asc->nr_regs * 4);
     s->regs[SILICON_REV] = s->silicon_rev;
@@ -616,8 +616,9 @@ static const Property aspeed_scu_properties[] = {
 static void aspeed_scu_class_init(ObjectClass *klass, const void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     dc->realize = aspeed_scu_realize;
-    device_class_set_legacy_reset(dc, aspeed_scu_reset);
+    rc->phases.hold = aspeed_scu_reset_hold;
     dc->desc = "ASPEED System Control Unit";
     dc->vmsd = &vmstate_aspeed_scu;
     device_class_set_props(dc, aspeed_scu_properties);
@@ -822,10 +823,10 @@ static const uint32_t ast2600_a3_resets[ASPEED_AST2600_SCU_NR_REGS] = {
     [AST2600_CHIP_ID1]          = 0x88884444,
 };
 
-static void aspeed_ast2600_scu_reset(DeviceState *dev)
+static void aspeed_ast2600_scu_reset_hold(Object *obj, ResetType type)
 {
-    AspeedSCUState *s = ASPEED_SCU(dev);
-    AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
+    AspeedSCUState *s = ASPEED_SCU(obj);
+    AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(obj);
 
     memcpy(s->regs, asc->resets, asc->nr_regs * 4);
 
@@ -844,10 +845,11 @@ static void aspeed_ast2600_scu_reset(DeviceState *dev)
 static void aspeed_2600_scu_class_init(ObjectClass *klass, const void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
 
     dc->desc = "ASPEED 2600 System Control Unit";
-    device_class_set_legacy_reset(dc, aspeed_ast2600_scu_reset);
+    rc->phases.hold = aspeed_ast2600_scu_reset_hold;
     asc->resets = ast2600_a3_resets;
     asc->calc_hpll = aspeed_2600_scu_calc_hpll;
     asc->get_apb = aspeed_2600_scu_get_apb_freq;
@@ -950,10 +952,10 @@ static const uint32_t ast2700_a0_resets[ASPEED_AST2700_SCU_NR_REGS] = {
     [AST2700_SCU_VGA_SCRATCH_0]     = 0x00000040,
 };
 
-static void aspeed_ast2700_scu_reset(DeviceState *dev)
+static void aspeed_ast2700_scu_reset_hold(Object *obj, ResetType type)
 {
-    AspeedSCUState *s = ASPEED_SCU(dev);
-    AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
+    AspeedSCUState *s = ASPEED_SCU(obj);
+    AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(obj);
 
     memcpy(s->regs, asc->resets, asc->nr_regs * 4);
     s->regs[AST2700_SILICON_REV] = s->silicon_rev;
@@ -963,10 +965,11 @@ static void aspeed_ast2700_scu_reset(DeviceState *dev)
 static void aspeed_2700_scu_class_init(ObjectClass *klass, const void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
 
     dc->desc = "ASPEED 2700 System Control Unit";
-    device_class_set_legacy_reset(dc, aspeed_ast2700_scu_reset);
+    rc->phases.hold = aspeed_ast2700_scu_reset_hold;
     asc->resets = ast2700_a0_resets;
     asc->calc_hpll = aspeed_2600_scu_calc_hpll;
     asc->get_apb = aspeed_2700_scu_get_apb_freq;
@@ -1082,10 +1085,11 @@ static const uint32_t ast2700_a0_resets_io[ASPEED_AST2700_SCU_NR_REGS] = {
 static void aspeed_2700_scuio_class_init(ObjectClass *klass, const void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
 
     dc->desc = "ASPEED 2700 System Control Unit I/O";
-    device_class_set_legacy_reset(dc, aspeed_ast2700_scu_reset);
+    rc->phases.hold = aspeed_ast2700_scu_reset_hold;
     asc->resets = ast2700_a0_resets_io;
     asc->calc_hpll = aspeed_2600_scu_calc_hpll;
     asc->get_apb = aspeed_2700_scuio_get_apb_freq;
@@ -1123,10 +1127,10 @@ static const uint32_t ast1030_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = {
     [AST2600_CHIP_ID1]          = 0x0BADCAFE,
 };
 
-static void aspeed_ast1030_scu_reset(DeviceState *dev)
+static void aspeed_ast1030_scu_reset_hold(Object *obj, ResetType type)
 {
-    AspeedSCUState *s = ASPEED_SCU(dev);
-    AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev);
+    AspeedSCUState *s = ASPEED_SCU(obj);
+    AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(obj);
 
     memcpy(s->regs, asc->resets, asc->nr_regs * 4);
 
@@ -1140,10 +1144,11 @@ static void aspeed_ast1030_scu_reset(DeviceState *dev)
 static void aspeed_1030_scu_class_init(ObjectClass *klass, const void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass);
 
     dc->desc = "ASPEED 1030 System Control Unit";
-    device_class_set_legacy_reset(dc, aspeed_ast1030_scu_reset);
+    rc->phases.hold = aspeed_ast1030_scu_reset_hold;
     asc->resets = ast1030_a1_resets;
     asc->calc_hpll = aspeed_2600_scu_calc_hpll;
     asc->get_apb = aspeed_1030_scu_get_apb_freq;