arm64: dts: qcom: milos: Add power-domain and iface clk for ice node

Qualcomm in-line crypto engine (ICE) platform driver specifies and votes
for its own resources. Before accessing ICE hardware during probe, to
avoid potential unclocked register access issues (when clk_ignore_unused
is not passed on the kernel command line), in addition to the 'core' clock
the 'iface' clock should also be turned on by the driver. This can only be
done if the UFS_PHY_GDSC power domain is enabled. Specify both the
UFS_PHY_GDSC power domain and the 'iface' clock in the ICE node for milos.

Fixes: 04bb37433330e ("arm64: dts: qcom: milos: Add UFS nodes")
Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260416-qcom_ice_power_and_clk_vote-v5-12-5ccf5d7e2846@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 4a64a98a434b6bb3f3961a5e8b25d45a5df19cbf..a6e463f3885dc6f79d384e0909d6dce7e952de70 100644 (file)
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -1275,7 +1275,11 @@
                                     "qcom,inline-crypto-engine";
                        reg = <0x0 0x01d88000 0x0 0x18000>;
 
-                       clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+                       clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+                                <&gcc GCC_UFS_PHY_AHB_CLK>;
+                       clock-names = "core",
+                                     "iface";
+                       power-domains = <&gcc UFS_PHY_GDSC>;
                };
 
                tcsr_mutex: hwlock@1f40000 {