[PATCH v2] RISC-V: Add Synopsys RHX-100 series pipeline description

This patch introduces the pipeline description for the Synopsys RHX-100 series
processor to the RISC-V GCC backend.  The RHX-100 features a 10-stage,
dual-issue, in-order execution pipeline architecture.

It has support for instruction fusion, which will be addressed by subsequent
patches.  Due to fusion, up to four instructions can be issued in a single
cycle.  It is modeled as four separate pipelines and the issue_rate is set to
four.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_TUNE): Add arc-v-rhx-100-series.
	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add
	arcv_rhx100.
	* config/riscv/riscv.cc (arcv_rhx100_tune_info): New riscv_tune_param.
	* config/riscv/riscv.md: Add arcv_rhx100 to tune attribute.
	* doc/riscv-mtune.texi: Add RHX-100 documentation.
	* config/riscv/arcv-rhx100.md: New file.

Co-authored-by: Artemiy Volkov <artemiyv@acm.org>
Co-authored-by: Luis Silva <luiss@synopsys.com>
Signed-off-by: Michiel Derhaeg <michiel@synopsys.com>

diff --git a/gcc/config/riscv/arcv-rhx100.md b/gcc/config/riscv/arcv-rhx100.md
new file mode 100644 (file)
index 0000000..da46f71
--- /dev/null
+++ b/gcc/config/riscv/arcv-rhx100.md
@@ -0,0 +1,120 @@
+;; DFA scheduling description of the Synopsys RHX-100 cpu
+;; for GNU C compiler
+;; Copyright (C) 2026 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_automaton "arcv_rhx100")
+
+(define_cpu_unit "arcv_rhx100_ALU_A_fuse0_early"       "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_ALU_A_fuse1_early"       "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_ALU_B_fuse0_early"       "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_ALU_B_fuse1_early"       "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_MPY"     "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_DIV"     "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_DMP_fuse0"       "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_DMP_fuse1"       "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_fdivsqrt"        "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_issueA_fuse0" "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_issueA_fuse1" "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_issueB_fuse0" "arcv_rhx100")
+(define_cpu_unit "arcv_rhx100_issueB_fuse1" "arcv_rhx100")
+
+;; Instruction reservation for arithmetic instructions (pipe A, pipe B).
+(define_insn_reservation "arcv_rhx100_alu_early_arith" 1
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "unknown,move,const,arith,shift,slt,multi,auipc,nop,logical,\
+               bitmanip,min,max,minu,maxu,clz,ctz,atomic,\
+               condmove,mvpair,zicond,cpop,clmul,rotate"))
+  "((arcv_rhx100_issueA_fuse0 + arcv_rhx100_ALU_A_fuse0_early) | (arcv_rhx100_issueA_fuse1 + arcv_rhx100_ALU_A_fuse1_early)) | ((arcv_rhx100_issueB_fuse0 + arcv_rhx100_ALU_B_fuse0_early) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_ALU_B_fuse1_early))")
+
+(define_insn_reservation "arcv_rhx100_jmp_insn" 1
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+  "arcv_rhx100_issueA_fuse0 | arcv_rhx100_issueA_fuse1")
+
+(define_insn_reservation "arcv_rhx100_div_insn" 12
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "idiv"))
+  "arcv_rhx100_issueA_fuse0 + arcv_rhx100_DIV")
+
+(define_insn_reservation "arcv_rhx100_mpy_insn" 4
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "imul"))
+  "arcv_rhx100_issueA_fuse0 + arcv_rhx100_MPY")
+
+(define_insn_reservation "arcv_rhx100_load_insn" 3
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "load,fpload"))
+  "(arcv_rhx100_issueB_fuse0 + arcv_rhx100_DMP_fuse0) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_DMP_fuse1)")
+
+(define_insn_reservation "arcv_rhx100_store_insn" 1
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "store,fpstore"))
+  "(arcv_rhx100_issueB_fuse0 + arcv_rhx100_DMP_fuse0) | (arcv_rhx100_issueB_fuse1 + arcv_rhx100_DMP_fuse1)")
+
+;; (soft) floating points
+(define_insn_reservation "arcv_rhx100_xfer" 3
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "mfc,mtc,fcvt,fcvt_i2f,fcvt_f2i,fmove,fcmp"))
+  "(arcv_rhx100_ALU_A_fuse0_early | arcv_rhx100_ALU_B_fuse0_early)")
+
+(define_insn_reservation "arcv_rhx100_fmul" 5
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "fadd,fmul,fmadd"))
+  "(arcv_rhx100_ALU_A_fuse0_early | arcv_rhx100_ALU_B_fuse0_early)")
+
+(define_insn_reservation "arcv_rhx100_fdiv" 20
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "fdiv,fsqrt"))
+  "arcv_rhx100_fdivsqrt*7")
+
+(define_insn_reservation "arcv_rhx100_unknown" 5
+  (and (eq_attr "tune" "arcv_rhx100")
+       (eq_attr "type" "vfwalu,vfwcvtftoi,vrol,vmidx,vext,vaeskf1,vfredo,
+                        vector,sfb_alu,vlds,viminmax,vfcmp,vimov,vsmul,vnclip,
+                        vldm,vsetvl_pre,vwsll,vfmerge,vmffs,vclmul,vmpop,wrfrm,
+                        vsha2ms,vidiv,vfncvtitof,vaesef,vldr,vlsegdox,vfwmul,
+                        vfmul,vfredu,crypto,vmalu,vimul,vghsh,vialu,viwmul,
+                        vfcvtftoi,vaalu,vislide1up,vfcvtitof,vfwcvtftof,vgather,
+                        vaesz,vbrev,vshift,vsha2ch,vssegtux,vssegtox,vcompress,
+                        vcpop,vstux,vfncvtftof,vfrecp,vssegts,sf_vfnrclip,
+                        vstox,vstr,vlsegdff,vired,vimovvx,vislide1down,vclz,
+                        vfwredu,rdvl,vlde,vaesem,vsm3me,vmiota,vldux,vlsegde,
+                        vssegte,vfwmaccbf16,vfwredo,vctz,vsm4k,vsshift,vsts,
+                        vmsfs,vfmovvf,vfslide1down,viwred,vslidedown,vfncvtftoi,
+                        vsm3c,vnshift,vfalu,vfsqrt,wrvxrm,vfmuladd,vmov,vsetvl,
+                        vfclass,vsha2cl,vicmp,vldff,vfdiv,vste,vaeskf2,
+                        vfncvtbf16,vandn,vbrev8,vgmul,vaesdm,vlsegdux,vfsgnj,
+                        vfmov,rdfrm,vlsegds,vclmulh,vimuladd,viwalu,vfwmuladd,
+                        vimerge,vror,rdvlenb,vfwcvtitof,vaesdf,viwmuladd,vrev8,
+                        vsm4r,vsalu,vfminmax,vicalu,vslideup,vldox,vstm,
+                        vfwcvtbf16,vfmovfv,vfslide1up,vimovxv,sf_vc,sf_vqmacc,
+                        sf_vc_se"))
+  "(arcv_rhx100_issueA_fuse0 + arcv_rhx100_issueA_fuse1) | (arcv_rhx100_issueB_fuse0 + arcv_rhx100_issueB_fuse1)")
+
+;; Bypasses
+(define_bypass 1 "arcv_rhx100_alu_early_arith" "arcv_rhx100_store_insn" "riscv_store_data_bypass_p")
+
+(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_store_insn" "riscv_store_data_bypass_p")
+(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_alu_early_arith")
+(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_mpy_insn")
+(define_bypass 2 "arcv_rhx100_load_insn" "arcv_rhx100_load_insn")
+(define_bypass 1 "arcv_rhx100_load_insn" "arcv_rhx100_div_insn")
+
+(define_bypass 3 "arcv_rhx100_mpy_insn" "arcv_rhx100_mpy_insn")
+(define_bypass 3 "arcv_rhx100_mpy_insn" "arcv_rhx100_div_insn")

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index 79a460f8176edac774290a4a7b653cecf04d753f..66f1dc7031519a70f8a466c4663c535a1b0922af 100644 (file)
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -51,6 +51,7 @@ RISCV_TUNE("xt-c920v2", generic, generic_ooo_tune_info)
 RISCV_TUNE("xiangshan-nanhu", xiangshan, xiangshan_nanhu_tune_info)
 RISCV_TUNE("xiangshan-kunminghu", xiangshan, generic_ooo_tune_info)
 RISCV_TUNE("spacemit-x60", spacemit_x60, spacemit_x60_tune_info)
+RISCV_TUNE("arc-v-rhx-100-series", arcv_rhx100, arcv_rhx100_tune_info)
 RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info)
 RISCV_TUNE("size", generic, optimize_size_tune_info)
 RISCV_TUNE("mips-p8700", mips_p8700, mips_p8700_tune_info)

diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 1c44bc4e6eceab509dfd961c8415fbb4c19b3e0f..d4bd4310076439086bd14b9e3048e3fc7ac100c0 100644 (file)
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -65,6 +65,7 @@ enum riscv_microarchitecture_type {
   andes_23_series,
   andes_45_series,
   spacemit_x60,
+  arcv_rhx100
 };
 extern enum riscv_microarchitecture_type riscv_microarchitecture;
 

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e09587386ca4cfab45edb776dc45905542fe73e1..7cb9798349295539ab9bfa4e9c41a6286c28802b 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -837,6 +837,32 @@ static const struct riscv_tune_param andes_45_tune_info = {
   true,                                                /* prefer-agnostic.  */
 };
 
+/* Costs to use when optimizing for Synopsys RHX-100.  */
+static const struct riscv_tune_param arcv_rhx100_tune_info = {
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (5)},      /* fp_add */
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (5)},      /* fp_mul */
+  {COSTS_N_INSNS (20), COSTS_N_INSNS (20)},    /* fp_div */
+  {COSTS_N_INSNS (4), COSTS_N_INSNS (4)},      /* int_mul */
+  {COSTS_N_INSNS (27), COSTS_N_INSNS (43)},    /* int_div */
+  4,                                          /* issue_rate */
+  9,                                          /* branch_cost */
+  2,                                          /* memory_cost */
+  8,                                          /* fmv_cost */
+  false,                                      /* slow_unaligned_access */
+  false,                                      /* vector_unaligned_access */
+  true,                                               /* use_divmod_expansion */
+  false,                                      /* overlap_op_by_pieces */
+  true,                                               /* use_zero_stride_load */
+  false,                                      /* speculative_sched_vsetvl */
+  RISCV_FUSE_NOTHING,                         /* fusible_ops */
+  NULL,                                               /* vector cost */
+  NULL,                                               /* function_align */
+  NULL,                                               /* jump_align */
+  NULL,                                               /* loop_align */
+  true,                                               /* prefer-agnostic.  */
+};
+
+
 static bool riscv_avoid_shrink_wrapping_separate ();
 static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
 static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *);

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index ee44132291f0eb4e5393e20ffa9ad8debb2457df..43be603396346ccc2b3bca0e201eacbbd521db01 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -679,7 +679,8 @@
 ;; Keep this in sync with enum riscv_microarchitecture.
 (define_attr "tune"
   "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,
-   tt_ascalon_d8,andes_25_series,andes_23_series,andes_45_series,spacemit_x60"
+   tt_ascalon_d8,andes_25_series,andes_23_series,andes_45_series,spacemit_x60,
+   arcv_rhx100"
   (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
 
 ;; Describe a user's asm statement.
@@ -5203,3 +5204,4 @@
 (include "andes-25-series.md")
 (include "andes-45-series.md")
 (include "spacemit-x60.md")
+(include "arcv-rhx100.md")

diff --git a/gcc/doc/riscv-mtune.texi b/gcc/doc/riscv-mtune.texi
index 6865bd6fbf708f36e4cfe41c20876fbca2991922..6ceb9a93facf4ccc032d59ea734f95633e635324 100644 (file)
--- a/gcc/doc/riscv-mtune.texi
+++ b/gcc/doc/riscv-mtune.texi
@@ -52,6 +52,8 @@ particular CPU name.  Permissible values for this option are:
 
 @samp{spacemit-x60},
 
+@samp{arc-v-rhx-100-series},
+
 @samp{generic-ooo},
 
 @samp{size},