RISC-V: Remove blanket else in riscv_hard_regno_mode_ok.

While looking at PR124439 I noticed that we have unreachable code in
riscv_hard_regno_mode_ok.  Right now we just return false for registers
that don't match one of the first four if conditions.

This patch just removes the else.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Remove else.

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0fbc94297ca5e8661cac7a9aa793b770066a25ee..9a0b5c296d9158d4792262db5792be3b5a7b6f1f 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -10960,8 +10960,6 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
   else if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno)
           || FRM_REG_P (regno))
     return true;
-  else
-    return false;
 
   /* Require same callee-savedness for all registers.  */
   for (unsigned i = 1; i < nregs; i++)