--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
-@@ -155,7 +155,7 @@
+@@ -151,7 +151,7 @@
};
firmware {
/*
* Round rate function for APSS CPU PLL Clock divider.
* It looks up the frequency table and returns the next higher frequency
-@@ -132,7 +155,7 @@ static long clk_cpu_div_round_rate(struc
+@@ -132,7 +155,7 @@ static int clk_cpu_div_determine_rate(st
struct clk_hw *p_hw;
const struct freq_tbl *f;
-- f = qcom_find_freq(pll->freq_tbl, rate);
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
+- f = qcom_find_freq(pll->freq_tbl, req->rate);
++ f = qcom_find_freq_close(pll->freq_tbl, req->rate);
if (!f)
return -EINVAL;
-@@ -154,7 +177,7 @@ static int clk_cpu_div_set_rate(struct c
+@@ -156,7 +179,7 @@ static int clk_cpu_div_set_rate(struct c
const struct freq_tbl *f;
u32 mask;
if (!f)
return -EINVAL;
-@@ -181,6 +204,7 @@ static unsigned long
+@@ -183,6 +206,7 @@ static unsigned long
clk_cpu_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_fepll *pll = to_clk_fepll(hw);
u32 cdiv, pre_div;
u64 rate;
-@@ -201,7 +225,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
+@@ -203,7 +227,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
do_div(rate, pre_div);
--- a/arch/arm/boot/compressed/vmlinux.lds.S
+++ b/arch/arm/boot/compressed/vmlinux.lds.S
-@@ -103,6 +103,13 @@ SECTIONS
+@@ -104,6 +104,13 @@ SECTIONS
_edata = .;
/*
* The image_end section appears after any additional loadable sections
* that the linker may decide to insert in the binary image. Having
-@@ -140,4 +147,4 @@ SECTIONS
+@@ -141,4 +148,4 @@ SECTIONS
ARM_ASSERTS
}
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
-@@ -2401,7 +2401,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
+@@ -2454,7 +2454,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
static const struct sdhci_ops sdhci_msm_ops = {
.reset = sdhci_and_cqhci_reset,
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -19038,6 +19038,13 @@ L: netdev@vger.kernel.org
+@@ -21140,6 +21140,13 @@ L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ethernet/qualcomm/emac/
L: netdev@vger.kernel.org
--- a/drivers/net/ethernet/qualcomm/Kconfig
+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -61,6 +61,17 @@ config QCOM_EMAC
- low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
- Precision Clock Synchronization Protocol.
+@@ -75,6 +75,17 @@ config QCOM_PPE
+ To compile this driver as a module, choose M here. The module
+ will be called qcom-ppe.
+config QCOM_IPQ4019_ESS_EDMA
+ tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
endif # NET_VENDOR_QUALCOMM
--- a/drivers/net/ethernet/qualcomm/Makefile
+++ b/drivers/net/ethernet/qualcomm/Makefile
-@@ -11,4 +11,6 @@ qcauart-objs := qca_uart.o
+@@ -11,5 +11,7 @@ qcauart-objs := qca_uart.o
obj-y += emac/
+obj-$(CONFIG_QCOM_IPQ4019_ESS_EDMA) += ipqess/
+
+ obj-$(CONFIG_QCOM_PPE) += ppe/
obj-$(CONFIG_RMNET) += rmnet/
--- /dev/null
+++ b/drivers/net/ethernet/qualcomm/ipqess/Makefile
+ .of_match_table = ipqess_of_mtable,
+ },
+ .probe = ipqess_axi_probe,
-+ .remove_new = ipqess_axi_remove,
++ .remove = ipqess_axi_remove,
+};
+
+module_platform_driver(ipqess_axi_driver);
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -19044,6 +19044,7 @@ L: netdev@vger.kernel.org
+@@ -21146,6 +21146,7 @@ L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml
F: drivers/net/ethernet/qualcomm/ipqess/
+#endif
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -4850,6 +4850,9 @@ enum skb_ext_id {
- #if IS_ENABLED(CONFIG_MCTP_FLOWS)
- SKB_EXT_MCTP,
+@@ -4920,6 +4920,9 @@ enum skb_ext_id {
+ #if IS_ENABLED(CONFIG_INET_PSP)
+ SKB_EXT_PSP,
#endif
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
+ SKB_EXT_DSA_OOB,
struct dsa_switch;
--- a/net/core/skbuff.c
+++ b/net/core/skbuff.c
-@@ -65,8 +65,12 @@
- #include <linux/kcov.h>
+@@ -66,8 +66,12 @@
#include <linux/iov_iter.h>
+ #include <linux/crc32.h>
#include <linux/if.h>
+#ifdef CONFIG_NET_DSA_TAG_OOB
+#include <linux/dsa/oob.h>
#include <net/dst.h>
#include <net/sock.h>
#include <net/checksum.h>
-@@ -5067,6 +5071,9 @@ static const u8 skb_ext_type_len[] = {
- #if IS_ENABLED(CONFIG_MCTP_FLOWS)
- [SKB_EXT_MCTP] = SKB_EXT_CHUNKSIZEOF(struct mctp_flow),
+@@ -5082,6 +5086,9 @@ static const u8 skb_ext_type_len[] = {
+ #if IS_ENABLED(CONFIG_INET_PSP)
+ [SKB_EXT_PSP] = SKB_EXT_CHUNKSIZEOF(struct psp_skb_ext),
#endif
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
+ [SKB_EXT_DSA_OOB] = SKB_EXT_CHUNKSIZEOF(struct dsa_oob_tag_info),
--- a/drivers/net/ethernet/qualcomm/Kconfig
+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -65,6 +65,7 @@ config QCOM_IPQ4019_ESS_EDMA
+@@ -79,6 +79,7 @@ config QCOM_IPQ4019_ESS_EDMA
tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
depends on (OF && ARCH_QCOM) || COMPILE_TEST
select PHYLINK
if (err)
goto err_notifier_unregister;
-+ dev_set_threaded(netdev, true);
++ dev_set_threaded(netdev, NETDEV_NAPI_THREADED_ENABLED);
+
return 0;
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
-@@ -600,6 +600,54 @@
+@@ -597,6 +597,54 @@
status = "disabled";
};
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
-@@ -600,6 +600,82 @@
+@@ -597,6 +597,82 @@
status = "disabled";
};
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
-@@ -758,6 +758,10 @@
+@@ -755,6 +755,10 @@
ethphy4: ethernet-phy@4 {
reg = <4>;
};
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
-@@ -470,7 +470,7 @@
+@@ -467,7 +467,7 @@
status = "disabled";
Subject: SoC: add qualcomm syscon
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
-@@ -295,4 +295,11 @@ config QCOM_PBS
+@@ -295,6 +295,13 @@ config QCOM_PBS
This module provides the APIs to the client drivers that wants to send the
PBS trigger event to the PBS RAM.
+ functions for various peripherals.
+
endmenu
+
+ config QCOM_UBWC_CONFIG
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
-@@ -39,3 +39,4 @@ obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmo
+@@ -39,4 +39,5 @@ obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmo
qcom_ice-objs += ice.o
obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += qcom_ice.o
obj-$(CONFIG_QCOM_PBS) += qcom-pbs.o
+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
+ obj-$(CONFIG_QCOM_UBWC_CONFIG) += ubwc_config.o
--- /dev/null
+++ b/drivers/soc/qcom/qcom_tcsr.c
@@ -0,0 +1,94 @@
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -206,11 +206,24 @@ struct qcom_pcie_resources_2_3_3 {
+@@ -203,11 +203,24 @@ struct qcom_pcie_resources_2_3_3 {
};
#define QCOM_PCIE_2_4_0_MAX_RESETS 12
};
#define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2
-@@ -710,12 +723,65 @@ static int qcom_pcie_post_init_2_3_2(str
+@@ -727,12 +740,65 @@ static int qcom_pcie_post_init_2_3_2(str
return 0;
}
int ret;
res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
-@@ -754,6 +820,17 @@ static void qcom_pcie_deinit_2_4_0(struc
+@@ -771,6 +837,17 @@ static void qcom_pcie_deinit_2_4_0(struc
clk_bulk_disable_unprepare(res->num_clks, res->clks);
}
static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
-@@ -1336,6 +1413,16 @@ static const struct qcom_pcie_ops ops_2_
+@@ -1379,6 +1456,16 @@ static const struct qcom_pcie_ops ops_2_
.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
};
/* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
static const struct qcom_pcie_ops ops_2_3_3 = {
.get_resources = qcom_pcie_get_resources_2_3_3,
-@@ -1404,6 +1491,10 @@ static const struct qcom_pcie_cfg cfg_2_
+@@ -1457,6 +1544,10 @@ static const struct qcom_pcie_cfg cfg_2_
.ops = &ops_2_4_0,
};
static const struct qcom_pcie_cfg cfg_2_7_0 = {
.ops = &ops_2_7_0,
};
-@@ -1827,6 +1918,7 @@ static const struct of_device_id qcom_pc
+@@ -2016,6 +2107,7 @@ static const struct of_device_id qcom_pc
{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
+ { .compatible = "qcom,pcie-ipq4019-lantiq-hack", .data = &cfg_2_4_0_lantiq_hack },
+ { .compatible = "qcom,pcie-ipq5018", .data = &cfg_2_9_0 },
{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
- { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
-@@ -2095,7 +2095,8 @@ err:
+@@ -2465,7 +2465,8 @@ static int qcom_scm_probe(struct platfor
static void qcom_scm_shutdown(struct platform_device *pdev)
{
/* Clean shutdown, disable download mode to allow normal restart */
--- a/drivers/net/ppp/ppp_generic.c
+++ b/drivers/net/ppp/ppp_generic.c
-@@ -2985,6 +2985,24 @@ char *ppp_dev_name(struct ppp_channel *c
+@@ -3003,6 +3003,24 @@ char *ppp_dev_name(struct ppp_channel *c
return name;
}
/*
* Disconnect a channel from the generic layer.
-@@ -3646,6 +3664,7 @@ EXPORT_SYMBOL(ppp_unregister_channel);
+@@ -3664,6 +3682,7 @@ EXPORT_SYMBOL(ppp_unregister_channel);
EXPORT_SYMBOL(ppp_channel_index);
EXPORT_SYMBOL(ppp_unit_number);
EXPORT_SYMBOL(ppp_dev_name);
projects / thirdparty / openwrt.git / commitdiff
