--- /dev/null
+From 5d029339bb8ce69aeb68280c3de67d3cea456146 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 20 Jan 2014 11:25:35 -0500
+Subject: drm/radeon: add UVD support for OLAND
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 5d029339bb8ce69aeb68280c3de67d3cea456146 upstream.
+
+It seems this got dropped when we merged UVD support
+last year. Add this back now.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_uvd.c | 1 +
+ drivers/gpu/drm/radeon/uvd_v2_2.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/radeon_uvd.c
++++ b/drivers/gpu/drm/radeon/radeon_uvd.c
+@@ -91,6 +91,7 @@ int radeon_uvd_init(struct radeon_device
+ case CHIP_VERDE:
+ case CHIP_PITCAIRN:
+ case CHIP_ARUBA:
++ case CHIP_OLAND:
+ fw_name = FIRMWARE_TAHITI;
+ break;
+
+--- a/drivers/gpu/drm/radeon/uvd_v2_2.c
++++ b/drivers/gpu/drm/radeon/uvd_v2_2.c
+@@ -153,6 +153,7 @@ int uvd_v2_2_resume(struct radeon_device
+ chip_id = 0x01000015;
+ break;
+ case CHIP_PITCAIRN:
++ case CHIP_OLAND:
+ chip_id = 0x01000016;
+ break;
+ case CHIP_ARUBA:
--- /dev/null
+From 6802d4bad83f50081b2788698570218aaff8d10e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 27 Jan 2014 18:29:35 -0500
+Subject: drm/radeon/DCE4+: clear bios scratch dpms bit (v2)
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 6802d4bad83f50081b2788698570218aaff8d10e upstream.
+
+The BlankCrtc table in some DCE8 boards has some
+logic shortcuts for the vbios when this bit is set.
+Clear it for driver use.
+
+v2: fix typo
+
+Bug:
+https://bugs.freedesktop.org/show_bug.cgi?id=73420
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_atombios.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/radeon_atombios.c
++++ b/drivers/gpu/drm/radeon/radeon_atombios.c
+@@ -3944,6 +3944,10 @@ void radeon_atom_initialize_bios_scratch
+ /* tell the bios not to handle mode switching */
+ bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
+
++ /* clear the vbios dpms state */
++ if (ASIC_IS_DCE4(rdev))
++ bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
++
+ if (rdev->family >= CHIP_R600) {
+ WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
+ WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
--- /dev/null
+From 78fe9e545ce6d510b979dc2d8e14096a279fc519 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Tue, 28 Jan 2014 23:49:37 -0500
+Subject: drm/radeon/dce8: workaround for atom BlankCrtc table
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 78fe9e545ce6d510b979dc2d8e14096a279fc519 upstream.
+
+Some DCE8 boards have a funky BlankCrtc table that results
+in a timeout when trying to blank the display. The
+timeout is harmless (all operations needed from the table
+are complete), but wastes time and is confusing to users so
+work around it.
+
+bug:
+https://bugs.freedesktop.org/show_bug.cgi?id=73420
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atombios_crtc.c | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/atombios_crtc.c
++++ b/drivers/gpu/drm/radeon/atombios_crtc.c
+@@ -209,6 +209,16 @@ static void atombios_enable_crtc_memreq(
+ atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+ }
+
++static const u32 vga_control_regs[6] =
++{
++ AVIVO_D1VGA_CONTROL,
++ AVIVO_D2VGA_CONTROL,
++ EVERGREEN_D3VGA_CONTROL,
++ EVERGREEN_D4VGA_CONTROL,
++ EVERGREEN_D5VGA_CONTROL,
++ EVERGREEN_D6VGA_CONTROL,
++};
++
+ static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
+ {
+ struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+@@ -216,13 +226,23 @@ static void atombios_blank_crtc(struct d
+ struct radeon_device *rdev = dev->dev_private;
+ int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
+ BLANK_CRTC_PS_ALLOCATION args;
++ u32 vga_control = 0;
+
+ memset(&args, 0, sizeof(args));
+
++ if (ASIC_IS_DCE8(rdev)) {
++ vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
++ WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
++ }
++
+ args.ucCRTC = radeon_crtc->crtc_id;
+ args.ucBlanking = state;
+
+ atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
++
++ if (ASIC_IS_DCE8(rdev)) {
++ WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
++ }
+ }
+
+ static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
--- /dev/null
+From 919cf555c04e16dafb1fba56904eb23889a812c3 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Sat, 11 Jan 2014 10:55:55 -0500
+Subject: drm/radeon: disable dpm on BTC
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 919cf555c04e16dafb1fba56904eb23889a812c3 upstream.
+
+Still unstable on some boards.
+
+Bugs:
+https://bugs.freedesktop.org/show_bug.cgi?id=73053
+https://bugzilla.kernel.org/show_bug.cgi?id=68571
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_pm.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/radeon_pm.c
++++ b/drivers/gpu/drm/radeon/radeon_pm.c
+@@ -1230,6 +1230,9 @@ int radeon_pm_init(struct radeon_device
+ case CHIP_RV670:
+ case CHIP_RS780:
+ case CHIP_RS880:
++ case CHIP_BARTS:
++ case CHIP_TURKS:
++ case CHIP_CAICOS:
+ case CHIP_CAYMAN:
+ case CHIP_BONAIRE:
+ case CHIP_KABINI:
+@@ -1259,9 +1262,6 @@ int radeon_pm_init(struct radeon_device
+ case CHIP_PALM:
+ case CHIP_SUMO:
+ case CHIP_SUMO2:
+- case CHIP_BARTS:
+- case CHIP_TURKS:
+- case CHIP_CAICOS:
+ case CHIP_ARUBA:
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
--- /dev/null
+From d8e24525094200601236fa64a54cf73e3d682f2e Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 13 Jan 2014 16:47:05 -0500
+Subject: drm/radeon: disable ss on DP for DCE3.x
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit d8e24525094200601236fa64a54cf73e3d682f2e upstream.
+
+Seems to cause problems with certain DP monitors.
+
+Bug:
+https://bugs.freedesktop.org/show_bug.cgi?id=40699
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/atombios_crtc.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/atombios_crtc.c
++++ b/drivers/gpu/drm/radeon/atombios_crtc.c
+@@ -938,11 +938,14 @@ static bool atombios_crtc_prepare_pll(st
+ radeon_atombios_get_ppll_ss_info(rdev,
+ &radeon_crtc->ss,
+ ATOM_DP_SS_ID1);
+- } else
++ } else {
+ radeon_crtc->ss_enabled =
+ radeon_atombios_get_ppll_ss_info(rdev,
+ &radeon_crtc->ss,
+ ATOM_DP_SS_ID1);
++ }
++ /* disable spread spectrum on DCE3 DP */
++ radeon_crtc->ss_enabled = false;
+ }
+ break;
+ case ATOM_ENCODER_MODE_LVDS:
--- /dev/null
+From e9a321c6b2ac954a7dbf235f419c255a424a1273 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 27 Jan 2014 11:54:44 -0500
+Subject: drm/radeon: fix DAC interrupt handling on DCE5+
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit e9a321c6b2ac954a7dbf235f419c255a424a1273 upstream.
+
+DCE5 and newer hardware only has 1 DAC. Use the correct
+offset. This may fix display problems on certain board
+configurations.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen.c | 4 ++--
+ drivers/gpu/drm/radeon/si.c | 2 +-
+ drivers/gpu/drm/radeon/sid.h | 2 +-
+ 3 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -4298,8 +4298,8 @@ void evergreen_disable_interrupt_state(s
+ WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
+ }
+
+- /* only one DAC on DCE6 */
+- if (!ASIC_IS_DCE6(rdev))
++ /* only one DAC on DCE5 */
++ if (!ASIC_IS_DCE5(rdev))
+ WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
+ WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
+
+--- a/drivers/gpu/drm/radeon/si.c
++++ b/drivers/gpu/drm/radeon/si.c
+@@ -5566,7 +5566,7 @@ static void si_disable_interrupt_state(s
+ }
+
+ if (!ASIC_IS_NODCE(rdev)) {
+- WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
++ WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
+
+ tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
+ WREG32(DC_HPD1_INT_CONTROL, tmp);
+--- a/drivers/gpu/drm/radeon/sid.h
++++ b/drivers/gpu/drm/radeon/sid.h
+@@ -815,7 +815,7 @@
+ # define GRPH_PFLIP_INT_MASK (1 << 0)
+ # define GRPH_PFLIP_INT_TYPE (1 << 8)
+
+-#define DACA_AUTODETECT_INT_CONTROL 0x66c8
++#define DAC_AUTODETECT_INT_CONTROL 0x67c8
+
+ #define DC_HPD1_INT_STATUS 0x601c
+ #define DC_HPD2_INT_STATUS 0x6028
--- /dev/null
+From 10e9ffae463396c5a25fdfe8a48d7c98a87f6b85 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Jan 2014 18:02:59 -0500
+Subject: drm/radeon: fix surface sync in fence on cayman (v2)
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 10e9ffae463396c5a25fdfe8a48d7c98a87f6b85 upstream.
+
+We need to set the engine bit to select the ME and
+also set the full cache bit. Should help stability
+on TN and cayman.
+
+V2: fix up surface sync in ib execute as well
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/ni.c | 16 +++++++---------
+ drivers/gpu/drm/radeon/nid.h | 1 +
+ 2 files changed, 8 insertions(+), 9 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/ni.c
++++ b/drivers/gpu/drm/radeon/ni.c
+@@ -1330,13 +1330,12 @@ void cayman_fence_ring_emit(struct radeo
+ {
+ struct radeon_ring *ring = &rdev->ring[fence->ring];
+ u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
++ u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
++ PACKET3_SH_ACTION_ENA;
+
+ /* flush read cache over gart for this vmid */
+- radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+- radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
+- radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
+- radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
++ radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
+ radeon_ring_write(ring, 0xFFFFFFFF);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, 10); /* poll interval */
+@@ -1352,6 +1351,8 @@ void cayman_fence_ring_emit(struct radeo
+ void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
+ {
+ struct radeon_ring *ring = &rdev->ring[ib->ring];
++ u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
++ PACKET3_SH_ACTION_ENA;
+
+ /* set to DX10/11 mode */
+ radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
+@@ -1376,14 +1377,11 @@ void cayman_ring_ib_execute(struct radeo
+ (ib->vm ? (ib->vm->id << 24) : 0));
+
+ /* flush read cache over gart for this vmid */
+- radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+- radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
+- radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
+ radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
+- radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
++ radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
+ radeon_ring_write(ring, 0xFFFFFFFF);
+ radeon_ring_write(ring, 0);
+- radeon_ring_write(ring, 10); /* poll interval */
++ radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */
+ }
+
+ static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
+--- a/drivers/gpu/drm/radeon/nid.h
++++ b/drivers/gpu/drm/radeon/nid.h
+@@ -1154,6 +1154,7 @@
+ # define PACKET3_DB_ACTION_ENA (1 << 26)
+ # define PACKET3_SH_ACTION_ENA (1 << 27)
+ # define PACKET3_SX_ACTION_ENA (1 << 28)
++# define PACKET3_ENGINE_ME (1 << 31)
+ #define PACKET3_ME_INITIALIZE 0x44
+ #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
+ #define PACKET3_COND_WRITE 0x45
--- /dev/null
+From 9babd35ad72af631547c7ca294bc2e931cc40e58 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Fri, 24 Jan 2014 14:59:42 -0500
+Subject: drm/radeon/runpm: don't runtime suspend non-PX cards
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 9babd35ad72af631547c7ca294bc2e931cc40e58 upstream.
+
+Prevent runtime suspend of non-PX GPUs. Runtime suspend is
+not what we want in those cases.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/radeon_drv.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/gpu/drm/radeon/radeon_drv.c
++++ b/drivers/gpu/drm/radeon/radeon_drv.c
+@@ -400,6 +400,9 @@ static int radeon_pmops_runtime_suspend(
+ if (radeon_runtime_pm == 0)
+ return -EINVAL;
+
++ if (radeon_runtime_pm == -1 && !radeon_is_px())
++ return -EINVAL;
++
+ drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+ drm_kms_helper_poll_disable(drm_dev);
+ vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
+@@ -422,6 +425,9 @@ static int radeon_pmops_runtime_resume(s
+ if (radeon_runtime_pm == 0)
+ return -EINVAL;
+
++ if (radeon_runtime_pm == -1 && !radeon_is_px())
++ return -EINVAL;
++
+ drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
+
+ pci_set_power_state(pdev, PCI_D0);
--- /dev/null
+From ffcda352b569dcf5be5c8a5f57545794acf4adb9 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 27 Jan 2014 13:04:56 -0500
+Subject: drm/radeon: set si_notify_smc_display_change properly
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit ffcda352b569dcf5be5c8a5f57545794acf4adb9 upstream.
+
+This is effectively a revert of 4573388c92ee60b4ed72b8d95b73df861189988c.
+
+Forcing a display active when there is none causes problems with
+dpm on some SI boards which results in improperly initialized
+dpm state and boot failures on some boards. As for the bug commit
+4573388c92ee tried to address, one can manually force the state to
+high for better performance when using the card as a headless compute
+node until a better fix is developed.
+
+bugs:
+https://bugs.freedesktop.org/show_bug.cgi?id=73788
+https://bugs.freedesktop.org/show_bug.cgi?id=69395
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/si_dpm.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/si_dpm.c
++++ b/drivers/gpu/drm/radeon/si_dpm.c
+@@ -3591,10 +3591,9 @@ static void si_program_display_gap(struc
+
+ /* Setting this to false forces the performance state to low if the crtcs are disabled.
+ * This can be a problem on PowerXpress systems or if you want to use the card
+- * for offscreen rendering or compute if there are no crtcs enabled. Set it to
+- * true for now so that performance scales even if the displays are off.
++ * for offscreen rendering or compute if there are no crtcs enabled.
+ */
+- si_notify_smc_display_change(rdev, true /*rdev->pm.dpm.new_active_crtc_count > 0*/);
++ si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
+ }
+
+ static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
--- /dev/null
+From d45b964a22cad962d3ede1eba8d24f5cee7b2a92 Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 16 Jan 2014 18:11:47 -0500
+Subject: drm/radeon: set the full cache bit for fences on r7xx+
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit d45b964a22cad962d3ede1eba8d24f5cee7b2a92 upstream.
+
+Needed to properly flush the read caches for fences.
+
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/r600.c | 13 +++++++------
+ drivers/gpu/drm/radeon/r600d.h | 1 +
+ 2 files changed, 8 insertions(+), 6 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/r600.c
++++ b/drivers/gpu/drm/radeon/r600.c
+@@ -2607,14 +2607,17 @@ void r600_fence_ring_emit(struct radeon_
+ struct radeon_fence *fence)
+ {
+ struct radeon_ring *ring = &rdev->ring[fence->ring];
++ u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
++ PACKET3_SH_ACTION_ENA;
++
++ if (rdev->family >= CHIP_RV770)
++ cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
+
+ if (rdev->wb.use_event) {
+ u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
+ /* flush read cache over gart */
+ radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
+- radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
+- PACKET3_VC_ACTION_ENA |
+- PACKET3_SH_ACTION_ENA);
++ radeon_ring_write(ring, cp_coher_cntl);
+ radeon_ring_write(ring, 0xFFFFFFFF);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, 10); /* poll interval */
+@@ -2628,9 +2631,7 @@ void r600_fence_ring_emit(struct radeon_
+ } else {
+ /* flush read cache over gart */
+ radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
+- radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
+- PACKET3_VC_ACTION_ENA |
+- PACKET3_SH_ACTION_ENA);
++ radeon_ring_write(ring, cp_coher_cntl);
+ radeon_ring_write(ring, 0xFFFFFFFF);
+ radeon_ring_write(ring, 0);
+ radeon_ring_write(ring, 10); /* poll interval */
+--- a/drivers/gpu/drm/radeon/r600d.h
++++ b/drivers/gpu/drm/radeon/r600d.h
+@@ -1575,6 +1575,7 @@
+ # define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
+ #define PACKET3_SURFACE_SYNC 0x43
+ # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
++# define PACKET3_FULL_CACHE_ENA (1 << 20) /* r7xx+ only */
+ # define PACKET3_TC_ACTION_ENA (1 << 23)
+ # define PACKET3_VC_ACTION_ENA (1 << 24)
+ # define PACKET3_CB_ACTION_ENA (1 << 25)
--- /dev/null
+From 56492e0fac2dbaf7735ffd66b206a90624917789 Mon Sep 17 00:00:00 2001
+From: Marek Olšák <marek.olsak@amd.com>
+Date: Wed, 8 Jan 2014 18:16:26 +0100
+Subject: drm/radeon: skip colorbuffer checking if COLOR_INFO.FORMAT is set to INVALID
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Marek Olšák <marek.olsak@amd.com>
+
+commit 56492e0fac2dbaf7735ffd66b206a90624917789 upstream.
+
+This fixes a bug which was causing rejections of valid GPU commands
+from userspace.
+
+Signed-off-by: Marek Olšák <marek.olsak@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/radeon/evergreen_cs.c | 5 ++++-
+ drivers/gpu/drm/radeon/r600_cs.c | 5 ++++-
+ 2 files changed, 8 insertions(+), 2 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/evergreen_cs.c
++++ b/drivers/gpu/drm/radeon/evergreen_cs.c
+@@ -967,7 +967,10 @@ static int evergreen_cs_track_check(stru
+ if (track->cb_dirty) {
+ tmp = track->cb_target_mask;
+ for (i = 0; i < 8; i++) {
+- if ((tmp >> (i * 4)) & 0xF) {
++ u32 format = G_028C70_FORMAT(track->cb_color_info[i]);
++
++ if (format != V_028C70_COLOR_INVALID &&
++ (tmp >> (i * 4)) & 0xF) {
+ /* at least one component is enabled */
+ if (track->cb_color_bo[i] == NULL) {
+ dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
+--- a/drivers/gpu/drm/radeon/r600_cs.c
++++ b/drivers/gpu/drm/radeon/r600_cs.c
+@@ -749,7 +749,10 @@ static int r600_cs_track_check(struct ra
+ }
+
+ for (i = 0; i < 8; i++) {
+- if ((tmp >> (i * 4)) & 0xF) {
++ u32 format = G_0280A0_FORMAT(track->cb_color_info[i]);
++
++ if (format != V_0280A0_COLOR_INVALID &&
++ (tmp >> (i * 4)) & 0xF) {
+ /* at least one component is enabled */
+ if (track->cb_color_bo[i] == NULL) {
+ dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
--- /dev/null
+From 7f4237c6dad7c959615b896d3c6c728c37943f4d Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Thu, 9 Jan 2014 10:59:56 -0500
+Subject: Revert "drm/radeon: disable CIK CP semaphores for now"
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit 7f4237c6dad7c959615b896d3c6c728c37943f4d upstream.
+
+This reverts commit 99b4f25122f43210278cde17a9d100906235a074.
+
+Semaphores work fine after further review and testing.
+
+---
+ drivers/gpu/drm/radeon/cik.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+--- a/drivers/gpu/drm/radeon/cik.c
++++ b/drivers/gpu/drm/radeon/cik.c
+@@ -3566,8 +3566,6 @@ bool cik_semaphore_ring_emit(struct rade
+ struct radeon_semaphore *semaphore,
+ bool emit_wait)
+ {
+-/* TODO: figure out why semaphore cause lockups */
+-#if 0
+ uint64_t addr = semaphore->gpu_addr;
+ unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
+
+@@ -3576,9 +3574,6 @@ bool cik_semaphore_ring_emit(struct rade
+ radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
+
+ return true;
+-#else
+- return false;
+-#endif
+ }
+
+ /**
dib8000-fix-regression-with-dib807x.patch
m88rs2000-add-m88rs2000_set_carrieroffset.patch
m88rs2000-set-symbol-rate-accurately.patch
+drm-radeon-skip-colorbuffer-checking-if-color_info.format-is-set-to-invalid.patch
+revert-drm-radeon-disable-cik-cp-semaphores-for-now.patch
+drm-radeon-disable-dpm-on-btc.patch
+drm-radeon-disable-ss-on-dp-for-dce3.x.patch
+drm-radeon-fix-surface-sync-in-fence-on-cayman-v2.patch
+drm-radeon-set-the-full-cache-bit-for-fences-on-r7xx.patch
+drm-radeon-add-uvd-support-for-oland.patch
+drm-radeon-runpm-don-t-runtime-suspend-non-px-cards.patch
+drm-radeon-fix-dac-interrupt-handling-on-dce5.patch
+drm-radeon-set-si_notify_smc_display_change-properly.patch
+drm-radeon-dce4-clear-bios-scratch-dpms-bit-v2.patch
+drm-radeon-dce8-workaround-for-atom-blankcrtc-table.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
