drm/amdgpu: fix JPEG v5.0.0 queue reset failure in DPG mode

In DPG mode jpeg_v5_0_0_ring_reset() takes the DPG stop path, which only
clears the JPEG_PG_MODE bit and never resets the JRBC. A hung ring is not
recovered: the post-reset ring test times out and the driver falls back to
a full MODE1 reset.

Temporarily force the static power-gating path during the reset so the
stop/start sequence power-cycles the JPEG block (JMI soft reset + power
off/on), matching the jpeg_v4_0 reset which has no DPG path.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 79b3612827d1adcd2008cd585961fa35a6ff20f2)
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
index 72a4b2d0676fa4cc7af52c93bef2febed2de8cb4..c696a0dea32ce14a0c20fb9313b91f0b3c439652 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
@@ -648,15 +648,28 @@ static int jpeg_v5_0_0_ring_reset(struct amdgpu_ring *ring,
                                  unsigned int vmid,
                                  struct amdgpu_fence *timedout_fence)
 {
+       struct amdgpu_device *adev = ring->adev;
+       u32 pg_flags = adev->pg_flags;
        int r;
 
        amdgpu_ring_reset_helper_begin(ring, timedout_fence);
-       r = jpeg_v5_0_0_stop(ring->adev);
-       if (r)
-               return r;
-       r = jpeg_v5_0_0_start(ring->adev);
+
+       /*
+        * The DPG stop path only clears the JPEG_PG_MODE bit and never resets a
+        * hung JRBC, so the post-reset ring test times out and the driver falls
+        * back to a full MODE1 reset. Temporarily force the static power-gating
+        * path so the stop/start sequence actually power-cycles the JPEG block
+        * (JMI soft reset + ONO1 power off/on), matching the working jpeg_v4_0
+        * reset.
+        */
+       adev->pg_flags &= ~AMD_PG_SUPPORT_JPEG_DPG;
+       r = jpeg_v5_0_0_stop(adev);
+       if (!r)
+               r = jpeg_v5_0_0_start(adev);
+       adev->pg_flags = pg_flags;
        if (r)
                return r;
+
        return amdgpu_ring_reset_helper_end(ring, timedout_fence);
 }