5.10-stable patches

added patches:
	drm-i915-tgl-fix-combo-phy-dpll-fractional-divider-for-38.4mhz-ref-clock.patch

diff --git a/queue-5.10/drm-i915-tgl-fix-combo-phy-dpll-fractional-divider-for-38.4mhz-ref-clock.patch b/queue-5.10/drm-i915-tgl-fix-combo-phy-dpll-fractional-divider-for-38.4mhz-ref-clock.patch
new file mode 100644 (file)
index 0000000..d26cf3b
--- /dev/null
+++ b/queue-5.10/drm-i915-tgl-fix-combo-phy-dpll-fractional-divider-for-38.4mhz-ref-clock.patch
@@ -0,0 +1,126 @@
+From 0e2497e334de42dbaaee8e325241b5b5b34ede7e Mon Sep 17 00:00:00 2001
+From: Imre Deak <imre.deak@intel.com>
+Date: Sat, 3 Oct 2020 03:18:46 +0300
+Subject: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Imre Deak <imre.deak@intel.com>
+
+commit 0e2497e334de42dbaaee8e325241b5b5b34ede7e upstream.
+
+Apply Display WA #22010492432 for combo PHY PLLs too. This should fix a
+problem where the PLL output frequency is slightly off with the current
+PLL fractional divider value.
+
+I haven't seen an actual case where this causes a problem, but let's
+follow the spec. It's also needed on some EHL platforms, but for that we
+also need a way to distinguish the affected EHL SKUs, so I leave that
+for a follow-up.
+
+v2:
+- Apply the WA at one place when calculating the PLL dividers from the
+  frequency and the frequency from the dividers for all the combo PLL
+  use cases (DP, HDMI, TBT). (Ville)
+
+Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Imre Deak <imre.deak@intel.com>
+Link: https://patchwork.freedesktop.org/patch/msgid/20201003001846.1271151-6-imre.deak@intel.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+
+---
+ drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   41 +++++++++++++++-----------
+ 1 file changed, 25 insertions(+), 16 deletions(-)
+
+--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
++++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+@@ -2622,11 +2622,22 @@ static bool cnl_ddi_hdmi_pll_dividers(st
+       return true;
+ }
+ 
++/*
++ * Display WA #22010492432: tgl
++ * Program half of the nominal DCO divider fraction value.
++ */
++static bool
++tgl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
++{
++      return IS_TIGERLAKE(i915) && i915->dpll.ref_clks.nssc == 38400;
++}
++
+ static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
+                                   const struct intel_shared_dpll *pll,
+                                   int ref_clock)
+ {
+       const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state;
++      u32 dco_fraction;
+       u32 p0, p1, p2, dco_freq;
+ 
+       p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
+@@ -2669,8 +2680,13 @@ static int __cnl_ddi_wrpll_get_freq(stru
+       dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
+                  ref_clock;
+ 
+-      dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
+-                    DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000;
++      dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
++                     DPLL_CFGCR0_DCO_FRACTION_SHIFT;
++
++      if (tgl_combo_pll_div_frac_wa_needed(dev_priv))
++              dco_fraction *= 2;
++
++      dco_freq += (dco_fraction * ref_clock) / 0x8000;
+ 
+       if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0))
+               return 0;
+@@ -2948,16 +2964,6 @@ static const struct skl_wrpll_params tgl
+       /* the following params are unused */
+ };
+ 
+-/*
+- * Display WA #22010492432: tgl
+- * Divide the nominal .dco_fraction value by 2.
+- */
+-static const struct skl_wrpll_params tgl_tbt_pll_38_4MHz_values = {
+-      .dco_integer = 0x54, .dco_fraction = 0x1800,
+-      /* the following params are unused */
+-      .pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
+-};
+-
+ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
+                                 struct skl_wrpll_params *pll_params)
+ {
+@@ -2991,14 +2997,12 @@ static bool icl_calc_tbt_pll(struct inte
+                       MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
+                       fallthrough;
+               case 19200:
++              case 38400:
+                       *pll_params = tgl_tbt_pll_19_2MHz_values;
+                       break;
+               case 24000:
+                       *pll_params = tgl_tbt_pll_24MHz_values;
+                       break;
+-              case 38400:
+-                      *pll_params = tgl_tbt_pll_38_4MHz_values;
+-                      break;
+               }
+       } else {
+               switch (dev_priv->dpll.ref_clks.nssc) {
+@@ -3065,9 +3069,14 @@ static void icl_calc_dpll_state(struct d
+                               const struct skl_wrpll_params *pll_params,
+                               struct intel_dpll_hw_state *pll_state)
+ {
++      u32 dco_fraction = pll_params->dco_fraction;
++
+       memset(pll_state, 0, sizeof(*pll_state));
+ 
+-      pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(pll_params->dco_fraction) |
++      if (tgl_combo_pll_div_frac_wa_needed(i915))
++              dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
++
++      pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
+                           pll_params->dco_integer;
+ 
+       pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |

diff --git a/queue-5.10/series b/queue-5.10/series
index e48455397449608f62e3a49d843dffed03286bd1..30330be5dd09782a9f666c339039e108d6e38c7a 100644 (file)
--- a/queue-5.10/series
+++ b/queue-5.10/series
@@ -7,3 +7,4 @@ kdev_t-always-inline-major-minor-helper-functions.patch
 bluetooth-fix-attempting-to-set-rpa-timeout-when-unsupported.patch
 alsa-hda-realtek-modify-dell-platform-name.patch
 alsa-hda-hdmi-fix-incorrect-mutex-unlock-in-silent_stream_disable.patch
+drm-i915-tgl-fix-combo-phy-dpll-fractional-divider-for-38.4mhz-ref-clock.patch