realtek: pcs: fix PLL_CML_CTRL for serdes 0/1

Setup of register PLL_CML_CTRL has two issues.

- It clears out bits 4-31 due to a wrong mask
- Setup of bits 0-3 is not generic but depends on the mode of
  serdes 0/1

Fix that by relocating the code and adapting the mask. The error
exists for longer but it has survived the pcs refactoring. Thus
blame the corresponding refactoring commit.

Fixes: b670d48 ("realtek: pcs: rtl838x: refactor imported code")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/21956
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit fdc37760684e784d7c305796c7fba4a9ef891f1c)
Link: https://github.com/openwrt/openwrt/pull/22087
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
index 0a1d994da7a108cc0894290f84a0bb23c71c1ea4..cc1adeeec6d68fbf600eea1cd7e136873d13ea5f 100644 (file)
--- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
+++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
@@ -286,6 +286,9 @@ static struct rtpcs_link *rtpcs_phylink_pcs_to_link(struct phylink_pcs *pcs)
 
 static void rtpcs_838x_sds_patch_01_qsgmii_6275b(struct rtpcs_ctrl *ctrl)
 {
+       /* CKREFBUF_S0S1 for QSGMII */
+       regmap_write_bits(ctrl->map, RTPCS_838X_PLL_CML_CTRL, 0xf, 0xf);
+
        rtpcs_sds_write(SDS(ctrl, 0), 1, 3, 0xf46f);
        rtpcs_sds_write(SDS(ctrl, 0), 1, 2, 0x85fa);
        rtpcs_sds_write(SDS(ctrl, 1), 1, 2, 0x85fa);
@@ -522,18 +525,11 @@ static int rtpcs_838x_sds_patch(struct rtpcs_serdes *sds,
 
 static int rtpcs_838x_init_serdes_common(struct rtpcs_ctrl *ctrl)
 {
-       u32 val;
-
        dev_dbg(ctrl->dev, "Init RTL838X SerDes common\n");
 
        /* enable R/W of some protected registers */
        regmap_write(ctrl->map, RTPCS_838X_INT_RW_CTRL, 0x3);
 
-       regmap_read(ctrl->map, RTPCS_838X_PLL_CML_CTRL, &val);
-       dev_dbg(ctrl->dev, "PLL control register: %x\n", val);
-       regmap_write_bits(ctrl->map, RTPCS_838X_PLL_CML_CTRL, 0xfffffff0,
-                         0xaaaaaaaf & 0xf);
-
        /* power off and reset all SerDes */
        regmap_write(ctrl->map, RTPCS_838X_SDS_CFG_REG, 0x3f);
        regmap_write(ctrl->map, RTPCS_838X_RST_GLB_CTRL_0, 0x10); /* SW_SERDES_RST */