[x86] Adjust gcc.target/i386/vect-strided-?.c for cost compare

With cost comparison and MMX-with-SSE vector width available we
prefer to use V2SImode over V4SImode with shuffles, rightfully
so I think.  The following adds variants with explicit cost
compare enabled and disabled and adjusts the cost comparison
variant accordingly.

	* gcc.target/i386/vect-strided-1.c: Disable vector cost
	comparison.
	* gcc.target/i386/vect-strided-2.c: Likewise.
	* gcc.target/i386/vect-strided-3.c: Likewise.
	* gcc.target/i386/vect-strided-4.c: Likewise.
	* gcc.target/i386/vect-strided-1b.c: Copy of
	gcc.target/i386/vect-strided-1.c, enable vector cost comparison
	and adjust expected code generation.
	* gcc.target/i386/vect-strided-2b.c: Likewise.
	* gcc.target/i386/vect-strided-3b.c: Likewise.
	* gcc.target/i386/vect-strided-4b.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-1.c b/gcc/testsuite/gcc.target/i386/vect-strided-1.c
index db4a06711f11fe76cdef556f0d64db78d20287d8..8e232540bd448e145799a56ef7d23bb5e7a6666a 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/vect-strided-1.c
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -msse2 -mno-avx" } */
+/* { dg-options "-O2 -msse2 -mno-avx --param ix86-vect-compare-costs=0" } */
 
 void foo (int * __restrict a, int *b, int s)
 {

diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-1b.c b/gcc/testsuite/gcc.target/i386/vect-strided-1b.c
new file mode 100644 (file)
index 0000000..6f173ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-1b.c
@@ -0,0 +1,23 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -msse2 -mno-avx --param ix86-vect-compare-costs=1" } */
+
+void foo (int * __restrict a, int *b, int s)
+{
+  for (int i = 0; i < 1024; ++i)
+    {
+      a[8*i+0] = b[s*i+0];
+      a[8*i+1] = b[s*i+1];
+      a[8*i+2] = b[s*i+2];
+      a[8*i+3] = b[s*i+3];
+      a[8*i+4] = b[s*i+4];
+      a[8*i+5] = b[s*i+5];
+      a[8*i+6] = b[s*i+4];
+      a[8*i+7] = b[s*i+5];
+    }
+}
+
+/* Three two-element loads, four two-element stores.  No wider loads
+   or permutes.  */
+/* { dg-final { scan-assembler-times "movq" 7 } } */
+/* { dg-final { scan-assembler-times "movhps" 0 } } */
+/* { dg-final { scan-assembler-times "movups" 0 } } */

diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-2.c b/gcc/testsuite/gcc.target/i386/vect-strided-2.c
index 6fd64e28cf0d3742155af1e1df66c369b5a43cb0..67aa3917c4e47087c57588738b0fd3771415792d 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/vect-strided-2.c
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -msse2 -mno-avx" } */
+/* { dg-options "-O2 -msse2 -mno-avx --param ix86-vect-compare-costs=0" } */
 
 void foo (int * __restrict a, int *b, int s)
 {

diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-2b.c b/gcc/testsuite/gcc.target/i386/vect-strided-2b.c
new file mode 100644 (file)
index 0000000..9eabfbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-2b.c
@@ -0,0 +1,17 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -msse2 -mno-avx --param ix86-vect-compare-costs=1" } */
+
+void foo (int * __restrict a, int *b, int s)
+{
+  for (int i = 0; i < 1024; ++i)
+    {
+      a[4*i+0] = b[s*i+0];
+      a[4*i+1] = b[s*i+1];
+      a[4*i+2] = b[s*i+0];
+      a[4*i+3] = b[s*i+1];
+    }
+}
+
+/* One two-element load, two two-element stores.  */
+/* { dg-final { scan-assembler-times "movq" 3 } } */
+/* { dg-final { scan-assembler-times "movups" 0 } } */

diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-3.c b/gcc/testsuite/gcc.target/i386/vect-strided-3.c
index f9c54a6f71599569792ffe6f92fefb75db25900c..d08d5836a7ad62885ae0e5354f208ec6c6b85c76 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/vect-strided-3.c
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -msse2 -mno-sse4 -fno-tree-slp-vectorize" } */
+/* { dg-options "-O2 -msse2 -mno-sse4 -fno-tree-slp-vectorize --param ix86-vect-compare-costs=0" } */
 
 void foo (int * __restrict a, int *b, int s)
 {

diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-3b.c b/gcc/testsuite/gcc.target/i386/vect-strided-3b.c
new file mode 100644 (file)
index 0000000..829fb0c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-3b.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -msse2 -mno-sse4 -fno-tree-slp-vectorize --param ix86-vect-compare-costs=1" } */
+
+void foo (int * __restrict a, int *b, int s)
+{
+  if (s >= 6)
+    for (int i = 0; i < 1024; ++i)
+      {
+       a[s*i+0] = b[4*i+0];
+       a[s*i+1] = b[4*i+1];
+       a[s*i+2] = b[4*i+2];
+       a[s*i+3] = b[4*i+3];
+       a[s*i+4] = b[4*i+0];
+       a[s*i+5] = b[4*i+1];
+      }
+}
+
+/* The vectorizer generates 3 uint64 stores and two uint64 loads.  */
+/* { dg-final { scan-assembler-times "movq" 5 } } */
+/* { dg-final { scan-assembler-times "movhps" 0 } } */

diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-4.c b/gcc/testsuite/gcc.target/i386/vect-strided-4.c
index 3fb9f07886e33a2b54cf5495704d3723253e4a20..37f6e72c0a9402a840a18c15b034f01c82dc5f2a 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/vect-strided-4.c
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-4.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -msse4.2 -mno-avx -fno-tree-slp-vectorize" } */
+/* { dg-options "-O2 -msse4.2 -mno-avx -fno-tree-slp-vectorize --param ix86-vect-compare-costs=0" } */
 
 void foo (int * __restrict a, int * __restrict b, int *c, int s)
 {

diff --git a/gcc/testsuite/gcc.target/i386/vect-strided-4b.c b/gcc/testsuite/gcc.target/i386/vect-strided-4b.c
new file mode 100644 (file)
index 0000000..3183a5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/vect-strided-4b.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -msse4.2 -mno-avx -fno-tree-slp-vectorize --param ix86-vect-compare-costs=1" } */
+
+void foo (int * __restrict a, int * __restrict b, int *c, int s)
+{
+  if (s >= 2)
+    for (int i = 0; i < 1024; ++i)
+      {
+       a[s*i+0] = c[4*i+0];
+       a[s*i+1] = c[4*i+1];
+       b[s*i+0] = c[4*i+2];
+       b[s*i+1] = c[4*i+3];
+      }
+}
+
+/* Vectorization factor two, two two-element stores using movq
+   and two two-element stores to b via movq.  One reg-reg copy with movq.  */
+/* { dg-final { scan-assembler-times "movq\[^\r\n\]+\\\(" 4 } } */
+/* { dg-final { scan-assembler-times "pextrq" 0 } } */