LoongArch: feclearexcept: skip clearing CAUSE

The comment explaining the reason to clear CAUSE does not make any
sense: it says the next "CTC" instruction would raise the FP exception
of which both the CAUSE and ENABLE bits are set, but LoongArch does not
have the CTC instruction.  LoongArch has the movgr2fcsr instruction but
movgr2fcsr never raises any FP exception, different from the MIPS CTC
instruction.

So we don't really need to care CAUSE at all.

Signed-off-by: Xi Ruoyao <xry111@xry111.site>

diff --git a/sysdeps/loongarch/fpu/fclrexcpt.c b/sysdeps/loongarch/fpu/fclrexcpt.c
index 7ce166659b4d013ef7c57395c22ab83011d1b50f..0c95069a1d84c9868b63922b9b21ab76142709d3 100644 (file)
--- a/sysdeps/loongarch/fpu/fclrexcpt.c
+++ b/sysdeps/loongarch/fpu/fclrexcpt.c
@@ -31,11 +31,8 @@ __feclearexcept (int excepts)
   /* Read the complete control word.  */
   _FPU_GETCW (cw);
 
-  /* Clear exception flag bits and cause bits.  If the cause bit is not
-     cleared, the next CTC instruction (just below) will re-generate the
-     exception.  */
-
-  cw &= ~(excepts | (excepts << CAUSE_SHIFT));
+  /* Clear exception flag bits.  */
+  cw &= ~excepts;
 
   /* Put the new data in effect.  */
   _FPU_SETCW (cw);