drm/i915: move GEN7_ERR_INT snapshot to display irq code

The error interrupt register GEN7_ERR_INT is a display irq
register. Move its GPU error capture to display irq snapshot.

Cc: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260122123759.1701492-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 9adeebb376b189ef72a97e0206e0c24b0f4e7117..0a71840041de825ed279ae9c65404744b0f979e4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -2472,6 +2472,7 @@ void intel_display_irq_init(struct intel_display *display)
 
 struct intel_display_irq_snapshot {
        u32 derrmr;
+       u32 err_int;
 };
 
 struct intel_display_irq_snapshot *
@@ -2486,6 +2487,9 @@ intel_display_irq_snapshot_capture(struct intel_display *display)
        if (DISPLAY_VER(display) >= 6 && DISPLAY_VER(display) < 20 && !HAS_GMCH(display))
                snapshot->derrmr = intel_de_read(display, DERRMR);
 
+       if (DISPLAY_VER(display) == 7)
+               snapshot->err_int = intel_de_read(display, GEN7_ERR_INT);
+
        return snapshot;
 }
 
@@ -2496,4 +2500,5 @@ void intel_display_irq_snapshot_print(const struct intel_display_irq_snapshot *s
                return;
 
        drm_printf(p, "DERRMR: 0x%08x\n", snapshot->derrmr);
+       drm_printf(p, "ERR_INT: 0x%08x\n", snapshot->err_int);
 }

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 303d8d9b77753d8bf8a8c3428b1c8561e4c864d4..31c5341fb9cfb6d54f7e76dbb78373f6ebbcfad4 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -824,9 +824,6 @@ static void err_print_gt_global(struct drm_i915_error_state_buf *m,
                err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
                           gt->fault_data1, gt->fault_data0);
 
-       if (GRAPHICS_VER(m->i915) == 7)
-               err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
-
        if (IS_GRAPHICS_VER(m->i915, 8, 11))
                err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
 
@@ -1929,9 +1926,6 @@ static void gt_record_global_regs(struct intel_gt_coredump *gt)
        if (IS_VALLEYVIEW(i915))
                gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
 
-       if (GRAPHICS_VER(i915) == 7)
-               gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
-
        if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
                gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
                                                        XEHP_FAULT_TLB_DATA0);

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index 91b3df621a492f8de7f579425857ba0ba99b0229..26970c5e291e9b7efd763f4d8295d67da5a83df8 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -149,7 +149,6 @@ struct intel_gt_coredump {
        u32 gtier[6], ngtier;
        u32 forcewake;
        u32 error; /* gen6+ */
-       u32 err_int; /* gen7 */
        u32 fault_data0; /* gen8, gen9 */
        u32 fault_data1; /* gen8, gen9 */
        u32 done_reg;