Merge branch 'master' into v2.1

diff --cc src/lj_asm_mips.h
index d663aa0fbe791b06b9a6ca467cf3c183f7fbdacb,03270ccaa69c5504d584e6370af4e882802d69b3..dd821c702091b1e735fb1774f739a6e4c517af2f
--- 1/src/lj_asm_mips.h
--- 2/src/lj_asm_mips.h
+++ b/src/lj_asm_mips.h
@@@ -453,16 -443,14 +453,13 @@@ static void asm_conv(ASMState *as, IRIn
        /* y = (x ^ 0x8000000) + 2147483648.0 */
        Reg left = ra_alloc1(as, lref, RSET_GPR);
        Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, dest));
-       emit_fgh(as, irt_isfloat(ir->t) ? MIPSI_ADD_S : MIPSI_ADD_D,
-              dest, dest, tmp);
-       emit_fg(as, irt_isfloat(ir->t) ? MIPSI_CVT_S_W : MIPSI_CVT_D_W,
-             dest, dest);
        if (irt_isfloat(ir->t))
-       emit_lsptr(as, MIPSI_LWC1, (tmp & 31),
-                  (void *)&as->J->k32[LJ_K32_2P31], RSET_GPR);
-       else
-       emit_lsptr(as, MIPSI_LDC1, (tmp & 31),
-                  (void *)&as->J->k64[LJ_K64_2P31], RSET_GPR);
+       emit_fg(as, MIPSI_CVT_S_D, dest, dest);
+       /* Must perform arithmetic with doubles to keep the precision. */
+       emit_fgh(as, MIPSI_ADD_D, dest, dest, tmp);
+       emit_fg(as, MIPSI_CVT_D_W, dest, dest);
+       emit_lsptr(as, MIPSI_LDC1, (tmp & 31),
 -               (void *)lj_ir_k64_find(as->J, U64x(41e00000,00000000)),
 -               RSET_GPR);
++               (void *)&as->J->k64[LJ_K64_2P31], RSET_GPR);
        emit_tg(as, MIPSI_MTC1, RID_TMP, dest);
        emit_dst(as, MIPSI_XOR, RID_TMP, RID_TMP, left);
        emit_ti(as, MIPSI_LUI, RID_TMP, 0x8000);

diff --cc src/lj_target_mips.h
index 308dd7ce3f2a97ab5a17e8bee5d34805bfce7b09,bed174b8e57c8dcd379151ea1abb10253a98b92a..1b061943207d2968d4b9e1642d95652b6b4877fa
--- 1/src/lj_target_mips.h
--- 2/src/lj_target_mips.h
+++ b/src/lj_target_mips.h
@@@ -74,15 -63,11 +75,15 @@@ enum 
  
  /* -- Register sets ------------------------------------------------------- */
  
- /* Make use of all registers, except ZERO, TMP, SP, SYS1, SYS2 and JGL. */
+ /* Make use of all registers, except ZERO, TMP, SP, SYS1, SYS2, JGL and GP. */
  #define RSET_FIXED \
    (RID2RSET(RID_ZERO)|RID2RSET(RID_TMP)|RID2RSET(RID_SP)|\
-    RID2RSET(RID_SYS1)|RID2RSET(RID_SYS2)|RID2RSET(RID_JGL))
+    RID2RSET(RID_SYS1)|RID2RSET(RID_SYS2)|RID2RSET(RID_JGL)|RID2RSET(RID_GP))
  #define RSET_GPR      (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED)
 +#if LJ_SOFTFP
 +#define RSET_FPR      0
 +#else
 +#if LJ_32
  #define RSET_FPR \
    (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\
     RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\
@@@ -97,11 -78,7 +98,11 @@@
  
  #define RSET_SCRATCH_GPR \
    (RSET_RANGE(RID_R1, RID_R15+1)|\
-    RID2RSET(RID_R24)|RID2RSET(RID_R25)|RID2RSET(RID_R28))
+    RID2RSET(RID_R24)|RID2RSET(RID_R25))
 +#if LJ_SOFTFP
 +#define RSET_SCRATCH_FPR      0
 +#else
 +#if LJ_32
  #define RSET_SCRATCH_FPR \
    (RID2RSET(RID_F0)|RID2RSET(RID_F2)|RID2RSET(RID_F4)|RID2RSET(RID_F6)|\
     RID2RSET(RID_F8)|RID2RSET(RID_F10)|RID2RSET(RID_F12)|RID2RSET(RID_F14)|\