[PATCH] RISC-V: Support Zalasr extension.

This patch support RISC-V Zalasr[1](load-acquire/store-release) extension. Based on Edwin Lu's old patch:
https://patchwork.sourceware.org/project/gcc/patch/20250410214940.2712673-1-ewlu@rivosinc.com/

[1] https://docs.riscv.org/reference/isa/extensions/zalasr/_attachments/riscv-zalasr.pdf

Co-Authored-by: Edwin Lu <ewlu@rivosinc.com>
gcc/ChangeLog:

	* config/riscv/riscv-ext.def: New extension.
	* config/riscv/riscv-ext.opt: Ditto.
	* config/riscv/sync-rvwmo.md: Add check for zalasr.
	* config/riscv/sync-ztso.md: Ditto.
	* doc/riscv-ext.texi: New extension.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/amo/a-rvwmo-fence.c: Disable zalasr from -march.
	* gcc.target/riscv/amo/a-rvwmo-load-acquire.c: Ditto.
	* gcc.target/riscv/amo/a-rvwmo-load-relaxed.c: Ditto.
	* gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/a-rvwmo-store-relaxed.c: Ditto.
	* gcc.target/riscv/amo/a-rvwmo-store-release.c: Ditto.
	* gcc.target/riscv/amo/a-ztso-fence.c: Ditto.
	* gcc.target/riscv/amo/a-ztso-load-acquire.c: Ditto.
	* gcc.target/riscv/amo/a-ztso-load-relaxed.c: Ditto.
	* gcc.target/riscv/amo/a-ztso-load-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/a-ztso-store-relaxed.c: Ditto.
	* gcc.target/riscv/amo/a-ztso-store-release.c: Ditto.
	* gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c: Ditto.
	* gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c: Ditto.
	* gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c: Ditto.
	* gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c: Ditto.
	* gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c: Ditto.
	* gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c: Ditto.
	* gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c: Ditto.
	* gcc.target/riscv/amo/zabha-zacas-atomic-cas.c: Ditto.
	* gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c: Ditto.
	* gcc.target/riscv/amo/zabha-ztso-amo-add-char.c: Ditto.
	* gcc.target/riscv/amo/zabha-ztso-amo-add-short.c: Ditto.
	* gcc.target/riscv/amo/zacas-char-requires-zabha.c: Ditto.
	* gcc.target/riscv/amo/zacas-char-requires-zacas.c: Ditto.
	* gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c: Ditto.
	* gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c: Ditto.
	* gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c: Ditto.
	* gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc: Ditto.
	* gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c: Ditto.
	* gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c: Ditto.
	* gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c: Ditto.
	* lib/target-supports.exp: Add zalasr checks.
	* gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c: New test.
	* gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c: New test.
	* gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c: New test.
	* gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c: New test.
	* gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c: New test.
	* gcc.target/riscv/amo/zalasr-rvwmo-store-release.c: New test.
	* gcc.target/riscv/amo/zalasr-ztso-load-acquire.c: New test.
	* gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c: New test.
	* gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c: New test.
	* gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c: New test.
	* gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c: New test.
	* gcc.target/riscv/amo/zalasr-ztso-store-release.c: New test.

	Co-Authored-by: Edwin Lu <ewlu@rivosinc.com>

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 1621e81b011e575a4a396aeb1031f007889083f8..1993e8991483de392634a4370e1e04076a3474bf 100644 (file)
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -545,6 +545,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ 26,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ zalasr,
+  /* UPPERCASE_NAME */ ZALASR,
+  /* FULL_NAME */ "Atomic load-acquire and store-release extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ za,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ zalrsc,
   /* UPPERCASE_NAME */ ZALRSC,

diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index 18402ea97c7771642e4b56a4d8f30bb219296360..7bf3d4effc6336781d9c9f1670eb939326bdcb22 100644 (file)
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -176,6 +176,8 @@ Mask(ZABHA) Var(riscv_za_subext)
 
 Mask(ZACAS) Var(riscv_za_subext)
 
+Mask(ZALASR) Var(riscv_za_subext)
+
 Mask(ZALRSC) Var(riscv_za_subext)
 
 Mask(ZAWRS) Var(riscv_za_subext)

diff --git a/gcc/config/riscv/sync-rvwmo.md b/gcc/config/riscv/sync-rvwmo.md
index ed65cecf51438989f88330597ff0fe30ccdff182..be2a7303854993e523ceca2b9dff40e5b721c3c0 100644 (file)
--- a/gcc/config/riscv/sync-rvwmo.md
+++ b/gcc/config/riscv/sync-rvwmo.md
@@ -61,11 +61,12 @@
       return "fence\trw,rw\;"
             "<load>\t%0,%1\;"
             "fence\tr,rw";
+    if (TARGET_ZALASR && model == MEMMODEL_ACQUIRE)
+      return "<load>.aq\t%0,%1";
     if (model == MEMMODEL_ACQUIRE)
       return "<load>\t%0,%1\;"
             "fence\tr,rw";
-    else
-      return "<load>\t%0,%1";
+    return "<load>\t%0,%1";
   }
   [(set_attr "type" "multi")
    (set (attr "length")
@@ -86,6 +87,10 @@
     enum memmodel model = (enum memmodel) INTVAL (operands[2]);
     model = memmodel_base (model);
 
+    if (TARGET_ZALASR
+       && (model == MEMMODEL_RELEASE || model == MEMMODEL_SEQ_CST))
+      return "<store>.rl\t%z1,%0";
+
     if (model == MEMMODEL_SEQ_CST)
       return "fence\trw,w\;"
             "<store>\t%z1,%0\;"
@@ -93,8 +98,8 @@
     if (model == MEMMODEL_RELEASE)
       return "fence\trw,w\;"
             "<store>\t%z1,%0";
-    else
-      return "<store>\t%z1,%0";
+
+    return "<store>\t%z1,%0";
   }
   [(set_attr "type" "multi")
    (set (attr "length")

diff --git a/gcc/config/riscv/sync-ztso.md b/gcc/config/riscv/sync-ztso.md
index 689025a4b2111af21d8b52785f9514ee6ca18572..4f3eddd0da0dd198aad6caa9869433af5f82150c 100644 (file)
--- a/gcc/config/riscv/sync-ztso.md
+++ b/gcc/config/riscv/sync-ztso.md
@@ -51,11 +51,13 @@
     enum memmodel model = (enum memmodel) INTVAL (operands[2]);
     model = memmodel_base (model);
 
+    /* Ignoring RCsc atomic load-acquire on MEMMODEL_SEQ_CST due to
+       Note 3 abi break for when TARGET_ZALASR is enabled.  */
     if (model == MEMMODEL_SEQ_CST)
       return "fence\trw,rw\;"
             "<load>\t%0,%1";
-    else
-      return "<load>\t%0,%1";
+
+    return "<load>\t%0,%1";
   }
   [(set_attr "type" "multi")
    (set (attr "length")
@@ -74,11 +76,14 @@
     enum memmodel model = (enum memmodel) INTVAL (operands[2]);
     model = memmodel_base (model);
 
+    if (TARGET_ZALASR && (model == MEMMODEL_SEQ_CST))
+      return "<store>.rl\t%z1,%0";
+
     if (model == MEMMODEL_SEQ_CST)
       return "<store>\t%z1,%0\;"
             "fence\trw,rw";
-    else
-      return "<store>\t%z1,%0";
+
+    return "<store>\t%z1,%0";
   }
   [(set_attr "type" "multi")
    (set (attr "length")

diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 36b4dff31ff4d58e45aa3a1a9730d3fd5a75ba7e..bf4f56a620124e5c9e39f0379c7ad032ae17f86a 100644 (file)
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -158,6 +158,10 @@
 @tab 1.0
 @tab Atomic compare-and-swap instructions extension
 
+@item @samp{zalasr}
+@tab 1.0
+@tab Atomic load-acquire and store-release extension
+
 @item @samp{zalrsc}
 @tab 1.0
 @tab Load-reserved/store-conditional subset of the A extension

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c
index 6803bf92aa32b91bad563f7cb22ed69323283e1e..3947923e6ea4de2a09ff97a107353448820b4734 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-fence.c
@@ -2,6 +2,7 @@
 /* Verify that fence mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c
index 93a0c68ae8a92bfac187486f36969f5ca1bf4f6f..810e7959508bf7d8bd5c18a64ba1692f0459982a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-acquire.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c
index 2403d53c13128e2db0fa6cf4dd0821ca94317377..01a1e3c5c8635e134ad642b7e01130a74dc91db0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-relaxed.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c
index 31b35cf9f6af5092a9cc971819861e704f51a997..ee728675155f4879e50820fe2608274ad3a2782d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-load-seq-cst.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
index 45c9abb1425e300f17f8bd6aa648dc06fd35d4d5..b3ec4e1061b1904f58ef8a706335b21790608ebb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-compat-seq-cst.c
@@ -3,6 +3,7 @@
    mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
index 4b321b2b75fdfb56af5044b613bd86688a022cd6..2f224f993de44a206946b48cfe81f16de91df661 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-relaxed.c
@@ -2,6 +2,7 @@
 /* Verify that store mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
index a2a617c4d15474be3d9add26f19aa6d6e631b724..6daca225d2407660c9487e365419922089a81cb3 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-rvwmo-store-release.c
@@ -2,6 +2,7 @@
 /* Verify that store mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c
index 153f6ef8a3d5a3dad65507347f879e2c54577efe..d432cdc2ffc2ed7dab7c6e89bda455759ce3a7e7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-fence.c
@@ -2,6 +2,7 @@
 /* Verify that fence mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c
index 76a12059f391f84d899d5de8628fdcdd41b2347f..f221169def9ff5ebab7360f5f7eea2bb080b721e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-acquire.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c
index c4ee56e2cc0eb36de0eabed11a63bdd28e01b369..2ee094679eb4531d8e7f017463ac4ae050b38091 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-relaxed.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c
index 7163311433ccd463254cfbd9672d7ab07831ccca..8ad64e6579cf7085e25dbb73e3f8d50e0fd2d7b4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-load-seq-cst.c
@@ -2,6 +2,7 @@
 /* Verify that load mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
index 2f4c9124aaf9f74662195f977729ea37e10328e5..a1cefbb11097cb26ce24ba01f42cedf517d437c2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-compat-seq-cst.c
@@ -3,6 +3,7 @@
    mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
index d469bf348d986ef9f51cfeeb106eda0b4700916a..939ad757462569a023a1dce9c8708c6d9f6891ea 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-relaxed.c
@@ -2,6 +2,7 @@
 /* Verify that store mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
index 3a275740401a67ec2257150e19856a074eb87ca6..bb97b8a6d5243f8363a45300a1082124c65a378a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/a-ztso-store-release.c
@@ -2,6 +2,7 @@
 /* Verify that store mappings match the PSABI doc's recommended mapping.  */
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c
index dae30c32e0167f95f8219caa3619efc531c67ba1..09089c8e980ee94c8d6708a79043d5eedd0a2040 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zaamo-preferred-over-zalrsc.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_zaamo } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c
index ca40a49f9b5716434a288568665329fa6f74d6cd..9d365fc07789e81da493ed98e83727094dd92f50 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zaamo-rvwmo-amo-add-int.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zaamo } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c
index 8ebdc61992ecb5512c271b582c318155e6ece352..56122bc1f059bd4b752114b289c33ae1b13b8f3e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zaamo-ztso-amo-add-int.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zaamo } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
index 58211207186cd428f6531ed9cdebdf5c82daa591..845e07e8866a4bd9d4369dc1156538c9269cd893 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-char.c
@@ -3,6 +3,7 @@
 /* { dg-options "-Wno-address-of-packed-member" } */
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler "\tamoadd.b" } } */
 /* { dg-final { scan-assembler "\tamoadd.b.aq" } } */
 /* { dg-final { scan-assembler "\tamoadd.b.rl" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
index c846ca48d72843968d7646521c9defb03d708199..43c79aca19b8dd246cd68f18246b54376bfdaee0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-all-amo-ops-short.c
@@ -3,6 +3,7 @@
 /* { dg-options "-Wno-address-of-packed-member" } */
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler "\tamoadd.h" } } */
 /* { dg-final { scan-assembler "\tamoadd.h.aq" } } */
 /* { dg-final { scan-assembler "\tamoadd.h.rl" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c
index a75c102196d353bbab2b19790032d2a924b29bbf..6acde263132f8f2cbb0cdf127887a859f7dc5159 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-char.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c
index 7755bb84784192bfe7e4be41e08be32a95a177e9..31eaa9feb18a81662e62b17f660a8cdcfe6938f4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-rvwmo-amo-add-short.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c
index d3d84fd30882ff8deb0ba4636859ae5b23a6cef9..851d81239f76994b5030e6eca76a75ba82decf2d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 
 _Bool b;
 void atomic_bool_cmpxchg()

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c
index a06e195c6d44ebc81ef413e0d15650c12162bd10..6c19c90a9f39fdcd85fa72ee4dc607028717a256 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-preferred-over-zalrsc.c
@@ -5,6 +5,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c
index bcd7477c6730273689985024eb4974ac3f6ae26d..f3c1a26166f8312cb98d0aa055c63f98c47f1230 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-char.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-add-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c
index c4e8c9cf3ef77fdd6a1c05bf725f63abd88d308d..b632094acfe69f1c18283f63b6d9e187e59f3790 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-ztso-amo-add-short.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-add-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c
index c7d6e7c578bc3952eb2a01d3239f74059d3e1386..82f9942b110549956710c84d477746ab2dbe37ff 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zabha.c
@@ -5,6 +5,7 @@
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_zabha } */
 /* { dg-remove-options riscv_zalrsc } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler "\tcall\t" } } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c
index d0cf14432fe2e21c701729091700981a3264b95d..9c77848c680708e48bc565c170616a43b6caa6a4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-char-requires-zacas.c
@@ -5,6 +5,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-remove-options riscv_zacas } */
 /* { dg-remove-options riscv_zalrsc } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler "\tcall\t" } } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c
index 9a995cca37fd038013a454ffcf6277de5ceb7388..7a8200eb08bce850c5ed1021e614b12945951dcf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-preferred-over-zalrsc.c
@@ -4,6 +4,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c
index b76385b4d2684442b9bd86646953d13276b4ba23..fea3c53757bcbefa6d6c3802f613a20ccaaa80b7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acq-rel.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\.aqrl\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c
index 62ecf7b5fff8be7f046a82f6944f554afeed9a94..ab67c49234d4d7048053893338ac0e2e6206ee1f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-acquire.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\.aq\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c
index 21c960c893b8bc3909df792639860b405524b78f..10dd0f7399f5def070c4cf602b1d756c3125152e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-relaxed.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c
index 6b4083376ee97c73b3672981c1843f2c39a1ee08..b4968c12a4cab0ba0f45d27927d7e065f1ca050b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-release.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\.rl\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c
index 289bdf44e9f27fb3d1752fd2e78661975cd198ce..4416d457c7e3e286b4db411b8a76f619f3cf9355 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-char-seq-cst.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\.aqrl\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c
index 99fd7577a481b60d19de748208dd80f7857754af..e4f5eeb47dca79d8589d6b782fd6ec222623a60b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping-no-fence.c
@@ -7,6 +7,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tfence" } } */
 
 void atomic_compare_exchange_weak_int_seq_cst_relaxed (int *bar, int *baz, int qux)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc
index c8d812991972c752860d89fc4bc6e90ebf61297b..a5058a273c2ad91976377cdbbe4a4e20fa5401e9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-compatability-mapping.cc
@@ -7,6 +7,7 @@
 /* { dg-options "-O3 -std=c++17" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 /*

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c
index 1b55c9349622909df3d3b3e1bff7fc949cd1dd15..fe01950607d0e1a119e1e1694e591579a22b4e90 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acq-rel.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\.aqrl\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c
index 8182360f24444033e4f90f02abce28e39b1f1e89..15afd4a8a2f5c80b75e0e8d5ca4025f5d0f6ba11 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-acquire.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\.aq\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c
index fb2a7b4f55af6b5de765ca34b55e4edc99bf0456..3e9c110a0f0de7276c1ba5a3a2f4834e8102f42c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-relaxed.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c
index 756f5cbe7d1a4870428abe18aed5f62c49976581..506eb02615a9eb2a7b9caac63188ff64a7569fbe 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-release.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\.rl\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c
index 1c5b4ac0e2fc2dabc26b72ece025be2a8e9add6a..6c7981b083293acb21276cb07b4630687eff787c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-int-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\.aqrl\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c
index 2987eb3615d2ba7205944c4775333a15d99c0ea7..287dd3fddba8eaf14616a714ec386b95d2541c8a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acq-rel.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\.aqrl\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c
index 505791090be270b75c13cb672e28f36d836cfe55..165142b7041a282a0dc61384b4c211d6b88140f4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-acquire.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\.aq\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c
index a85694e26c82dba73ad75f2f0f4f2696ef9a1ed6..4be9a566d0a0c2606fb197778be2ebbed7f4d872 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-relaxed.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c
index e8e9aae0265aab96343506541f453dabcc853af8..12d5b506721081884c66a0a3d6aaf72494360918 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-release.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\.rl\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c
index d676d378e06eced3aa5d70f40c4b19e8aa160f45..c219ea03b4e576be4c95a9f2bbd1f65592722839 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-rvwmo-compare-exchange-short-seq-cst.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\.aqrl\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c
index 183dc4020c7caf740b36d7b7dfdbceedff3a805a..9ede267eea25f43d638ce91da41e930d3339d07f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-char.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.b\t" 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c
index 2712eff51071d5e1815e39659229b6b4ecb7e6b2..65b6e392fcf09596bd2b8f50528cf17e02ab46dc 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping-no-fence.c
@@ -7,6 +7,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tfence" } } */
 
 void atomic_compare_exchange_weak_int_seq_cst_relaxed (int *bar, int *baz, int qux)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc
index 560172bfbed8258029d91ea768d320cbed3d0d61..8556837793c037fd2b11dbceb7c460ca8ce92d21 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-compatability-mapping.cc
@@ -7,6 +7,7 @@
 /* { dg-options "-O3 -std=c++17" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 /*

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c
index 1ee6cc202184e9fc9fc44d9aad0fea9f2812efbf..766ae162253b30e93cf4fcf36d3c5a091eb9f03c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c
index 2c332623a954ab0b1bdaa11bafa5678f3b537715..6d2a17f919965c7590f55e1616f9221776736a94 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-int.c
@@ -3,6 +3,7 @@
 /* { dg-options "-O3" } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.w\t" 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c
index 1938448183caa08c46609276719562ffd871c8fa..7ab8ce0e98fbfc68f0b144e09bc70c8bb530f74a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short-seq-cst.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\t" 2 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c
index 69fe5ae3eacd3e2034a4adc6185e7d932c15e4b6..3089e68ab7140f8d39fe6e5f46f4d8c55f035213 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zacas-ztso-compare-exchange-short.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zabha } */
 /* { dg-add-options riscv_zacas } */
 /* { dg-add-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-not "\tlr\.w" } } */
 /* { dg-final { scan-assembler-not "\tsc\.w" } } */
 /* { dg-final { scan-assembler-times "amocas\.h\t" 8 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c
new file mode 100644 (file)
index 0000000..aea6bc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-acquire.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_acquire:
+**     l[wd].aq\t[atx][0-9]+,0\(a0\)
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_acquire (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_int_acquire:
+**     lw.aq\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_acquire (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_short_acquire:
+**     lh.aq\t[atx][0-9]+,0\(a0\)
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_acquire (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_char_acquire:
+**     lb.aq\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_acquire (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_bool_acquire:
+**     lb.aq\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_acquire (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c
new file mode 100644 (file)
index 0000000..eee5f8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_relaxed:
+**     l[wd]\t[atx][0-9]+,0\(a0\)
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_relaxed (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_int_relaxed:
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_relaxed (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_short_relaxed:
+**     lh\t[atx][0-9]+,0\(a0\)
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_relaxed (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_char_relaxed:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_relaxed (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_bool_relaxed:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c
new file mode 100644 (file)
index 0000000..54ad19b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-load-seq-cst.c
@@ -0,0 +1,72 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_seq_cst:
+**     fence\trw,rw
+**     l[wd]\t[atx][0-9]+,0\(a0\)
+**     fence\tr,rw
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_seq_cst (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_int_seq_cst:
+**     fence\trw,rw
+**     lw\t[atx][0-9]+,0\(a0\)
+**     fence\tr,rw
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_seq_cst (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_short_seq_cst:
+**     fence\trw,rw
+**     lh\t[atx][0-9]+,0\(a0\)
+**     fence\tr,rw
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_seq_cst (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_char_seq_cst:
+**     fence\trw,rw
+**     lb\t[atx][0-9]+,0\(a0\)
+**     fence\tr,rw
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_seq_cst (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_bool_seq_cst:
+**     fence\trw,rw
+**     lb\t[atx][0-9]+,0\(a0\)
+**     fence\tr,rw
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
new file mode 100644 (file)
index 0000000..7f40d44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-compat-seq-cst.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended compatibility
+   mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_seq_cst:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd].rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_seq_cst (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_int_seq_cst:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_seq_cst (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_short_seq_cst:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_seq_cst (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_char_seq_cst:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_seq_cst (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_bool_seq_cst:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
new file mode 100644 (file)
index 0000000..d0127e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_relaxed:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd]\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_relaxed (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_int_relaxed:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_relaxed (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_short_relaxed:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_relaxed (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_char_relaxed:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_relaxed (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_bool_relaxed:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
new file mode 100644 (file)
index 0000000..6174718
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-rvwmo-store-release.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-remove-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_release:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd].rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_release (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_int_release:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_release (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_short_release:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_release (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_char_release:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_release (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_bool_release:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_release (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-acquire.c
new file mode 100644 (file)
index 0000000..2e71ea3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-acquire.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_acquire:
+**     l[wd]\t[atx][0-9]+,0\(a0\)
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_acquire (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_int_acquire:
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_acquire (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_short_acquire:
+**     lh\t[atx][0-9]+,0\(a0\)
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_acquire (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_char_acquire:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_acquire (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}
+
+/*
+** atomic_load_bool_acquire:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_acquire (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_ACQUIRE);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c
new file mode 100644 (file)
index 0000000..ce2c415
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_relaxed:
+**     l[wd]\t[atx][0-9]+,0\(a0\)
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_relaxed (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_int_relaxed:
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_relaxed (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_short_relaxed:
+**     lh\t[atx][0-9]+,0\(a0\)
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_relaxed (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_char_relaxed:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_relaxed (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_load_bool_relaxed:
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_RELAXED);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c
new file mode 100644 (file)
index 0000000..70038f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-load-seq-cst.c
@@ -0,0 +1,67 @@
+/* { dg-do compile } */
+/* Verify that load mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_load_long_seq_cst:
+**     fence\trw,rw
+**     l[wd]\t[atx][0-9]+,0\(a0\)
+**     s[wd]\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_long_seq_cst (long* bar, long* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_int_seq_cst:
+**     fence\trw,rw
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_int_seq_cst (int* bar, int* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_short_seq_cst:
+**     fence\trw,rw
+**     lh\t[atx][0-9]+,0\(a0\)
+**     sh\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_short_seq_cst (short* bar, short* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_char_seq_cst:
+**     fence\trw,rw
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_char_seq_cst (char* bar, char* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_load_bool_seq_cst:
+**     fence\trw,rw
+**     lb\t[atx][0-9]+,0\(a0\)
+**     sb\t[atx][0-9]+,0\(a1\)
+**     ret
+*/
+void atomic_load_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+  __atomic_load(bar, baz, __ATOMIC_SEQ_CST);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
new file mode 100644 (file)
index 0000000..085f94e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-compat-seq-cst.c
@@ -0,0 +1,63 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended compatibility
+   mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_seq_cst:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd].rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_seq_cst (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_int_seq_cst:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_seq_cst (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_short_seq_cst:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_seq_cst (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_char_seq_cst:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_seq_cst (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}
+
+/*
+** atomic_store_bool_seq_cst:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb.rl\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_seq_cst (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_SEQ_CST);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
new file mode 100644 (file)
index 0000000..cb68849
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-relaxed.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_relaxed:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd]\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_relaxed (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_int_relaxed:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_relaxed (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_short_relaxed:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_relaxed (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_char_relaxed:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_relaxed (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}
+
+/*
+** atomic_store_bool_relaxed:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_relaxed (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELAXED);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c
new file mode 100644 (file)
index 0000000..b5cc2e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalasr-ztso-store-release.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* Verify that store mappings match the PSABI doc's recommended mapping.  */
+/* { dg-options "-O3" } */
+/* { dg-add-options riscv_zalasr } */
+/* { dg-add-options riscv_ztso } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** atomic_store_long_release:
+**     l[wd]\t[atx][0-9]+,0\(a1\)
+**     s[wd]\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_long_release (long* bar, long* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_int_release:
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_int_release (int* bar, int* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_short_release:
+**     lhu\t[atx][0-9]+,0\(a1\)
+**     sh\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_short_release (short* bar, short* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_char_release:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_char_release (char* bar, char* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}
+
+/*
+** atomic_store_bool_release:
+**     lbu\t[atx][0-9]+,0\(a1\)
+**     sb\t[atx][0-9]+,0\(a0\)
+**     ret
+*/
+void atomic_store_bool_release (_Bool* bar, _Bool* baz)
+{
+  __atomic_store(bar, baz, __ATOMIC_RELEASE);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c
index 0dfe816ba29134719cfd5597eee0ee225220b9cf..c0e9673925b99e3009a7475ff563501d71944db2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_zaamo } */
 /* { dg-remove-options riscv_ztso } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c
index 9a5616f891663532b3dcd4f9ba374ecd4de1b04e..621c79ac32c0ad26f994fb56aa06a4b80a36d76b 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire-release.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* Mixed mappings need to be unioned.  */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c
index a24234855e9966cd9cd46b5e7b0ce94f94c3fe02..b449607553ee64d445089a6ce16505440bc42aaa 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-acquire.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c
index 18f53c83a387f771f021be9da66bf2d8e5390734..63bb275def1ae3670bf98875e0b3e24a9f35097f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-consume.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c
index c7a43ecd323a565aa534b6733989359e918a6435..40dcdf6be8c640fbdcc666550477d5ccf259d582 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-relaxed.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c
index 302fca2ca1711f47d2cdb68984ac14758ee63e97..9161f2acc11a950b0abaa5f338d33b0c6fa137e2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-release.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c
index e62002d267ac91fa2de343a65df7759870d2408e..769ce56d9a203753d54dd0a1378649bf22af2a95 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst-relaxed.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c
index c047d509aafed7d67ef90bc321c6346d7bbf95d5..55a13e1268004d32049b521350473cce94696762 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-compare-exchange-int-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c
index 33b70acb15c01bfca8884ae6dc27c22c510aaa7e..c453115362ea3c5d618e22573a3bc8890d33dd83 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acq-rel.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c
index e173296bcfce2455034fb78f44e330e5b56889fd..7eae408a6b435d8d60a28d71fb76d3e8d5664b45 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-acquire.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aq\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c
index f544d67721976273e0f6584d957836cdbc9eeac7..6ded40d5a18709c0588abcdaba613b9f8300301f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-relaxed.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c
index bb34873feeb2db0a1f88b87a53c7f4be37646013..919057bdd6db5132fafc13a7a69fc53eb2ab9742 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-release.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c
index d8991ee1a84e6fbb86e7fba0141ff16fa606e355..4aec4f259aabc68389ea09348ca5b1c2ccbf1e46 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-subword-amo-add-char-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-remove-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c
index 658b0404b9725cac728249e6ecdeb4a834a43bc8..6573b3a64593718cd1ed10adb9bf3c2d5c8dc16d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zaamo } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
 /* { dg-final { check-function-bodies "**" "" } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c
index 496af8bfd7df6528c555d42302c5ee92e3857f09..1a9a8e4a36a152ca5bbb0528ebd9a283ab1f7067 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire-release.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c
index 737e3eb3d684749a7faa7aa6e8888ffcdf712d84..b9a92d39f8a2a30d661f677042f8522c67eabd45 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-acquire.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c
index 51b3b5a8dc7332854a9514d849781472432d5270..0ce1d3eefc2d806fdb1aa0f881966df41cb75166 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-consume.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c
index 9a41410a57bf59280d06cda5bde6534f7f59b398..1aba82e52864b9c4b8346bfa80dea4e2f9efd5ac 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-relaxed.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c
index ee778a760d12cb350711007ab28e7a0ba4993fff..2bf0cc16b3359d33bb3418ba755245bdba783e43 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-release.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c
index 6fbe943b31692f180b3efc0f57d027664f5e0d26..532cb18dda7df522678c76e60f01be7a8d55b0e1 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst-relaxed.c
@@ -4,6 +4,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c
index a361c10086d57e40681e241154e14f86758b1a17..559f5a18866215f3c787bca36a51b492cbfb390d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-compare-exchange-int-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zacas } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c
index 7c9187e52b5cdc02c531d3a79069f45042280ff2..ff3a5f790a3e3ec6df5b573f22779e686db147bf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acq-rel.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c
index 675043f9c6105499e80d5e78daa7d3ecc4741764..1828b47c4d8d0b4d383c9a811d97d626bf0b3f16 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-acquire.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c
index 7bf9eb0a7f79d9831b8b01b39c0f1d1aeb987a64..3b76458b7b9b2024f9c5a95bd2dbea034de7ed1c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-relaxed.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c
index 6b78ce74b00cc22c0aa564d670df4ae01c763053..1a81054cc02b37daa75028573633869b882936b0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-release.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w\t" 1 } } */
 

diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c
index 14fadf1e3fe7351d89a5350104c4562513c73d5b..b6eacb725728a96f68c2676a10531db651ab0dab 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-subword-amo-add-char-seq-cst.c
@@ -3,6 +3,7 @@
 /* { dg-add-options riscv_zalrsc } */
 /* { dg-add-options riscv_ztso } */
 /* { dg-remove-options riscv_zabha } */
+/* { dg-remove-options riscv_zalasr } */
 /* { dg-final { scan-assembler-times "lr.w.aqrl\t" 1 } } */
 /* { dg-final { scan-assembler-times "sc.w.rl\t" 1 } } */
 

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 9912c6df233d0540cb8fd70e90be17b30e08897a..373a61f4d5719e51da82dc1618a37f6ecd188612 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -2104,6 +2104,16 @@ proc check_effective_target_riscv_zacas { } {
     }]
 }
 
+# Return 1 if the target arch supports the atomic-acquire and load-release extension, 0 otherwise.
+# Cache the result.
+proc check_effective_target_riscv_zalasr { } {
+    return [check_no_compiler_messages riscv_ext_zalasr assembly {
+       #ifndef __riscv_zalasr
+       #error "Not __riscv_zalasr"
+       #endif
+    }]
+}
+
 # Return 1 if the target arch supports the double precision floating point
 # extension, 0 otherwise.  Cache the result.
 
@@ -2528,7 +2538,7 @@ proc check_effective_target_riscv_v_misalign_ok { } {
 proc riscv_get_arch { } {
     set gcc_march ""
     # ??? do we neeed to add more extensions to the list below?
-    foreach ext { i e m a f d q c b v zicsr zifencei zfh zba zbb zbc zbkb zbkc zbs zvbb zvfh ztso zaamo zalrsc zabha zacas } {
+    foreach ext { i e m a f d q c b v zicsr zifencei zfh zba zbb zbc zbkb zbkc zbs zvbb zvfh ztso zaamo zalrsc zalasr zabha zacas } {
        if { [check_no_compiler_messages  riscv_ext_$ext assembly [string map [list DEF __riscv_$ext] {
                #ifndef DEF
                #error "Not DEF"
@@ -2725,6 +2735,14 @@ proc remove_options_for_riscv_zalrsc { flags } {
     return $modified_flags
 }
 
+proc add_options_for_riscv_zalasr { flags } {
+    return [add_options_for_riscv_z_ext zalasr $flags]
+}
+
+proc remove_options_for_riscv_zalasr { flags } {
+    return [remove_options_for_riscv_z_ext zalasr $flags]
+}
+
 proc add_options_for_riscv_zabha { flags } {
     return [add_options_for_riscv_z_ext zabha $flags]
 }