drm/amd/display: Remove unnecessary Freesync w/a from DCN32

[Why/How]
A workaround was previously used for certain Freesync cases that would
override the vstartup_start value from DML to position the SDP
correctly. This is no longer needed in DCN32 and above, so remove the
workaround.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index e29497204df7602e8bd4cc6100265ee550c65789..eb199215d298e2e98e8afd6d138ee041e598d294 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -1610,38 +1610,6 @@ static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
        return false;
 }
 
-static void dcn20_adjust_freesync_v_startup(const struct dc_crtc_timing *dc_crtc_timing, int *vstartup_start)
-{
-       struct dc_crtc_timing patched_crtc_timing;
-       uint32_t asic_blank_end   = 0;
-       uint32_t asic_blank_start = 0;
-       uint32_t newVstartup      = 0;
-
-       patched_crtc_timing = *dc_crtc_timing;
-
-       if (patched_crtc_timing.flags.INTERLACE == 1) {
-               if (patched_crtc_timing.v_front_porch < 2)
-                       patched_crtc_timing.v_front_porch = 2;
-       } else {
-               if (patched_crtc_timing.v_front_porch < 1)
-                       patched_crtc_timing.v_front_porch = 1;
-       }
-
-       /* blank_start = frame end - front porch */
-       asic_blank_start = patched_crtc_timing.v_total -
-                                       patched_crtc_timing.v_front_porch;
-
-       /* blank_end = blank_start - active */
-       asic_blank_end = asic_blank_start -
-                                       patched_crtc_timing.v_border_bottom -
-                                       patched_crtc_timing.v_addressable -
-                                       patched_crtc_timing.v_border_top;
-
-       newVstartup = asic_blank_end + (patched_crtc_timing.v_total - asic_blank_start);
-
-       *vstartup_start = ((newVstartup > *vstartup_start) ? newVstartup : *vstartup_start);
-}
-
 static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
                                       display_e2e_pipe_params_st *pipes,
                                       int pipe_cnt, int vlevel)
@@ -1756,11 +1724,6 @@ static void dcn32_calculate_dlg_params(struct dc *dc, struct dc_state *context,
                        }
                }
 
-               if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
-                       dcn20_adjust_freesync_v_startup(
-                               &context->res_ctx.pipe_ctx[i].stream->timing,
-                               &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
-
                pipe_idx++;
        }
        /* If DCN isn't making memory requests we can allow pstate change and lower clocks */