arm64: versal-net: Move board_early_init_r clock setup to mach code

board_early_init_r() programmed the IOU switch clock and the system
timestamp counter directly with readl()/writel() in board code. This is
SoC register setup rather than board policy, and the same block is
duplicated across the Xilinx SoCs.

Move it into versal_net_timer_setup() in arch/arm/mach-versal-net so the
board hook only keeps the EL3 guard and calls the helper.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://patch.msgid.link/10dd9f35d03be0402ce13475f20b2cd3761189a6.1782219202.git.michal.simek@amd.com

diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c
index 78ead1f45f69555d9e1bd9c1552de01164cbbce1..bce66124c47b3a7bc2bfb2d2c564f6f835f15a08 100644 (file)
--- a/arch/arm/mach-versal-net/cpu.c
+++ b/arch/arm/mach-versal-net/cpu.c
@@ -7,6 +7,8 @@
  */
 
 #include <init.h>
+#include <log.h>
+#include <time.h>
 #include <asm/armv8/mmu.h>
 #include <asm/cache.h>
 #include <asm/global_data.h>
@@ -88,6 +90,47 @@ u64 get_page_table_size(void)
        return 0x14000;
 }
 
+void versal_net_timer_setup(void)
+{
+       u32 val;
+
+       debug("iou_switch ctrl div0 %x\n",
+             readl(&crlapb_base->iou_switch_ctrl));
+
+       writel(IOU_SWITCH_CTRL_CLKACT_BIT |
+              (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
+              &crlapb_base->iou_switch_ctrl);
+
+       /* Global timer init - Program time stamp reference clk */
+       val = readl(&crlapb_base->timestamp_ref_ctrl);
+       val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
+       writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+       debug("ref ctrl 0x%x\n",
+             readl(&crlapb_base->timestamp_ref_ctrl));
+
+       /* Clear reset of timestamp reg */
+       writel(0, &crlapb_base->rst_timestamp);
+
+       /*
+        * Program freq register in System counter and
+        * enable system counter.
+        */
+       writel(CONFIG_COUNTER_FREQUENCY,
+              &iou_scntr_secure->base_frequency_id_register);
+
+       debug("counter val 0x%x\n",
+             readl(&iou_scntr_secure->base_frequency_id_register));
+
+       writel(IOU_SCNTRS_CONTROL_EN,
+              &iou_scntr_secure->counter_control_register);
+
+       debug("scntrs control 0x%x\n",
+             readl(&iou_scntr_secure->counter_control_register));
+       debug("timer 0x%llx\n", get_ticks());
+       debug("timer 0x%llx\n", get_ticks());
+}
+
 U_BOOT_DRVINFO(soc_xilinx_versal_net) = {
        .name = "soc_xilinx_versal_net",
 };

diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h
index 23374d10a6b4705cea53a19e689f94a5e497cffd..33253ca88bfedbfdc4751ffb4757472d4c469bac 100644 (file)
--- a/arch/arm/mach-versal-net/include/mach/sys_proto.h
+++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h
@@ -7,3 +7,5 @@
 #include <linux/build_bug.h>
 
 void mem_map_fill(void);
+/* EL3 clock/timer register setup, called from board_early_init_r() */
+void versal_net_timer_setup(void);

diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 65b2a451ad7a36b8a2c5a5c3ccd930d93bffe456..a40039a1dc8e6bc183b70e624576b6d802031bd6 100644 (file)
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -148,46 +148,10 @@ int board_early_init_f(void)
 
 int board_early_init_r(void)
 {
-       u32 val;
-
        if (current_el() != 3)
                return 0;
 
-       debug("iou_switch ctrl div0 %x\n",
-             readl(&crlapb_base->iou_switch_ctrl));
-
-       writel(IOU_SWITCH_CTRL_CLKACT_BIT |
-              (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
-              &crlapb_base->iou_switch_ctrl);
-
-       /* Global timer init - Program time stamp reference clk */
-       val = readl(&crlapb_base->timestamp_ref_ctrl);
-       val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
-       writel(val, &crlapb_base->timestamp_ref_ctrl);
-
-       debug("ref ctrl 0x%x\n",
-             readl(&crlapb_base->timestamp_ref_ctrl));
-
-       /* Clear reset of timestamp reg */
-       writel(0, &crlapb_base->rst_timestamp);
-
-       /*
-        * Program freq register in System counter and
-        * enable system counter.
-        */
-       writel(CONFIG_COUNTER_FREQUENCY,
-              &iou_scntr_secure->base_frequency_id_register);
-
-       debug("counter val 0x%x\n",
-             readl(&iou_scntr_secure->base_frequency_id_register));
-
-       writel(IOU_SCNTRS_CONTROL_EN,
-              &iou_scntr_secure->counter_control_register);
-
-       debug("scntrs control 0x%x\n",
-             readl(&iou_scntr_secure->counter_control_register));
-       debug("timer 0x%llx\n", get_ticks());
-       debug("timer 0x%llx\n", get_ticks());
+       versal_net_timer_setup();
 
        return 0;
 }