powercap: intel_rapl: Do not change CLAMPING bit if ENABLE bit cannot be changed

commit 964209202ebe1569c858337441e87ef0f9d71416 upstream.

PL1 cannot be disabled on some platforms. The ENABLE bit is still set
after software clears it. This behavior leads to a scenario where, upon
user request to disable the Power Limit through the powercap sysfs, the
ENABLE bit remains set while the CLAMPING bit is inadvertently cleared.

According to the Intel Software Developer's Manual, the CLAMPING bit,
"When set, allows the processor to go below the OS requested P states in
order to maintain the power below specified Platform Power Limit value."

Thus this means the system may operate at higher power levels than
intended on such platforms.

Enhance the code to check ENABLE bit after writing to it, and stop
further processing if ENABLE bit cannot be changed.

Reported-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Fixes: 2d281d8196e3 ("PowerCap: Introduce Intel RAPL power capping driver")
Cc: All applicable <stable@vger.kernel.org>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Link: https://patch.msgid.link/20250619071340.384782-1-rui.zhang@intel.com
[ rjw: Use str_enabled_disabled() instead of open-coded equivalent ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/powercap/intel_rapl_common.c b/drivers/powercap/intel_rapl_common.c
index 5e793b80fd6b6b14ee720ea90cff012e5d57c99f..c3de52e78e016632f1a483b2b897e339682b5368 100644 (file)
--- a/drivers/powercap/intel_rapl_common.c
+++ b/drivers/powercap/intel_rapl_common.c
@@ -340,12 +340,28 @@ static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
 {
        struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
        struct rapl_defaults *defaults = get_defaults(rd->rp);
+       u64 val;
        int ret;
 
        cpus_read_lock();
        ret = rapl_write_pl_data(rd, POWER_LIMIT1, PL_ENABLE, mode);
-       if (!ret && defaults->set_floor_freq)
+       if (ret)
+               goto end;
+
+       ret = rapl_read_pl_data(rd, POWER_LIMIT1, PL_ENABLE, false, &val);
+       if (ret)
+               goto end;
+
+       if (mode != val) {
+               pr_debug("%s cannot be %s\n", power_zone->name,
+                        str_enabled_disabled(mode));
+               goto end;
+       }
+
+       if (defaults->set_floor_freq)
                defaults->set_floor_freq(rd, mode);
+
+end:
        cpus_read_unlock();
 
        return ret;