RISC-V: Add test for vec_duplicate + vmsgtu.vv combine with GR2VR cost 0, 1 and 15

Add asm dump check and run test for vec_duplicate + vmsgtu.vv
combine to vmsgtu.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
	for vmsgtu.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test
	helper macro.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
	data for run test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index 7e3ad1f70fc01e27cc92143725e92de585efecd8..2cae55389b3a93109e9a72b688b40e5d015724ca 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -39,3 +39,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 36d8a6434ca561011d3cdcc84a26258e0d8ef4a0..946126e1fb9c3725427d966f3c8814cc18ff8bfd 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsleu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index aab16016dd450bf8f3c37f3cc6d1a582a4237ebf..63f1fae266fc91a3b208173755144b44642d6485 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -43,3 +43,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsleu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index dcea470dc5f43096cb377742442018c25138ba96..add5a7255ccad6eb31f3d345890d53480445ba04 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -30,3 +30,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmsleu.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmsgtu.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index a3162b1626a4ba1ad8228198a5e1f11a605045e6..735b9c094d7f6cf96daf64f6044a75bb29d6c11c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
 /* { dg-final { scan-assembler-not {vmsltu.vx} } } */
 /* { dg-final { scan-assembler-not {vmsleu.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index e90cdf652af4bc664a763c1f281fef313f596f2a..576d7c188453f91e3645bb98b4b8db13e8cfe9d4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
 /* { dg-final { scan-assembler-not {vmsltu.vx} } } */
 /* { dg-final { scan-assembler-not {vmsleu.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 79a2b3fb7432fb0f37fa7f82b7fa137410175bd1..ce14846b987217b76312fe71266fc7a11b7abb3a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
 /* { dg-final { scan-assembler-not {vmsltu.vx} } } */
 /* { dg-final { scan-assembler-not {vmsleu.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index 989e101389069416c552cf38870ade5b51bf4d67..8b5718feb4def352346f333d7d7a63b774a89d89 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -30,3 +30,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
 /* { dg-final { scan-assembler-not {vmsltu.vx} } } */
 /* { dg-final { scan-assembler-not {vmsleu.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index ae2216a75fef6a8486833bae98c20ff9d51f9319..e2d04a5df787e45f3eec427aec06f98c40ba242a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
 /* { dg-final { scan-assembler-not {vmsltu.vx} } } */
 /* { dg-final { scan-assembler-not {vmsleu.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 348f33e9a7975136494afd4493ca09e8f8fad30a..46f5a05b1b2a62e36220f03df21fd6a001324870 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
 /* { dg-final { scan-assembler-not {vmsltu.vx} } } */
 /* { dg-final { scan-assembler-not {vmsleu.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 85f9085ca62fbccc1f3a2c089450002b726eb71b..0d73725f491e78cfa89e44614f48482695844b11 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -40,3 +40,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
 /* { dg-final { scan-assembler-not {vmsltu.vx} } } */
 /* { dg-final { scan-assembler-not {vmsleu.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index 82e5389f7d3b2e6d62bbc6a8343b05aa610e4c2d..a98cc802c5502d9dd1a480d6be039c83e5add0f4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -30,3 +30,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmsne.vx} } } */
 /* { dg-final { scan-assembler-not {vmsltu.vx} } } */
 /* { dg-final { scan-assembler-not {vmsleu.vx} } } */
+/* { dg-final { scan-assembler-not {vmsgtu.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
index 149787ae4761d80bb1dbe717234eebea7da6fe0b..ff6b7f6542dbcdd8f3546da17fdfed835e61c605 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h
@@ -428,6 +428,7 @@ DEF_AVG_CEIL(int32_t, int64_t)
   DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne)                            \
   DEF_VX_BINARY_CASE_0_WRAP(T, <, ltu)                            \
   DEF_VX_BINARY_CASE_0_WRAP(T, <=, leu)                           \
+  DEF_VX_BINARY_CASE_0_WRAP(T, >, gtu)                            \
   DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max)           \
   DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max)           \
   DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min)           \

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 8e66c22a23530c19d875e671aef05db1169e93ab..952c8b49ecd2ca7a9f017f1316d4bf697cb46cc0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -6974,4 +6974,140 @@ int64_t TEST_BINARY_DATA(int64_t, le)[][3][N] =
   },
 };
 
+uint8_t TEST_BINARY_DATA(uint8_t, gtu)[][3][N] =
+{
+  {
+    { 127 },
+    {
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+      127, 127, 127, 127,
+      128, 128, 128, 128,
+    },
+    {
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { 255 },
+    {
+         0,   0,   0,   0,
+         1,   1,   1,   1,
+         2,   2,   2,   2,
+       255, 255, 255, 255,
+    },
+    {
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+    },
+  },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, gtu)[][3][N] =
+{
+  {
+    { 32767 },
+    {
+          0,     0,     0,     0,
+          1,     1,     1,     1,
+      32767, 32767, 32767, 32767,
+      32768, 32768, 32768, 32768,
+    },
+    {
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { 65535 },
+    {
+           0,     0,     0,     0,
+           1,     1,     1,     1,
+           2,     2,     2,     2,
+       65535, 65535, 65535, 65535,
+    },
+    {
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+    },
+  },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, gtu)[][3][N] =
+{
+  {
+    { 2147483647 },
+    {
+               0,          0,          0,          0,
+               1,          1,          1,          1,
+      2147483647, 2147483647, 2147483647, 2147483647,
+      2147483648, 2147483648, 2147483648, 2147483648,
+    },
+    {
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { 4294967295 },
+    {
+                0,          0,          0,          0,
+                1,          1,          1,          1,
+                2,          2,          2,          2,
+       4294967295, 4294967295, 4294967295, 4294967295,
+    },
+    {
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+    },
+  },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, gtu)[][3][N] =
+{
+  {
+    { 9223372036854775807ull },
+    {
+                           0,                      0,                      0,                      0,
+                           1,                      1,                      1,                      1,
+      9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull,
+      9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull,
+    },
+    {
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+        0,   0,   0,   0,
+        1,   1,   1,   1,
+    },
+  },
+  {
+    { 18446744073709551615ull },
+    {
+                             0,                       0,                       0,                       0,
+                             1,                       1,                       1,                       1,
+                             2,                       2,                       2,                       2,
+       18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull,
+    },
+    {
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+         0,   0,   0,   0,
+    },
+  },
+};
+
 #endif

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c
new file mode 100644 (file)
index 0000000..8fcc304
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint16_t
+#define NAME gtu
+
+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c
new file mode 100644 (file)
index 0000000..ed269c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint32_t
+#define NAME gtu
+
+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c
new file mode 100644 (file)
index 0000000..11752b4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint64_t
+#define NAME gtu
+
+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c
new file mode 100644 (file)
index 0000000..78c5835
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    uint8_t
+#define NAME gtu
+
+DEF_VX_BINARY_CASE_0_WRAP(T, >, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n)
+
+#include "vx_binary_run.h"