clk: renesas: rzg2l: Deassert reset on assert timeout

[ Upstream commit 0b0201f259e1158a875c5fd01adf318ae5d32352 ]

If the assert() fails due to timeout error, set the reset register bit
back to deasserted state. This change is needed especially for handling
assert error in suspend() callback that expect the device to be in
operational state in case of failure.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260108123433.104464-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 64d1ef6e4c943c910f5b43b330f66f9d91898326..c20ea1212b360fec81f17becc7a0388b3d248953 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1647,6 +1647,7 @@ static int __rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
        u32 mask = BIT(info->resets[id].bit);
        s8 monbit = info->resets[id].monbit;
        u32 value = mask << 16;
+       u32 mon;
        int ret;
 
        dev_dbg(rcdev->dev, "%s id:%ld offset:0x%x\n",
@@ -1667,10 +1668,10 @@ static int __rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
                return 0;
        }
 
-       ret = readl_poll_timeout_atomic(priv->base + reg, value,
-                                       assert == !!(value & mask), 10, 200);
-       if (ret && !assert) {
-               value = mask << 16;
+       ret = readl_poll_timeout_atomic(priv->base + reg, mon,
+                                       assert == !!(mon & mask), 10, 200);
+       if (ret) {
+               value ^= mask;
                writel(value, priv->base + CLK_RST_R(info->resets[id].off));
        }