tools arch x86: Sync the msr-index.h copy with the kernel sources

To pick up the changes in:

  e93a93f11490992a ("KVM: x86: Virtualize AMD CPUID faulting")

That introduce these new entries in the string tables:

  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before.txt
  $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after.txt
  $ diff -u before.txt after.txt
  @@ -349,6 +349,7 @@
   	[0xc00102b2 - x86_AMD_V_KVM_MSRs_offset] = "AMD_CPPC_CAP2",
   	[0xc00102b3 - x86_AMD_V_KVM_MSRs_offset] = "AMD_CPPC_REQ",
   	[0xc00102b4 - x86_AMD_V_KVM_MSRs_offset] = "AMD_CPPC_STATUS",
  +	[0xc00102b5 - x86_AMD_V_KVM_MSRs_offset] = "AMD_CPPC_REQ2",
   	[0xc00102f0 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN_CTL",
   	[0xc00102f1 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PPIN",
   	[0xc0010300 - x86_AMD_V_KVM_MSRs_offset] = "AMD_SAMP_BR_FROM",

This addresses this perf build warning:

  Warning: Kernel ABI header differences:
    diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h

Please see tools/include/uapi/README for further details.

Cc: Jim Mattson <jmattson@google.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index eff29645719bc7c31cf09e8e5fbe626d369c8009..18c4be75e927197c1b6ab0c82a66f7546fdb1cde 100644 (file)
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -674,6 +674,9 @@
 #define MSR_AMD64_DC_CFG               0xc0011022
 #define MSR_AMD64_TW_CFG               0xc0011023
 
+#define MSR_AMD64_FP_CFG               0xc0011028
+#define MSR_AMD64_FP_CFG_ZEN1_DENORM_FIX_BIT   9
+
 #define MSR_AMD64_DE_CFG               0xc0011029
 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT   1
 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE      BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
@@ -698,6 +701,8 @@
 #define MSR_AMD64_IBSBRTARGET          0xc001103b
 #define MSR_AMD64_ICIBSEXTDCTL         0xc001103c
 #define MSR_AMD64_IBSOPDATA4           0xc001103d
+#define MSR_AMD64_IBSOPCTL2            0xc001103e
+#define MSR_AMD64_IBSFETCHCTL2         0xc001103f
 #define MSR_AMD64_IBS_REG_COUNT_MAX    8 /* includes MSR_AMD64_IBSBRTARGET */
 #define MSR_AMD64_SVM_AVIC_DOORBELL    0xc001011b
 #define MSR_AMD64_VM_PAGE_FLUSH                0xc001011e
@@ -765,12 +770,14 @@
 #define MSR_AMD_CPPC_CAP2              0xc00102b2
 #define MSR_AMD_CPPC_REQ               0xc00102b3
 #define MSR_AMD_CPPC_STATUS            0xc00102b4
+#define MSR_AMD_CPPC_REQ2              0xc00102b5
 
 /* Masks for use with MSR_AMD_CPPC_CAP1 */
 #define AMD_CPPC_LOWEST_PERF_MASK      GENMASK(7, 0)
 #define AMD_CPPC_LOWNONLIN_PERF_MASK   GENMASK(15, 8)
 #define AMD_CPPC_NOMINAL_PERF_MASK     GENMASK(23, 16)
 #define AMD_CPPC_HIGHEST_PERF_MASK     GENMASK(31, 24)
+#define AMD_CPPC_FLOOR_PERF_CNT_MASK   GENMASK_ULL(39, 32)
 
 /* Masks for use with MSR_AMD_CPPC_REQ */
 #define AMD_CPPC_MAX_PERF_MASK         GENMASK(7, 0)
@@ -778,6 +785,9 @@
 #define AMD_CPPC_DES_PERF_MASK         GENMASK(23, 16)
 #define AMD_CPPC_EPP_PERF_MASK         GENMASK(31, 24)
 
+/* Masks for use with MSR_AMD_CPPC_REQ2 */
+#define AMD_CPPC_FLOOR_PERF_MASK       GENMASK(7, 0)
+
 /* AMD Performance Counter Global Status and Control MSRs */
 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS      0xc0000300
 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL         0xc0000301
@@ -889,6 +899,7 @@
 #define MSR_K7_HWCR_IRPERF_EN_BIT      30
 #define MSR_K7_HWCR_IRPERF_EN          BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
 #define MSR_K7_HWCR_CPUID_USER_DIS_BIT 35
+#define MSR_K7_HWCR_CPUID_USER_DIS     BIT_ULL(MSR_K7_HWCR_CPUID_USER_DIS_BIT)
 #define MSR_K7_FID_VID_CTL             0xc0010041
 #define MSR_K7_FID_VID_STATUS          0xc0010042
 #define MSR_K7_HWCR_CPB_DIS_BIT                25