clk: qcom: videocc-glymur: Add video clock controller driver for Glymur

Add support for the video clock controller for video clients to be able
to request for videocc clocks on Glymur platform.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-4-8f7d8b4d8edd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 3bc60958d72150822fd35678cc1ee26559d6ae9c..f23280219d56436fd142a38ff22a219e431539a6 100644 (file)
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -55,6 +55,15 @@ config CLK_GLYMUR_TCSRCC
          Support for the TCSR clock controller on Glymur devices.
          Say Y if you want to use peripheral devices such as USB/PCIe/EDP.
 
+config CLK_GLYMUR_VIDEOCC
+       tristate "Glymur Video Clock Controller"
+       depends on ARM64 || COMPILE_TEST
+       select CLK_GLYMUR_GCC
+       help
+         Support for the video clock controller on Glymur devices.
+         Say Y if you want to support video devices and functionality such as
+         video encode and decode.
+
 config CLK_KAANAPALI_CAMCC
        tristate "Kaanapali Camera Clock Controller"
        depends on ARM64 || COMPILE_TEST

diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index d871d21b5dc9060ca25a3e82854495228f46fbf5..90ea21c3b7cf7956309648c4445ecf8fd61f23b0 100644 (file)
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
 obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
 obj-$(CONFIG_CLK_GLYMUR_GPUCC) += gpucc-glymur.o gxclkctl-kaanapali.o
 obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
+obj-$(CONFIG_CLK_GLYMUR_VIDEOCC) += videocc-glymur.o
 obj-$(CONFIG_CLK_KAANAPALI_CAMCC) += cambistmclkcc-kaanapali.o camcc-kaanapali.o
 obj-$(CONFIG_CLK_KAANAPALI_DISPCC) += dispcc-kaanapali.o
 obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o

diff --git a/drivers/clk/qcom/videocc-glymur.c b/drivers/clk/qcom/videocc-glymur.c
new file mode 100644 (file)
index 0000000..5dea01f
--- /dev/null
+++ b/drivers/clk/qcom/videocc-glymur.c
@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/qcom,glymur-videocc.h>
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+       DT_BI_TCXO,
+       DT_BI_TCXO_AO,
+       DT_SLEEP_CLK,
+};
+
+enum {
+       P_BI_TCXO,
+       P_SLEEP_CLK,
+       P_VIDEO_CC_PLL0_OUT_MAIN,
+};
+
+static const struct pll_vco taycan_eko_t_vco[] = {
+       { 249600000, 2500000000, 0 },
+};
+
+/* 720.0 MHz Configuration */
+static const struct alpha_pll_config video_cc_pll0_config = {
+       .l = 0x25,
+       .alpha = 0x8000,
+       .config_ctl_val = 0x25c400e7,
+       .config_ctl_hi_val = 0x0a8060e0,
+       .config_ctl_hi1_val = 0xf51dea20,
+       .user_ctl_val = 0x00000008,
+       .user_ctl_hi_val = 0x00000002,
+};
+
+static struct clk_alpha_pll video_cc_pll0 = {
+       .offset = 0x0,
+       .config = &video_cc_pll0_config,
+       .vco_table = taycan_eko_t_vco,
+       .num_vco = ARRAY_SIZE(taycan_eko_t_vco),
+       .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
+       .clkr = {
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "video_cc_pll0",
+                       .parent_data = &(const struct clk_parent_data) {
+                               .index = DT_BI_TCXO,
+                       },
+                       .num_parents = 1,
+                       .ops = &clk_alpha_pll_taycan_eko_t_ops,
+               },
+       },
+};
+
+static const struct parent_map video_cc_parent_map_0[] = {
+       { P_BI_TCXO, 0 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_0[] = {
+       { .index = DT_BI_TCXO },
+};
+
+static const struct parent_map video_cc_parent_map_1[] = {
+       { P_BI_TCXO, 0 },
+       { P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_1[] = {
+       { .index = DT_BI_TCXO },
+       { .hw = &video_cc_pll0.clkr.hw },
+};
+
+static const struct parent_map video_cc_parent_map_2[] = {
+       { P_SLEEP_CLK, 0 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_2[] = {
+       { .index = DT_SLEEP_CLK },
+};
+
+static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 video_cc_ahb_clk_src = {
+       .cmd_rcgr = 0x8018,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = video_cc_parent_map_0,
+       .freq_tbl = ftbl_video_cc_ahb_clk_src,
+       .clkr.hw.init = &(const struct clk_init_data) {
+               .name = "video_cc_ahb_clk_src",
+               .parent_data = video_cc_parent_data_0,
+               .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_shared_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
+       F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+       F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+       F(1098000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+       F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+       F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+       F(1965000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 video_cc_mvs0_clk_src = {
+       .cmd_rcgr = 0x8000,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = video_cc_parent_map_1,
+       .freq_tbl = ftbl_video_cc_mvs0_clk_src,
+       .clkr.hw.init = &(const struct clk_init_data) {
+               .name = "video_cc_mvs0_clk_src",
+               .parent_data = video_cc_parent_data_1,
+               .num_parents = ARRAY_SIZE(video_cc_parent_data_1),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_shared_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
+       F(32000, P_SLEEP_CLK, 1, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 video_cc_sleep_clk_src = {
+       .cmd_rcgr = 0x8120,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = video_cc_parent_map_2,
+       .freq_tbl = ftbl_video_cc_sleep_clk_src,
+       .clkr.hw.init = &(const struct clk_init_data) {
+               .name = "video_cc_sleep_clk_src",
+               .parent_data = video_cc_parent_data_2,
+               .num_parents = ARRAY_SIZE(video_cc_parent_data_2),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_shared_ops,
+       },
+};
+
+static struct clk_rcg2 video_cc_xo_clk_src = {
+       .cmd_rcgr = 0x80f8,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = video_cc_parent_map_0,
+       .freq_tbl = ftbl_video_cc_ahb_clk_src,
+       .clkr.hw.init = &(const struct clk_init_data) {
+               .name = "video_cc_xo_clk_src",
+               .parent_data = video_cc_parent_data_0,
+               .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_shared_ops,
+       },
+};
+
+static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
+       .reg = 0x809c,
+       .shift = 0,
+       .width = 4,
+       .clkr.hw.init = &(const struct clk_init_data) {
+               .name = "video_cc_mvs0_div_clk_src",
+               .parent_hws = (const struct clk_hw*[]) {
+                       &video_cc_mvs0_clk_src.clkr.hw,
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_regmap_div_ro_ops,
+       },
+};
+
+static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
+       .reg = 0x8060,
+       .shift = 0,
+       .width = 4,
+       .clkr.hw.init = &(const struct clk_init_data) {
+               .name = "video_cc_mvs0c_div2_div_clk_src",
+               .parent_hws = (const struct clk_hw*[]) {
+                       &video_cc_mvs0_clk_src.clkr.hw,
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_regmap_div_ro_ops,
+       },
+};
+
+static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
+       .reg = 0x80d8,
+       .shift = 0,
+       .width = 4,
+       .clkr.hw.init = &(const struct clk_init_data) {
+               .name = "video_cc_mvs1_div_clk_src",
+               .parent_hws = (const struct clk_hw*[]) {
+                       &video_cc_mvs0_clk_src.clkr.hw,
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_regmap_div_ro_ops,
+       },
+};
+
+static struct clk_branch video_cc_mvs0_clk = {
+       .halt_reg = 0x807c,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x807c,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x807c,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "video_cc_mvs0_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &video_cc_mvs0_div_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch video_cc_mvs0_freerun_clk = {
+       .halt_reg = 0x808c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x808c,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "video_cc_mvs0_freerun_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &video_cc_mvs0_div_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch video_cc_mvs0_shift_clk = {
+       .halt_reg = 0x8114,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x8114,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x8114,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "video_cc_mvs0_shift_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &video_cc_xo_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch video_cc_mvs0c_clk = {
+       .halt_reg = 0x804c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x804c,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "video_cc_mvs0c_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &video_cc_mvs0c_div2_div_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch video_cc_mvs0c_freerun_clk = {
+       .halt_reg = 0x805c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x805c,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "video_cc_mvs0c_freerun_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &video_cc_mvs0c_div2_div_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch video_cc_mvs0c_shift_clk = {
+       .halt_reg = 0x811c,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x811c,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x811c,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "video_cc_mvs0c_shift_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &video_cc_xo_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch video_cc_mvs1_clk = {
+       .halt_reg = 0x80b8,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x80b8,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x80b8,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "video_cc_mvs1_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &video_cc_mvs1_div_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch video_cc_mvs1_freerun_clk = {
+       .halt_reg = 0x80c8,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x80c8,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "video_cc_mvs1_freerun_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &video_cc_mvs1_div_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch video_cc_mvs1_shift_clk = {
+       .halt_reg = 0x8118,
+       .halt_check = BRANCH_HALT_VOTED,
+       .hwcg_reg = 0x8118,
+       .hwcg_bit = 1,
+       .clkr = {
+               .enable_reg = 0x8118,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data) {
+                       .name = "video_cc_mvs1_shift_clk",
+                       .parent_hws = (const struct clk_hw*[]) {
+                               &video_cc_xo_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct gdsc video_cc_mvs0c_gdsc = {
+       .gdscr = 0x8034,
+       .en_rest_wait_val = 0x2,
+       .en_few_wait_val = 0x2,
+       .clk_dis_wait_val = 0x6,
+       .pd = {
+               .name = "video_cc_mvs0c_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+       .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct gdsc video_cc_mvs0_gdsc = {
+       .gdscr = 0x8068,
+       .en_rest_wait_val = 0x2,
+       .en_few_wait_val = 0x2,
+       .clk_dis_wait_val = 0x6,
+       .pd = {
+               .name = "video_cc_mvs0_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+       .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+       .parent = &video_cc_mvs0c_gdsc.pd,
+};
+
+static struct gdsc video_cc_mvs1_gdsc = {
+       .gdscr = 0x80a4,
+       .en_rest_wait_val = 0x2,
+       .en_few_wait_val = 0x2,
+       .clk_dis_wait_val = 0x6,
+       .pd = {
+               .name = "video_cc_mvs1_gdsc",
+       },
+       .pwrsts = PWRSTS_OFF_ON,
+       .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
+};
+
+static struct clk_regmap *video_cc_glymur_clocks[] = {
+       [VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
+       [VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
+       [VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
+       [VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
+       [VIDEO_CC_MVS0_FREERUN_CLK] = &video_cc_mvs0_freerun_clk.clkr,
+       [VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr,
+       [VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
+       [VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
+       [VIDEO_CC_MVS0C_FREERUN_CLK] = &video_cc_mvs0c_freerun_clk.clkr,
+       [VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr,
+       [VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
+       [VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
+       [VIDEO_CC_MVS1_FREERUN_CLK] = &video_cc_mvs1_freerun_clk.clkr,
+       [VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr,
+       [VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
+       [VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
+       [VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
+};
+
+static struct gdsc *video_cc_glymur_gdscs[] = {
+       [VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
+       [VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
+       [VIDEO_CC_MVS1_GDSC] = &video_cc_mvs1_gdsc,
+};
+
+static const struct qcom_reset_map video_cc_glymur_resets[] = {
+       [VIDEO_CC_INTERFACE_BCR] = { 0x80dc },
+       [VIDEO_CC_MVS0_BCR] = { 0x8064 },
+       [VIDEO_CC_MVS0C_FREERUN_CLK_ARES] = { 0x805c, 2 },
+       [VIDEO_CC_MVS0C_BCR] = { 0x8030 },
+       [VIDEO_CC_MVS0_FREERUN_CLK_ARES] = { 0x808c, 2 },
+       [VIDEO_CC_MVS1_FREERUN_CLK_ARES] = { 0x80c8, 2 },
+       [VIDEO_CC_MVS1_BCR] = { 0x80a0 },
+};
+
+static struct clk_alpha_pll *video_cc_glymur_plls[] = {
+       &video_cc_pll0,
+};
+
+static u32 video_cc_glymur_critical_cbcrs[] = {
+       0x80e0, /* VIDEO_CC_AHB_CLK */
+       0x8138, /* VIDEO_CC_SLEEP_CLK */
+       0x8110, /* VIDEO_CC_XO_CLK */
+};
+
+static const struct regmap_config video_cc_glymur_regmap_config = {
+       .reg_bits = 32,
+       .reg_stride = 4,
+       .val_bits = 32,
+       .max_register = 0x9f54,
+       .fast_io = true,
+};
+
+static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap)
+{
+       /* Update CTRL_IN register */
+       regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0));
+}
+
+static struct qcom_cc_driver_data video_cc_glymur_driver_data = {
+       .alpha_plls = video_cc_glymur_plls,
+       .num_alpha_plls = ARRAY_SIZE(video_cc_glymur_plls),
+       .clk_cbcrs = video_cc_glymur_critical_cbcrs,
+       .num_clk_cbcrs = ARRAY_SIZE(video_cc_glymur_critical_cbcrs),
+       .clk_regs_configure = clk_glymur_regs_configure,
+};
+
+static struct qcom_cc_desc video_cc_glymur_desc = {
+       .config = &video_cc_glymur_regmap_config,
+       .clks = video_cc_glymur_clocks,
+       .num_clks = ARRAY_SIZE(video_cc_glymur_clocks),
+       .resets = video_cc_glymur_resets,
+       .num_resets = ARRAY_SIZE(video_cc_glymur_resets),
+       .gdscs = video_cc_glymur_gdscs,
+       .num_gdscs = ARRAY_SIZE(video_cc_glymur_gdscs),
+       .use_rpm = true,
+       .driver_data = &video_cc_glymur_driver_data,
+};
+
+static const struct of_device_id video_cc_glymur_match_table[] = {
+       { .compatible = "qcom,glymur-videocc" },
+       { }
+};
+MODULE_DEVICE_TABLE(of, video_cc_glymur_match_table);
+
+static int video_cc_glymur_probe(struct platform_device *pdev)
+{
+       return qcom_cc_probe(pdev, &video_cc_glymur_desc);
+}
+
+static struct platform_driver video_cc_glymur_driver = {
+       .probe = video_cc_glymur_probe,
+       .driver = {
+               .name = "videocc-glymur",
+               .of_match_table = video_cc_glymur_match_table,
+       },
+};
+
+module_platform_driver(video_cc_glymur_driver);
+
+MODULE_DESCRIPTION("QTI VIDEOCC Glymur Driver");
+MODULE_LICENSE("GPL");